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ORCIDBibTeX records: Harika Manem
@article{DBLP:journals/jetc/UddinMBMACR18,
author = {Mesbah Uddin and
Md. Badruddoja Majumder and
Karsten Beckmann and
Harika Manem and
Zahiruddin Alamgir and
Nathaniel C. Cady and
Garrett S. Rose},
title = {Design Considerations for Memristive Crossbar Physical Unclonable
Functions},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {14},
number = {1},
pages = {2:1--2:23},
year = {2018},
url = {https://doi.org/10.1145/3094414},
doi = {10.1145/3094414},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/UddinMBMACR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tetc/BeckmannMC17,
author = {Karsten Beckmann and
Harika Manem and
Nathaniel C. Cady},
title = {Performance Enhancement of a Time-Delay {PUF} Design by Utilizing
Integrated Nanoscale ReRAM Devices},
journal = {{IEEE} Trans. Emerg. Top. Comput.},
volume = {5},
number = {3},
pages = {304--316},
year = {2017},
url = {https://doi.org/10.1109/TETC.2016.2575448},
doi = {10.1109/TETC.2016.2575448},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tetc/BeckmannMC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/UddinMRBMAC16,
author = {Mesbah Uddin and
Md. Badruddoja Majumder and
Garrett S. Rose and
Karsten Beckmann and
Harika Manem and
Zahiruddin Alamgir and
Nathaniel C. Cady},
title = {Techniques for Improved Reliability in Memristive Crossbar {PUF} Circuits},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2016, Pittsburgh,
PA, USA, July 11-13, 2016},
pages = {212--217},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/ISVLSI.2016.33},
doi = {10.1109/ISVLSI.2016.33},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/UddinMRBMAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cisda/ManemBXCGC15,
author = {Harika Manem and
Karsten Beckmann and
Min Xu and
Robert Carroll and
Robert E. Geer and
Nathaniel C. Cady},
title = {An extendable multi-purpose 3D neuromorphic fabric using nanoscale
memristors},
booktitle = {2015 {IEEE} Symposium on Computational Intelligence for Security and
Defense Applications, {CISDA} 2015, Verona, NY, USA, May 26-28, 2015},
pages = {1--8},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/CISDA.2015.7208625},
doi = {10.1109/CISDA.2015.7208625},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cisda/ManemBXCGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/ManemRR12,
author = {Harika Manem and
Jeyavijayan Rajendran and
Garrett S. Rose},
title = {Design Considerations for Multilevel CMOS/Nano Memristive Memory},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {8},
number = {1},
pages = {6:1--6:22},
year = {2012},
url = {https://doi.org/10.1145/2093145.2093151},
doi = {10.1145/2093145.2093151},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/ManemRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pieee/RoseRMKP12,
author = {Garrett S. Rose and
Jeyavijayan Rajendran and
Harika Manem and
Ramesh Karri and
Robinson E. Pino},
title = {Leveraging Memristive Systems in the Construction of Digital Logic
Circuits},
journal = {Proc. {IEEE}},
volume = {100},
number = {6},
pages = {2033--2049},
year = {2012},
url = {https://doi.org/10.1109/JPROC.2011.2167489},
doi = {10.1109/JPROC.2011.2167489},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pieee/RoseRMKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/RajendranMKR12,
author = {Jeyavijayan Rajendran and
Harika Manem and
Ramesh Karri and
Garrett S. Rose},
title = {An Energy-Efficient Memristive Threshold Logic Circuit},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {4},
pages = {474--487},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.26},
doi = {10.1109/TC.2011.26},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/RajendranMKR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ManemRR12,
author = {Harika Manem and
Jeyavijayan Rajendran and
Garrett S. Rose},
title = {Stochastic Gradient Descent Inspired Training Technique for a CMOS/Nano
Memristive Trainable Threshold Gate Array},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {59-I},
number = {5},
pages = {1051--1060},
year = {2012},
url = {https://doi.org/10.1109/TCSI.2012.2190665},
doi = {10.1109/TCSI.2012.2190665},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ManemRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ManemR11,
author = {Harika Manem and
Garrett S. Rose},
title = {A read-monitored write circuit for 1T1M multi-level memristor memories},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {2938--2941},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5938207},
doi = {10.1109/ISCAS.2011.5938207},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ManemR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RajendranMKR11,
author = {Jeyavijayan Rajendran and
Harika Manem and
Ramesh Karri and
Garrett S. Rose},
title = {An Approach to Tolerate Process Related Variations in Memristor-Based
Applications},
booktitle = {{VLSI} Design 2011: 24th International Conference on {VLSI} Design,
{IIT} Madras, Chennai, India, 2-7 January 2011},
pages = {18--23},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/VLSID.2011.49},
doi = {10.1109/VLSID.2011.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RajendranMKR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ManemRHW10,
author = {Harika Manem and
Garrett S. Rose and
Xiaoli He and
Wei Wang},
editor = {R. Iris Bahar and
Fabrizio Lombardi and
David Atienza and
Erik Brunvand},
title = {Design considerations for variation tolerant multilevel CMOS/Nano
memristor memory},
booktitle = {Proceedings of the 20th {ACM} Great Lakes Symposium on {VLSI} 2009,
Providence, Rhode Island, USA, May 16-18 2010},
pages = {287--292},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1785481.1785548},
doi = {10.1145/1785481.1785548},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ManemRHW10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nanoarch/RajendranMKR10,
author = {Jeyavijayan Rajendran and
Harika Manem and
Ramesh Karri and
Garrett S. Rose},
editor = {Shamik Das and
Iris Bahar and
Michael T. Niemier},
title = {Memristor based programmable threshold logic array},
booktitle = {2010 {IEEE/ACM} International Symposium on Nanoscale Architectures,
{NANOARCH} 2010, Anaheim, CA, USA, June 17-18, 2010},
pages = {5--10},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/NANOARCH.2010.5510933},
doi = {10.1109/NANOARCH.2010.5510933},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nanoarch/RajendranMKR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/GojmanMRD09,
author = {Benjamin Gojman and
Harika Manem and
Garrett S. Rose and
Andr{\'{e}} DeHon},
title = {Inversion schemes for sublithographic programmable logic arrays},
journal = {{IET} Comput. Digit. Tech.},
volume = {3},
number = {6},
pages = {625--642},
year = {2009},
url = {https://doi.org/10.1049/iet-cdt.2008.0128},
doi = {10.1049/IET-CDT.2008.0128},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/GojmanMRD09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ManemR09,
author = {Harika Manem and
Garrett S. Rose},
editor = {Fabrizio Lombardi and
Sanjukta Bhanja and
Yehia Massoud and
R. Iris Bahar},
title = {The effects of logic partitioning in a majority logic based {CMOS-NANO}
{FPGA}},
booktitle = {Proceedings of the 19th {ACM} Great Lakes Symposium on {VLSI} 2009,
Boston Area, MA, USA, May 10-12 2009},
pages = {157--160},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1531542.1531582},
doi = {10.1145/1531542.1531582},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ManemR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ManemPR08,
author = {Harika Manem and
Peter C. Paliwoda and
Garrett S. Rose},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {A hybrid cmos/nano fpga architecture built fromprogrammable majority
logic arrays},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {249--254},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366171},
doi = {10.1145/1366110.1366171},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ManemPR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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last updated on 2023-09-28 03:11 CEST by the dblp team
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