BibTeX records: Ku-Feng Lin

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@inproceedings{DBLP:conf/isscc/LinNSYLCHLLHTANYGSJWJWCWCCWC24,
  author       = {Ku{-}Feng Lin and
                  Hiroki Noguchi and
                  Yi{-}Chun Shih and
                  Perng{-}Fei Yuh and
                  Yuan{-}Jen Lee and
                  Tung{-}Cheng Chang and
                  Sheng{-}Po Huang and
                  Yu{-}Fan Lin and
                  Chun{-}Ying Lee and
                  Yen{-}Hsiang Huang and
                  Jui{-}Che Tsai and
                  Saman Adham and
                  Peter Noel and
                  Ramin Yazdi and
                  Marat Gershoig and
                  YangJae Shin and
                  Vineet Joshi and
                  Ted Wong and
                  Meng{-}Ru Jiang and
                  J. J. Wu and
                  Chun{-}Tai Cheng and
                  Yu{-}Jen Wang and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Yih Wang and
                  Tsung{-}Yung Jonathan Chang},
  title        = {15.9 {A} 16nm 16Mb Embedded {STT-MRAM} with a 20ns Write Time, a 10\({}^{\mbox{12}}\)
                  Write Endurance and Integrated Margin-Expansion Schemes},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2024,
                  San Francisco, CA, USA, February 18-22, 2024},
  pages        = {292--294},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ISSCC49657.2024.10454339},
  doi          = {10.1109/ISSCC49657.2024.10454339},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LinNSYLCHLLHTANYGSJWJWCWCCWC24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ShihLCLLCLYYCCC19,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40-nm 16-Mb, Embedded Perpendicular-MRAM
                  With Hybrid-Resistance Reference, Sub- {\textdollar}{\textbackslash}mu{\textdollar}
                  {A} Sensing Resolution, and 17.5-nS Read Access Time},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {54},
  number       = {4},
  pages        = {1029--1038},
  year         = {2019},
  url          = {https://doi.org/10.1109/JSSC.2018.2889106},
  doi          = {10.1109/JSSC.2018.2889106},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ShihLCLLCLYYCCC19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18,
  author       = {Yi{-}Chun Shih and
                  Chia{-}Fu Lee and
                  Yen{-}An Chang and
                  Po{-}Hao Lee and
                  Hon{-}Jarn Lin and
                  Yu{-}Lin Chen and
                  Ku{-}Feng Lin and
                  Ta{-}Ching Yeh and
                  Hung{-}Chang Yu and
                  Harry Chuang and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with
                  Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and
                  17.5NS Read Access Time},
  booktitle    = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
                  18-22, 2018},
  pages        = {79--80},
  publisher    = {{IEEE}},
  year         = {2018},
  url          = {https://doi.org/10.1109/VLSIC.2018.8502260},
  doi          = {10.1109/VLSIC.2018.8502260},
  timestamp    = {Wed, 07 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChangWCLYSKLLCC15,
  author       = {Meng{-}Fan Chang and
                  Jui{-}Jen Wu and
                  Tun{-}Fei Chien and
                  Yen{-}Chen Liu and
                  Ting{-}Chin Yang and
                  Wen{-}Chao Shen and
                  Ya{-}Chin King and
                  Chrong Jung Lin and
                  Ku{-}Feng Lin and
                  Yu{-}Der Chih and
                  Tsung{-}Yung Jonathan Chang},
  title        = {Low VDDmin Swing-Sample-and-Couple Sense Amplifier and Energy-Efficient
                  Self-Boost-Write-Termination Scheme for Embedded ReRAM Macros Against
                  Resistance and Switch-Time Variations},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {50},
  number       = {11},
  pages        = {2786--2795},
  year         = {2015},
  url          = {https://doi.org/10.1109/JSSC.2015.2472601},
  doi          = {10.1109/JSSC.2015.2472601},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChangWCLYSKLLCC15.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChangWCLYSKLLCN14,
  author       = {Meng{-}Fan Chang and
                  Jui{-}Jen Wu and
                  Tun{-}Fei Chien and
                  Yen{-}Chen Liu and
                  Ting{-}Chin Yang and
                  Wen{-}Chao Shen and
                  Ya{-}Chin King and
                  Chorng{-}Jung Lin and
                  Ku{-}Feng Lin and
                  Yu{-}Der Chih and
                  Sreedhar Natarajan and
                  Tsung{-}Yung Jonathan Chang},
  title        = {19.4 embedded 1Mb ReRAM in 28nm {CMOS} with 0.27-to-1V read using
                  swing-sample-and-couple sense amplifier and self-boost-write-termination
                  scheme},
  booktitle    = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
                  {ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
                  February 9-13, 2014},
  pages        = {332--333},
  publisher    = {{IEEE}},
  year         = {2014},
  url          = {https://doi.org/10.1109/ISSCC.2014.6757457},
  doi          = {10.1109/ISSCC.2014.6757457},
  timestamp    = {Mon, 09 Aug 2021 14:54:04 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChangWCLYSKLLCN14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChangSLWKCYCLLCSKKT13,
  author       = {Meng{-}Fan Chang and
                  Shyh{-}Shyuan Sheu and
                  Ku{-}Feng Lin and
                  Che{-}Wei Wu and
                  Chia{-}Chen Kuo and
                  Pi{-}Feng Chiu and
                  Yih{-}Shan Yang and
                  Yu{-}Sheng Chen and
                  Heng{-}Yuan Lee and
                  Chen{-}Hsin Lien and
                  Frederick T. Chen and
                  Keng{-}Li Su and
                  Tzu{-}Kun Ku and
                  Ming{-}Jer Kao and
                  Ming{-}Jinn Tsai},
  title        = {A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive
                  {RAM} (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode
                  Read Schemes},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {48},
  number       = {3},
  pages        = {878--891},
  year         = {2013},
  url          = {https://doi.org/10.1109/JSSC.2012.2230515},
  doi          = {10.1109/JSSC.2012.2230515},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/jssc/ChangSLWKCYCLLCSKKT13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChangWKSYLSKLC13,
  author       = {Meng{-}Fan Chang and
                  Che{-}Wei Wu and
                  Chia{-}Chen Kuo and
                  Shin{-}Jang Shen and
                  Sue{-}Meng Yang and
                  Ku{-}Feng Lin and
                  Wen{-}Chao Shen and
                  Ya{-}Chin King and
                  Chorng{-}Jung Lin and
                  Yu{-}Der Chih},
  title        = {A Low-Voltage Bulk-Drain-Driven Read Scheme for Sub-0.5 {V} 4 Mb 65
                  nm Logic-Process Compatible Embedded Resistive {RAM} (ReRAM) Macro},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {48},
  number       = {9},
  pages        = {2250--2259},
  year         = {2013},
  url          = {https://doi.org/10.1109/JSSC.2013.2259713},
  doi          = {10.1109/JSSC.2013.2259713},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChangWKSYLSKLC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YuLLHCOCNT13,
  author       = {Hung{-}Chang Yu and
                  Kai{-}Chun Lin and
                  Ku{-}Feng Lin and
                  Chin{-}Yi Huang and
                  Yu{-}Der Chih and
                  Tong{-}Chern Ong and
                  Tsung{-}Yung Jonathan Chang and
                  Sreedhar Natarajan and
                  Luan C. Tran},
  title        = {Cycling endurance optimization scheme for 1Mb {STT-MRAM} in 40nm technology},
  booktitle    = {2013 {IEEE} International Solid-State Circuits Conference - Digest
                  of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
                  17-21, 2013},
  pages        = {224--225},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/ISSCC.2013.6487710},
  doi          = {10.1109/ISSCC.2013.6487710},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YuLLHCOCNT13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsi-dat/YuLLCN13,
  author       = {Hung{-}Chang Yu and
                  Ku{-}Feng Lin and
                  Kai{-}Chun Lin and
                  Yu{-}Der Chih and
                  Sreedhar Natarajan},
  title        = {A 180 MHz direct access read 4.6Mb embedded flash in 90nm technology
                  operating under wide range power supply from 2.1V to 3.6V},
  booktitle    = {2013 International Symposium on {VLSI} Design, Automation, and Test,
                  {VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
  pages        = {1--4},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/VLDI-DAT.2013.6533858},
  doi          = {10.1109/VLDI-DAT.2013.6533858},
  timestamp    = {Wed, 16 Oct 2019 14:14:54 +0200},
  biburl       = {https://dblp.org/rec/conf/vlsi-dat/YuLLCN13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChangWKSLYKLC12,
  author       = {Meng{-}Fan Chang and
                  Che{-}Wei Wu and
                  Chia{-}Chen Kuo and
                  Shin{-}Jang Shen and
                  Ku{-}Feng Lin and
                  Shu{-}Meng Yang and
                  Ya{-}Chin King and
                  Chorng{-}Jung Lin and
                  Yu{-}Der Chih},
  title        = {A 0.5V 4Mb logic-process compatible embedded resistive {RAM} (ReRAM)
                  in 65nm {CMOS} using low-voltage current-mode sensing scheme with
                  45ns random read time},
  booktitle    = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2012, San Francisco, CA, USA, February 19-23, 2012},
  pages        = {434--436},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/ISSCC.2012.6177079},
  doi          = {10.1109/ISSCC.2012.6177079},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChangWKSLYKLC12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/SheuCLWCCKYCLLLGWCSLCWKKT11,
  author       = {Shyh{-}Shyuan Sheu and
                  Meng{-}Fan Chang and
                  Ku{-}Feng Lin and
                  Che{-}Wei Wu and
                  Yu{-}Sheng Chen and
                  Pi{-}Feng Chiu and
                  Chia{-}Chen Kuo and
                  Yih{-}Shan Yang and
                  Pei{-}Chia Chiang and
                  Wen{-}Pin Lin and
                  Che{-}He Lin and
                  Heng{-}Yuan Lee and
                  Peiyi Gu and
                  Sumin Wang and
                  Frederick T. Chen and
                  Keng{-}Li Su and
                  Chen{-}Hsin Lien and
                  Kuo{-}Hsing Cheng and
                  Hsin{-}Tun Wu and
                  Tzu{-}Kun Ku and
                  Ming{-}Jer Kao and
                  Ming{-}Jinn Tsai},
  title        = {A 4Mb embedded {SLC} resistive-RAM macro with 7.2ns read-write random-access
                  time and 160ns MLC-access capability},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
                  Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
                  2011},
  pages        = {200--202},
  publisher    = {{IEEE}},
  year         = {2011},
  url          = {https://doi.org/10.1109/ISSCC.2011.5746281},
  doi          = {10.1109/ISSCC.2011.5746281},
  timestamp    = {Sun, 25 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/SheuCLWCCKYCLLLGWCSLCWKKT11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/ChangYLCCL10,
  author       = {Meng{-}Fan Chang and
                  Shu{-}Meng Yang and
                  Chih{-}Wei Liang and
                  Chih{-}Chyuang Chiang and
                  Pi{-}Feng Chiu and
                  Ku{-}Feng Lin},
  title        = {Noise-Immune Embedded {NAND-ROM} Using a Dynamic Split Source-Line
                  Scheme for VDDmin and Speed Improvements},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {45},
  number       = {10},
  pages        = {2142--2155},
  year         = {2010},
  url          = {https://doi.org/10.1109/JSSC.2010.2060279},
  doi          = {10.1109/JSSC.2010.2060279},
  timestamp    = {Sun, 30 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/ChangYLCCL10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/ChangYLCCLCWY10,
  author       = {Meng{-}Fan Chang and
                  Shu{-}Meng Yang and
                  Chih{-}Wei Liang and
                  Chih{-}Chyuang Chiang and
                  Pi{-}Feng Chiu and
                  Ku{-}Feng Lin and
                  Yuan{-}Hua Chu and
                  Wen{-}Chin Wu and
                  Hiroyuki Yamauchi},
  title        = {A 0.29V embedded {NAND-ROM} in 90nm {CMOS} for ultra-low-voltage applications},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
                  Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
                  2010},
  pages        = {266--267},
  publisher    = {{IEEE}},
  year         = {2010},
  url          = {https://doi.org/10.1109/ISSCC.2010.5433914},
  doi          = {10.1109/ISSCC.2010.5433914},
  timestamp    = {Tue, 07 May 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/ChangYLCCLCWY10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

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