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ORCIDBibTeX records: Stephen V. Kosonocky
@inproceedings{DBLP:conf/asplos/BharadwajDMBK23,
author = {Srikant Bharadwaj and
Shomit Das and
Kaushik Mazumdar and
Bradford M. Beckmann and
Stephen Kosonocky},
editor = {Tor M. Aamodt and
Michael M. Swift and
Natalie D. Enright Jerger},
title = {Predict; Don't React for Enabling Efficient Fine-Grain {DVFS} in GPUs},
booktitle = {Proceedings of the 28th {ACM} International Conference on Architectural
Support for Programming Languages and Operating Systems, Volume 4,
{ASPLOS} 2023, Vancouver, BC, Canada, March 25-29, 2023},
pages = {253--267},
publisher = {{ACM}},
year = {2023},
url = {https://doi.org/10.1145/3623278.3624756},
doi = {10.1145/3623278.3624756},
timestamp = {Sat, 10 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asplos/BharadwajDMBK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2205-00121,
author = {Srikant Bharadwaj and
Shomit Das and
Kaushik Mazumdar and
Bradford M. Beckmann and
Stephen Kosonocky},
title = {Predict; Do not React for Enabling Efficient Fine Grain {DVFS} in
GPUs},
journal = {CoRR},
volume = {abs/2205.00121},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2205.00121},
doi = {10.48550/ARXIV.2205.00121},
eprinttype = {arXiv},
eprint = {2205.00121},
timestamp = {Tue, 03 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2205-00121.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PapermasterKLN21,
author = {Mark Papermaster and
Stephen Kosonocky and
Gabriel H. Loh and
Samuel Naffziger},
title = {A New Era of Tailored Computing},
booktitle = {2021 Symposium on {VLSI} Circuits, Kyoto, Japan, June 13-19, 2021},
pages = {1--2},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/VLSICircuits52068.2021.9492400},
doi = {10.23919/VLSICIRCUITS52068.2021.9492400},
timestamp = {Mon, 02 Aug 2021 16:52:31 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PapermasterKLN21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SinghSRJHSRKNN18,
author = {Teja Singh and
Alex Schaefer and
Sundar Rangarajan and
Deepesh John and
Carson Henrion and
Russell Schreiber and
Miguel Rodriguez and
Stephen Kosonocky and
Samuel Naffziger and
Amy Novak},
title = {Zen: An Energy-Efficient High-Performance {\texttimes} 86 Core},
journal = {{IEEE} J. Solid State Circuits},
volume = {53},
number = {1},
pages = {102--114},
year = {2018},
url = {https://doi.org/10.1109/JSSC.2017.2752839},
doi = {10.1109/JSSC.2017.2752839},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SinghSRJHSRKNN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SundaramGNBKLRR17,
author = {Sriram Sundaram and
Aaron Grenat and
Samuel Naffziger and
Tom Burd and
Stephen Kosonocky and
Steven Liepe and
Ravinder Rachala and
Miguel Rodriguez and
Michael Austin and
Sriram Sambamurthy},
title = {Bristol Ridge: {A} 28-nm {\texttimes} 86 Performance-Enhanced Microprocessor
Through System Power Management},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {89--97},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2623637},
doi = {10.1109/JSSC.2016.2623637},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SundaramGNBKLRR17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/SinghRJHSMNKJSC17,
author = {Teja Singh and
Sundar Rangarajan and
Deepesh John and
Carson Henrion and
Shane Southard and
Hugh McIntyre and
Amy Novak and
Stephen Kosonocky and
Ravi Jotwani and
Alex Schaefer and
Edward Chang and
Joshua Bell and
Michael Co},
title = {3.2 Zen: {A} next-generation high-performance {\texttimes}86 core},
booktitle = {2017 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2017, San Francisco, CA, USA, February 5-9, 2017},
pages = {52--53},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISSCC.2017.7870256},
doi = {10.1109/ISSCC.2017.7870256},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/SinghRJHSMNKJSC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/RachalaRKT16,
author = {Ravinder Rachala and
Miguel Rodriguez and
Stephen Kosonocky and
Milos Trajkovic},
title = {Modeling and implementation of a fully-digital integrated per-core
voltage regulation system in a 28nm high performance 64-bit processor},
booktitle = {Proceedings of the 2016 International Symposium on Low Power Electronics
and Design, {ISLPED} 2016, San Francisco Airport, CA, USA, August
08 - 10, 2016},
pages = {88--93},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2934583.2934586},
doi = {10.1145/2934583.2934586},
timestamp = {Tue, 06 Nov 2018 16:59:21 +0100},
biburl = {https://dblp.org/rec/conf/islped/RachalaRKT16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GrenatSKRSLRBCA16,
author = {Aaron Grenat and
Sriram Sundaram and
Stephen Kosonocky and
Ravinder Rachala and
Sriram Sambamurthy and
Steven Liepe and
Miguel Rodriguez and
Tom Burd and
Adam Clark and
Michael Austin and
Samuel Naffziger},
title = {4.2 Increasing the performance of a 28nm x86-64 microprocessor through
system power management},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {74--75},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417913},
doi = {10.1109/ISSCC.2016.7417913},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/GrenatSKRSLRBCA16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SundaramSAGGKN16,
author = {Sriram Sundaram and
Sriram Sambamurthy and
Michael Austin and
Aaron Grenat and
Michael Golden and
Stephen Kosonocky and
Samuel Naffziger},
title = {Adaptive Voltage Frequency Scaling Using Critical Path Accumulator
Implemented in 28nm {CPU}},
booktitle = {29th International Conference on {VLSI} Design and 15th International
Conference on Embedded Systems, {VLSID} 2016, Kolkata, India, January
4-8, 2016},
pages = {565--566},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/VLSID.2016.106},
doi = {10.1109/VLSID.2016.106},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SundaramSAGGKN16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/DeKCRS15,
author = {Vivek De and
Stephen Kosonocky and
Jonathan Chang and
Yogesh K. Ramadass and
David Stoppa},
title = {Highlights of the {IEEE} {ISSCC} 2014 Processors, Digital, Memory,
Biomedical {\&} Next-Generation Systems Technologies, and Imagers,
MEMS, Medical {\&} Displays Sessions},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {4--9},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2379853},
doi = {10.1109/JSSC.2014.2379853},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/DeKCRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/WilcoxCFGGHJKMNOPPRW15,
author = {Kathryn Wilcox and
Robert Cole and
Harry R. Fair III and
Kevin Gillespie and
Aaron Grenat and
Carson Henrion and
Ravi Jotwani and
Stephen Kosonocky and
Benjamin Munger and
Samuel Naffziger and
Robert S. Orefice and
Sanjay Pant and
Donald A. Priore and
Ravinder Rachala and
Jonathan White},
title = {Steamroller Module and Adaptive Clocking System in 28 nm {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {50},
number = {1},
pages = {24--34},
year = {2015},
url = {https://doi.org/10.1109/JSSC.2014.2357428},
doi = {10.1109/JSSC.2014.2357428},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/WilcoxCFGGHJKMNOPPRW15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/GillespieFHJKOP14,
author = {Kevin Gillespie and
Harry R. Fair III and
Carson Henrion and
Ravi Jotwani and
Stephen V. Kosonocky and
Robert S. Orefice and
Donald A. Priore and
Jonathan White and
Kathryn Wilcox},
title = {5.5 Steamroller: An x86-64 core implemented in 28nm bulk {CMOS}},
booktitle = {2014 {IEEE} International Conference on Solid-State Circuits Conference,
{ISSCC} 2014, Digest of Technical Papers, San Francisco, CA, USA,
February 9-13, 2014},
pages = {104--105},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISSCC.2014.6757357},
doi = {10.1109/ISSCC.2014.6757357},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/isscc/GillespieFHJKOP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/CraigSKALCK12,
author = {Kyle Craig and
Yousef Shakhsheer and
Sudhanshu Khanna and
Saad Arrabi and
John C. Lach and
Benton H. Calhoun and
Stephen Kosonocky},
editor = {Naresh R. Shanbhag and
Massimo Poncino and
Pai H. Chou and
Ajith Amerasekera},
title = {A programmable resistive power grid for post-fabrication flexibility
and energy tradeoffs},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12,
Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
pages = {167--172},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2333660.2333703},
doi = {10.1145/2333660.2333703},
timestamp = {Fri, 20 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/CraigSKALCK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KosonockySBCKF12,
author = {Stephen Kosonocky and
Vladimir Stojanovic and
Kees van Berkel and
Ming{-}Yang Chao and
Tobias Knoll and
Joshua Friedrich},
title = {Power/performance optimization of many-core processor SoCs},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {508--509},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177118},
doi = {10.1109/ISSCC.2012.6177118},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KosonockySBCKF12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/JotwaniSKSANN11,
author = {Ravi Jotwani and
Sriram Sundaram and
Stephen Kosonocky and
Alex Schaefer and
Victor Andrade and
Amy Novak and
Sam Naffziger},
title = {An x86-64 Core in 32 nm {SOI} {CMOS}},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {1},
pages = {162--172},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2010.2080530},
doi = {10.1109/JSSC.2010.2080530},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/JotwaniSKSANN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hotchips/Kosonocky11,
author = {Stephen Kosonocky},
title = {Practical power gating and dynamic voltage/frequency scaling},
booktitle = {2011 {IEEE} Hot Chips 23 Symposium (HCS), Stanford, CA, USA, August
17-19, 2011},
pages = {1--62},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2011.7477480},
doi = {10.1109/HOTCHIPS.2011.7477480},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hotchips/Kosonocky11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/Kosonocky10,
author = {Stephen V. Kosonocky},
title = {Are you having fun yet?},
journal = {{IEEE} Des. Test Comput.},
volume = {27},
number = {6},
pages = {80},
year = {2010},
url = {https://doi.org/10.1109/MDT.2010.124},
doi = {10.1109/MDT.2010.124},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/Kosonocky10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/JotwaniSKSACNN10,
author = {Ravi Jotwani and
Sriram Sundaram and
Stephen Kosonocky and
Alex Schaefer and
Victor Andrade and
Greg Constant and
Amy Novak and
Sam Naffziger},
title = {An x86-64 core implemented in 32nm {SOI} {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {106--107},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5434076},
doi = {10.1109/ISSCC.2010.5434076},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/JotwaniSKSACNN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/BhavnagarwalaKR08,
author = {Azeez J. Bhavnagarwala and
Stephen Kosonocky and
Carl Radens and
Yuen H. Chan and
Kevin Stawiasz and
Uma Srinivasan and
Steven P. Kowalczyk and
Matthew M. Ziegler},
title = {A Sub-600-mV, Fluctuation Tolerant 65-nm {CMOS} {SRAM} Array With
Dynamic Cell Biasing},
journal = {{IEEE} J. Solid State Circuits},
volume = {43},
number = {4},
pages = {946--955},
year = {2008},
url = {https://doi.org/10.1109/JSSC.2008.917506},
doi = {10.1109/JSSC.2008.917506},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/BhavnagarwalaKR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PuriVEWFYK08,
author = {Ruchir Puri and
Devadas Varma and
Darvin Edwards and
Alan J. Weger and
Paul D. Franzon and
Andrew Yang and
Stephen V. Kosonocky},
editor = {Limor Fix},
title = {Keeping hot chips cool: are {IC} thermal problems hot air?},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {634--635},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391632},
doi = {10.1145/1391469.1391632},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/PuriVEWFYK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KosonockyY07,
author = {Stephen V. Kosonocky and
Kazuo Yano},
title = {Introduction to the Special Issue on the 2006 Symposium on {VLSI}
Circuits},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {4},
pages = {720--721},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2006.891761},
doi = {10.1109/JSSC.2006.891761},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KosonockyY07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KimKKSP07,
author = {Suhwan Kim and
Stephen V. Kosonocky and
Daniel R. Knebel and
Kevin Stawiasz and
Marios C. Papaefthymiou},
title = {A Multi-Mode Power Gating Structure for Low-Voltage Deep-Submicron
{CMOS} ICs},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {54-II},
number = {7},
pages = {586--590},
year = {2007},
url = {https://doi.org/10.1109/TCSII.2007.894428},
doi = {10.1109/TCSII.2007.894428},
timestamp = {Fri, 23 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KimKKSP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KamhiMMNWKMKC07,
author = {Gila Kamhi and
Sarah Miller and
Stephen Bailey Mentor and
Wolfgang Nebel and
Y. C. Wong and
Juergen Karmann and
Enrico Macii and
Stephen V. Kosonocky and
Steve Curtis},
title = {Early Power-Aware Design {\&} Validation: Myth or Reality?},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {210--211},
publisher = {{IEEE}},
year = {2007},
timestamp = {Tue, 29 Jul 2014 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/KamhiMMNWKMKC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ZieglerDKQS07,
author = {Matthew M. Ziegler and
Gary S. Ditlow and
Stephen V. Kosonocky and
Zhenyu Qi and
Mircea R. Stan},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Structured and tuned array generation {(STAG)} for high-performance
random logic},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {257--262},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228849},
doi = {10.1145/1228784.1228849},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ZieglerDKQS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/QiZKRS07,
author = {Zhenyu Qi and
Matthew M. Ziegler and
Stephen V. Kosonocky and
Jan M. Rabaey and
Mircea R. Stan},
title = {Multi-Dimensional Circuit and Micro-Architecture Level Optimization},
booktitle = {8th International Symposium on Quality of Electronic Design {(ISQED}
2007), 26-28 March 2007, San Jose, CA, {USA}},
pages = {275--280},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISQED.2007.105},
doi = {10.1109/ISQED.2007.105},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/QiZKRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChinZGK05,
author = {Phillip Chin and
Charles A. Zukowski and
George Gristede and
Stephen V. Kosonocky},
title = {Characterization of logic circuit techniques and optimization for
high-leakage {CMOS} technologies},
journal = {Integr.},
volume = {38},
number = {3},
pages = {491--504},
year = {2005},
url = {https://doi.org/10.1016/j.vlsi.2004.07.011},
doi = {10.1016/J.VLSI.2004.07.011},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/ChinZGK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChinZGK04,
author = {Phillip Chin and
Charles A. Zukowski and
George Gristede and
Stephen V. Kosonocky},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {Characterization of logic circuit techniques for high leakage {CMOS}
technologies},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {230--235},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.989008},
doi = {10.1145/988952.989008},
timestamp = {Fri, 20 Aug 2021 16:30:37 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ChinZGK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimKKS04,
author = {Suhwan Kim and
Stephen V. Kosonocky and
Daniel R. Knebel and
Kevin Stawiasz},
editor = {Rajiv V. Joshi and
Kiyoung Choi and
Vivek Tiwari and
Kaushik Roy},
title = {Experimental measurement of a novel power gating structure with intermediate
power saving mode},
booktitle = {Proceedings of the 2004 International Symposium on Low Power Electronics
and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
pages = {20--25},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1013235.1013246},
doi = {10.1145/1013235.1013246},
timestamp = {Fri, 23 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/KimKKS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/SatheZPKK04,
author = {Visvesh S. Sathe and
Conrad H. Ziesler and
Marios C. Papaefthymiou and
Suhwan Kim and
Stephen V. Kosonocky},
title = {A synchronous interface for SoCs with multiple clock domains},
booktitle = {Proceedings 2004 {IEEE} International {SOC} Conference, September
12-15, 2004, Hilton Santa Clara, CA, {USA}},
pages = {173--174},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/SOCC.2004.1362396},
doi = {10.1109/SOCC.2004.1362396},
timestamp = {Tue, 10 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/socc/SatheZPKK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/KosonockyBCGHHKKKWZ03,
author = {Stephen V. Kosonocky and
Azeez J. Bhavnagarwala and
Kenneth Chin and
George Gristede and
Anne{-}Marie Haen and
Wei Hwang and
Mark B. Ketchen and
Suhwan Kim and
Daniel R. Knebel and
Kevin W. Warren and
Victor V. Zyuban},
title = {Low-power circuits and technology for wireless digital systems},
journal = {{IBM} J. Res. Dev.},
volume = {47},
number = {2-3},
pages = {283--298},
year = {2003},
url = {https://doi.org/10.1147/rd.472.0283},
doi = {10.1147/RD.472.0283},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/KosonockyBCGHHKKKWZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/PlouchartZKSTRTWWLNOPRSFKKKJR03,
author = {Jean{-}Olivier Plouchart and
Noah Zamdmer and
Jonghae Kim and
Melanie Sherony and
Yue Tan and
Asit Ray and
Mohamed Talbi and
Lawrence F. Wagner and
Kun Wu and
Naftali E. Lustig and
Shreesh Narasimha and
Patricia O'Neil and
Nghia Phan and
Michael Rohn and
James Strom and
David M. Friend and
Stephen V. Kosonocky and
Daniel R. Knebel and
Suhwan Kim and
Keith A. Jenkins and
Michel M. Rivier},
title = {Application of an {SOI} 0.12-{\(\mathrm{\mu}\)}m {CMOS} technology
to SoCs with low-power and high-frequency circuits},
journal = {{IBM} J. Res. Dev.},
volume = {47},
number = {5-6},
pages = {611--630},
year = {2003},
url = {https://doi.org/10.1147/rd.475.0611},
doi = {10.1147/RD.475.0611},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ibmrd/PlouchartZKSTRTWWLNOPRSFKKKJR03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/KimKKSHI03,
author = {Suhwan Kim and
Stephen V. Kosonocky and
Daniel R. Knebel and
Kevin Stawiasz and
David F. Heidel and
Michael Immediato},
editor = {Jos{\'{e}} E. Franca and
Rudolf Koch},
title = {Minimizing inductive noise in system-on-a-chip with multiple power
gating structures},
booktitle = {{ESSCIRC} 2003 - 29th European Solid-State Circuits Conference, Estoril,
Portugal, September 16-18, 2003},
pages = {635--638},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ESSCIRC.2003.1257215},
doi = {10.1109/ESSCIRC.2003.1257215},
timestamp = {Tue, 04 Jul 2023 08:46:31 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/KimKKSHI03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimKK03,
author = {Suhwan Kim and
Stephen V. Kosonocky and
Daniel R. Knebel},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {Understanding and minimizing ground bounce during mode transition
of power gating structures},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {22--25},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871515},
doi = {10.1145/871506.871515},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KimKK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZyubanK02,
author = {Victor V. Zyuban and
Stephen V. Kosonocky},
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {Low power integrated scan-retention mechanism},
booktitle = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
pages = {98--102},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/566408.566436},
doi = {10.1145/566408.566436},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ZyubanK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WangCK02,
author = {Alice Wang and
Anantha P. Chandrakasan and
Stephen V. Kosonocky},
title = {Optimal Supply and Threshold Scaling for Subthreshold {CMOS} Circuits},
booktitle = {2002 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2002), 25-26 April 2002, Pittsburgh, PA, {USA}},
pages = {7--14},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISVLSI.2002.1016866},
doi = {10.1109/ISVLSI.2002.1016866},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WangCK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BhavnagarwalaKM01,
author = {Azeez J. Bhavnagarwala and
Stephen V. Kosonocky and
James D. Meindl},
title = {Interconnect-centric Array Architectures for Minimum {SRAM} Access
Time},
booktitle = {19th International Conference on Computer Design {(ICCD} 2001), {VLSI}
in Computers and Processors, 23-26 September 2001, Austin, TX, USA,
Proceedings},
pages = {400--405},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCD.2001.955058},
doi = {10.1109/ICCD.2001.955058},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BhavnagarwalaKM01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KosonockyICHMB01,
author = {Stephen V. Kosonocky and
Michael Immediato and
Peter E. Cottrell and
Terence B. Hook and
Randy W. Mann and
Jeff Brown},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Enchanced multi-threshold {(MTCMOS)} circuits using variable well
bias},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {165--169},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383125},
doi = {10.1145/383082.383125},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KosonockyICHMB01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChenHKGKJ01,
author = {W. Chen and
Wei Hwang and
Prabhakar Kudva and
George Gristede and
Stephen V. Kosonocky and
Rajiv V. Joshi},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Mixed multi-threshold differential cascode voltage switch {(MT-DCVS)}
circuit styles and strategies for low power {VLSI} design},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {263--266},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383156},
doi = {10.1145/383082.383156},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChenHKGKJ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/EbciogluFKGAKB98,
author = {Kemal Ebcioglu and
Jason Fritts and
Stephen Kosonocky and
Michael Gschwind and
Erik R. Altman and
Krishnan Kailas and
Terry Bright},
title = {An eight-issue tree-VLIW processor for dynamic binary translation},
booktitle = {International Conference on Computer Design: {VLSI} in Computers and
Processors, {ICCD} 1998, Proceedings, 5-7 October, 1998, Austin, TX,
{USA}},
pages = {488--495},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ICCD.1998.727094},
doi = {10.1109/ICCD.1998.727094},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/EbciogluFKGAKB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KosonockyBWHKABHHIJJPRS98,
author = {Stephen V. Kosonocky and
Arthur A. Bright and
Kevin W. Warren and
Ruud A. Haring and
Steve Klepner and
Sameh W. Asaad and
S. Basavaiah and
Bob Havreluk and
David F. Heidel and
Michael Immediato and
Keith A. Jenkins and
Rajiv V. Joshi and
Benjamin D. Parker and
T. V. Rajeevakumar and
Kevin Stawiasz},
title = {Designing a Testable System on a Chip},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {2--7},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670841},
doi = {10.1109/VTEST.1998.670841},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KosonockyBWHKABHHIJJPRS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icassp/KosonockyM95,
author = {Stephen V. Kosonocky and
Richard J. Mammone},
title = {A continuous density neural tree network word spotting system},
booktitle = {1995 International Conference on Acoustics, Speech, and Signal Processing,
{ICASSP} '95, Detroit, Michigan, USA, May 08-12, 1995},
pages = {305--308},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ICASSP.1995.479534},
doi = {10.1109/ICASSP.1995.479534},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icassp/KosonockyM95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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