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ORCIDBibTeX records: Atsushi Kawasumi
@article{DBLP:journals/jssc/KawasumiHC20,
author = {Atsushi Kawasumi and
Mototsugu Hamada and
Po{-}Hung Chen},
title = {Introduction to the Special Section on the 2019 Asian Solid-State
Circuits Conference {(A-SSCC)}},
journal = {{IEEE} J. Solid State Circuits},
volume = {55},
number = {10},
pages = {2627--2628},
year = {2020},
url = {https://doi.org/10.1109/JSSC.2020.3012639},
doi = {10.1109/JSSC.2020.3012639},
timestamp = {Mon, 05 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KawasumiHC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/SylvesterMGKM17,
author = {Dennis Sylvester and
Dejan Markovic and
Roman Genov and
Atsushi Kawasumi and
Subhasish Mitra},
title = {Introduction to the January Special Issue on the 2016 {IEEE} International
Solid-State Circuits Conference},
journal = {{IEEE} J. Solid State Circuits},
volume = {52},
number = {1},
pages = {3--7},
year = {2017},
url = {https://doi.org/10.1109/JSSC.2016.2635358},
doi = {10.1109/JSSC.2016.2635358},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/SylvesterMGKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/NoguchiITAKKHAS16,
author = {Hiroki Noguchi and
Kazutaka Ikegami and
Satoshi Takaya and
Eishi Arima and
Keiichi Kushida and
Atsushi Kawasumi and
Hiroyuki Hara and
Keiko Abe and
Naoharu Shimomura and
Junichi Ito and
Shinobu Fujita and
Takashi Nakada and
Hiroshi Nakamura},
title = {7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization
and write-verify-write / read-modify-write scheme},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {132--133},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7417942},
doi = {10.1109/ISSCC.2016.7417942},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/NoguchiITAKKHAS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MairK16,
author = {Hugh Mair and
Atsushi Kawasumi},
title = {Session 17 overview: {SRAM}},
booktitle = {2016 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2016, San Francisco, CA, USA, January 31 - February 4, 2016},
pages = {304--305},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISSCC.2016.7418028},
doi = {10.1109/ISSCC.2016.7418028},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/MairK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/NoguchiIKAITSIK15,
author = {Hiroki Noguchi and
Kazutaka Ikegami and
Keiichi Kushida and
Keiko Abe and
Shogo Itai and
Satoshi Takaya and
Naoharu Shimomura and
Junichi Ito and
Atsushi Kawasumi and
Hiroyuki Hara and
Shinobu Fujita},
title = {7.5 {A} 3.3ns-access-time 71.2{\(\mu\)}W/MHz 1Mb embedded {STT-MRAM}
using physically eliminated read-disturb scheme and normally-off memory
architecture},
booktitle = {2015 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2015, Digest of Technical Papers, San Francisco, CA, USA, February
22-26, 2015},
pages = {1--3},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISSCC.2015.7062963},
doi = {10.1109/ISSCC.2015.7062963},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/NoguchiIKAITSIK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/TachibanaHTSKKSNSYU14,
author = {Fumihiko Tachibana and
Osamu Hirabayashi and
Yasuhisa Takeyama and
Miyako Shizuno and
Atsushi Kawasumi and
Keiichi Kushida and
Azuma Suzuki and
Yusuke Niki and
Shinichi Sasaki and
Tomoaki Yabe and
Yasuo Unekawa},
title = {A 27{\%} Active and 85{\%} Standby Power Reduction in Dual-Power-Supply
{SRAM} Using {BL} Power Calculator and Digitally Controllable Retention
Circuit},
journal = {{IEEE} J. Solid State Circuits},
volume = {49},
number = {1},
pages = {118--126},
year = {2014},
url = {https://doi.org/10.1109/JSSC.2013.2280312},
doi = {10.1109/JSSC.2013.2280312},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/TachibanaHTSKKSNSYU14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/MiyanoMYKSSS13,
author = {Shinji Miyano and
Shinichi Moriwaki and
Yasue Yamamoto and
Atsushi Kawasumi and
Toshikazu Suzuki and
Takayasu Sakurai and
Hirofumi Shinohara},
title = {Highly Energy-Efficient {SRAM} With Hierarchical Bit Line Charge-Sharing
Method Using Non-Selected Bit Line Charges},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {4},
pages = {924--931},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2237572},
doi = {10.1109/JSSC.2012.2237572},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/MiyanoMYKSSS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ClintonK13,
author = {Michael Clinton and
Atsushi Kawasumi},
title = {Session 18 overview: Advanced embedded {SRAM}},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {314--315},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487848},
doi = {10.1109/ISSCC.2013.6487848},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/ClintonK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/TachibanaHTSKKSNSYU13,
author = {Fumihiko Tachibana and
Osamu Hirabayashi and
Yasuhisa Takeyama and
Miyako Shizuno and
Atsushi Kawasumi and
Keiichi Kushida and
Azuma Suzuki and
Yusuke Niki and
Shinichi Sasaki and
Tomoaki Yabe and
Yasuo Unekawa},
title = {A 27{\%} active and 85{\%} standby power reduction in dual-power-supply
{SRAM} using {BL} power calculator and digitally controllable retention
circuit},
booktitle = {2013 {IEEE} International Solid-State Circuits Conference - Digest
of Technical Papers, {ISSCC} 2013, San Francisco, CA, USA, February
17-21, 2013},
pages = {320--321},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISSCC.2013.6487752},
doi = {10.1109/ISSCC.2013.6487752},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isscc/TachibanaHTSKKSNSYU13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/YamamotoKMSMS12,
author = {Yasue Yamamoto and
Atsushi Kawasumi and
Shinichi Moriwaki and
Toshikazu Suzuki and
Shinji Miyano and
Hirofumi Shinohara},
title = {60{\%} Cycle time acceleration, 55{\%} energy reduction, 32Kbit {SRAM}
by auto-selective boost {(ASB)} scheme for slow memory cells in random
variations},
booktitle = {Proceedings of the 38th European Solid-State Circuit conference, {ESSCIRC}
2012, Bordeaux, France, September 17-21, 2012},
pages = {317--320},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ESSCIRC.2012.6341318},
doi = {10.1109/ESSCIRC.2012.6341318},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/YamamotoKMSMS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/KawasumiTHKTNSY12,
author = {Atsushi Kawasumi and
Yasuhisa Takeyama and
Osamu Hirabayashi and
Keiichi Kushida and
Fumihiko Tachibana and
Yusuke Niki and
Shinichi Sasaki and
Tomoaki Yabe},
title = {Energy efficiency deterioration by variability in {SRAM} and circuit
techniques for energy saving without voltage reduction},
booktitle = {{IEEE} International Conference on {IC} Design {\&} Technology,
{ICICDT} 2012, Austin, TX, USA, May 30 - June 1, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ICICDT.2012.6232859},
doi = {10.1109/ICICDT.2012.6232859},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/KawasumiTHKTNSY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/YoshimotoTUOKSMMKY12,
author = {Shusuke Yoshimoto and
Masaharu Terada and
Youhei Umeki and
Shunsuke Okumura and
Atsushi Kawasumi and
Toshikazu Suzuki and
Shinichi Moriwaki and
Shinji Miyano and
Hiroshi Kawaguchi and
Masahiko Yoshimoto},
editor = {Naresh R. Shanbhag and
Massimo Poncino and
Pai H. Chou and
Ajith Amerasekera},
title = {A 40-nm 256-Kb Sub-10 pJ/Access 8t {SRAM} with read bitline amplitude
limiting {(RBAL)} scheme},
booktitle = {International Symposium on Low Power Electronics and Design, ISLPED'12,
Redondo Beach, CA, {USA} - July 30 - August 01, 2012},
pages = {85--90},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2333660.2333683},
doi = {10.1145/2333660.2333683},
timestamp = {Mon, 11 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/YoshimotoTUOKSMMKY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MoriwakiYKSMSS12,
author = {Shinichi Moriwaki and
Yasuhiro Yamamoto and
Atsushi Kawasumi and
Toshikazu Suzuki and
Shinji Miyano and
Takayasu Sakurai and
Hirofumi Shinohara},
title = {A 13.8pJ/Access/Mbit {SRAM} with charge collector circuits for effective
use of non-selected bit line charges},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {60--61},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243789},
doi = {10.1109/VLSIC.2012.6243789},
timestamp = {Mon, 27 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MoriwakiYKSMSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KawasumiTHKTNSY12,
author = {Atsushi Kawasumi and
Yasuhisa Takeyama and
Osamu Hirabayashi and
Keiichi Kushida and
Fumihiko Tachibana and
Yusuke Niki and
Shinichi Sasaki and
Tomoaki Yabe},
title = {A 47{\%} access time reduction with a worst-case timing-generation
scheme utilizing a statistical method for ultra low voltage SRAMs},
booktitle = {Symposium on {VLSI} Circuits, {VLSIC} 2012, Honolulu, HI, USA, June
13-15, 2012},
pages = {100--101},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSIC.2012.6243809},
doi = {10.1109/VLSIC.2012.6243809},
timestamp = {Sun, 21 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KawasumiTHKTNSY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/NikiKSTHKTFY11,
author = {Yusuke Niki and
Atsushi Kawasumi and
Azuma Suzuki and
Yasuhisa Takeyama and
Osamu Hirabayashi and
Keiichi Kushida and
Fumihiko Tachibana and
Yuki Fujimura and
Tomoaki Yabe},
title = {A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant
Timing Generation of {SRAM} Sense Amplifiers},
journal = {{IEEE} J. Solid State Circuits},
volume = {46},
number = {11},
pages = {2545--2551},
year = {2011},
url = {https://doi.org/10.1109/JSSC.2011.2164294},
doi = {10.1109/JSSC.2011.2164294},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/NikiKSTHKTFY11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/PuZIMKTNSS11,
author = {Yu Pu and
Xin Zhang and
Katsuyuki Ikeuchi and
Atsushi Muramatsu and
Atsushi Kawasumi and
Makoto Takamiya and
Masahiro Nomura and
Hirofumi Shinohara and
Takayasu Sakurai},
title = {Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming
With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near
Threshold Digital Circuits},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {58-II},
number = {5},
pages = {294--298},
year = {2011},
url = {https://doi.org/10.1109/TCSII.2011.2149050},
doi = {10.1109/TCSII.2011.2149050},
timestamp = {Wed, 27 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/PuZIMKTNSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KushidaHTHKSTFN11,
author = {Keiichi Kushida and
Osamu Hirabayashi and
Fumihiko Tachibana and
Hiroyuki Hara and
Atsushi Kawasumi and
Azuma Suzuki and
Yasuhisa Takeyama and
Yuki Fujimura and
Yusuke Niki and
Miyako Shizuno and
Shinichi Sasaki and
Tomoaki Yabe},
title = {A trimless, 0.5V-1.0V wide voltage operation, high density {SRAM}
macro utilizing dynamic cell stability monitor and multiple memory
cell access},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {161--164},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123627},
doi = {10.1109/ASSCC.2011.6123627},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/asscc/KushidaHTHKSTFN11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asscc/KawasumiSMM11,
author = {Atsushi Kawasumi and
Toshikazu Suzuki and
Shinichi Moriwaki and
Shinji Miyano},
title = {Energy efficiency degradation caused by random variation in low-voltage
{SRAM} and 26{\%} energy reduction by Bitline Amplitude Limiting {(BAL)}
scheme},
booktitle = {{IEEE} Asian Solid-State Circuits Conference, {A-SSCC} 2011, Jeju,
South Korea, November 14-16, 2011},
pages = {165--168},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASSCC.2011.6123628},
doi = {10.1109/ASSCC.2011.6123628},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asscc/KawasumiSMM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/MoriwakiKSSM11,
author = {Shinichi Moriwaki and
Atsushi Kawasumi and
Toshikazu Suzuki and
Takayasu Sakurai and
Shinji Miyano},
editor = {Rakesh Patel and
Tom Andre and
Aurangzeb Khan},
title = {0.4V {SRAM} with bit line swing suppression charge share hierarchical
bit line scheme},
booktitle = {2011 {IEEE} Custom Integrated Circuits Conference, {CICC} 2011, San
Jose, CA, USA, Sept. 19-21, 2011},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/CICC.2011.6055398},
doi = {10.1109/CICC.2011.6055398},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/cicc/MoriwakiKSSM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KawasumiTHKFY10,
author = {Atsushi Kawasumi and
Yasuhisa Takeyama and
Osamu Hirabayashi and
Keiichi Kushida and
Yuki Fujimura and
Tomoaki Yabe},
title = {A Low-Supply-Voltage-Operation {SRAM} With {HCI} Trimmed Sense Amplifiers},
journal = {{IEEE} J. Solid State Circuits},
volume = {45},
number = {11},
pages = {2341--2347},
year = {2010},
url = {https://doi.org/10.1109/JSSC.2010.2065750},
doi = {10.1109/JSSC.2010.2065750},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KawasumiTHKFY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/esscirc/SuzukiMKMS10,
author = {Toshikazu Suzuki and
Shinichi Moriwaki and
Atsushi Kawasumi and
Shinji Miyano and
Hirofumi Shinohara},
title = {0.5-V, 150-MHz, bulk-CMOS {SRAM} with suspended bit-line read scheme},
booktitle = {36th European Solid-State Circuits Conference, {ESSCIRC} 2010, Sevilla,
Spain, September 13-17, 2010},
pages = {354--357},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ESSCIRC.2010.5619716},
doi = {10.1109/ESSCIRC.2010.5619716},
timestamp = {Mon, 09 Aug 2021 14:54:02 +0200},
biburl = {https://dblp.org/rec/conf/esscirc/SuzukiMKMS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FujimuraHSSKTKFKNY10,
author = {Yuki Fujimura and
Osamu Hirabayashi and
Takahiko Sasaki and
Azuma Suzuki and
Atsushi Kawasumi and
Yasuhisa Takeyama and
Keiichi Kushida and
Gou Fukano and
Akira Katayama and
Yusuke Niki and
Tomoaki Yabe},
title = {A configurable {SRAM} with constant-negative-level write buffer for
low-voltage operation with 0.149{\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
cell in 32nm high-k metal-gate {CMOS}},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2010,
Digest of Technical Papers, San Francisco, CA, USA, 7-11 February,
2010},
pages = {348--349},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISSCC.2010.5433813},
doi = {10.1109/ISSCC.2010.5433813},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FujimuraHSSKTKFKNY10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KushidaSFKHTSKF09,
author = {Keiichi Kushida and
Azuma Suzuki and
Gou Fukano and
Atsushi Kawasumi and
Osamu Hirabayashi and
Yasuhisa Takeyama and
Takahiko Sasaki and
Akira Katayama and
Yuki Fujimura and
Tomoaki Yabe},
title = {A 0.7 {V} Single-Supply {SRAM} With 0.495 {\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier
and Cascaded Bit Line Scheme},
journal = {{IEEE} J. Solid State Circuits},
volume = {44},
number = {4},
pages = {1192--1198},
year = {2009},
url = {https://doi.org/10.1109/JSSC.2009.2014009},
doi = {10.1109/JSSC.2009.2014009},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KushidaSFKHTSKF09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/HirabayashiKSTKSKFFNSKY09,
author = {Osamu Hirabayashi and
Atsushi Kawasumi and
Azuma Suzuki and
Yasuhisa Takeyama and
Keiichi Kushida and
Takahiko Sasaki and
Akira Katayama and
Gou Fukano and
Yuki Fujimura and
Takaaki Nakazato and
Yasushi Shizuki and
Natsuki Kushiyama and
Tomoaki Yabe},
title = {A process-variation-tolerant dual-power-supply {SRAM} with 0.179{\(\mathrm{\mu}\)}m\({}^{\mbox{2}}\)
Cell in 40nm {CMOS} using level-programmable wordline driver},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {458--459},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977506},
doi = {10.1109/ISSCC.2009.4977506},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/HirabayashiKSTKSKFFNSKY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KawasumiYTHKTSKFFO08,
author = {Atsushi Kawasumi and
Tomoaki Yabe and
Yasuhisa Takeyama and
Osamu Hirabayashi and
Keiichi Kushida and
Akihito Tohata and
Takahiko Sasaki and
Akira Katayama and
Gou Fukano and
Yuki Fujimura and
Nobuaki Otsuka},
title = {A Single-Power-Supply 0.7V 1GHz 45nm {SRAM} with An Asymmetrical Unit-{\texttimes}-ratio
Memory Cell},
booktitle = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2008, Digest of Technical Papers, San Francisco, CA, USA, February
3-7, 2008},
pages = {382--383},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISSCC.2008.4523217},
doi = {10.1109/ISSCC.2008.4523217},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KawasumiYTHKTSKFFO08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ibmrd/FlachsADHGKLLLLMOMTHKMNOPSYHWYBPTI07,
author = {Brian K. Flachs and
Shigehiro Asano and
Sang H. Dhong and
H. Peter Hofstee and
Gilles Gervais and
Roy Kim and
Tien Le and
Peichun Liu and
Jens Leenstra and
John S. Liberty and
Brad W. Michael and
Hwa{-}Joon Oh and
Silvia M. M{\"{u}}ller and
Osamu Takahashi and
Koji Hirairi and
Atsushi Kawasumi and
Hiroaki Murakami and
Hiromi Noro and
Shoji Onishi and
Juergen Pille and
Joel Silberman and
Suksoon Yong and
Akiyuki Hatakeyama and
Yukio Watanabe and
Naoka Yano and
Daniel A. Brokenshire and
Mohammad Peyravian and
VanDung To and
Eiji Iwata},
title = {Microarchitecture and implementation of the synergistic processor
in 65-nm and 90-nm {SOI}},
journal = {{IBM} J. Res. Dev.},
volume = {51},
number = {5},
pages = {529--544},
year = {2007},
url = {https://doi.org/10.1147/rd.515.0529},
doi = {10.1147/RD.515.0529},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ibmrd/FlachsADHGKLLLLMOMTHKMNOPSYHWYBPTI07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/AsanoSDTWCNKY05,
author = {Toru Asano and
Joel Silberman and
Sang H. Dhong and
Osamu Takahashi and
Michael White and
Scott R. Cottier and
Takaaki Nakazato and
Atsushi Kawasumi and
Hiroshi Yoshihara},
title = {Low-Power Design Approach of 11FO4 256-Kbyte Embedded {SRAM} for the
Synergistic Processor Element of a Cell Processor},
journal = {{IEEE} Micro},
volume = {25},
number = {5},
pages = {30--38},
year = {2005},
url = {https://doi.org/10.1109/MM.2005.94},
doi = {10.1109/MM.2005.94},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/AsanoSDTWCNKY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/TakahashiCCDFHKMNOOPS05,
author = {Osamu Takahashi and
Russ Cook and
Scott R. Cottier and
Sang H. Dhong and
Brian K. Flachs and
Koji Hirairi and
Atsushi Kawasumi and
Hiroaki Murakami and
Hiromi Noro and
Hwa{-}Joon Oh and
S. Onish and
Juergen Pille and
Joel Silberman},
title = {The circuit design of the synergistic processor element of a {CELL}
processor},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {111--117},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560049},
doi = {10.1109/ICCAD.2005.1560049},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/TakahashiCCDFHKMNOOPS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/HirabayashiSYKTKTO02,
author = {Osamu Hirabayashi and
Azuma Suzuki and
Tomoaki Yabe and
Atsushi Kawasumi and
Yasuhisa Takeyama and
Keiichi Kushida and
Akihito Tohata and
Nobuaki Otsuka},
title = {{DFT} Techniques for Wafer-Level At-Speed Testing of High-Speed SRAMs},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {164--169},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041757},
doi = {10.1109/TEST.2002.1041757},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/HirabayashiSYKTKTO02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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