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ORCIDBibTeX records: Naoaki Kanagawa
@inproceedings{DBLP:conf/vlsit/SakoNKNFMNKSYUK23,
author = {Mario Sako and
T. Nakajima and
Fumihiro Kono and
T. Nakano and
Masaki Fujiu and
Junji Musha and
Dai Nakamura and
Naoaki Kanagawa and
Y. Shimizu and
Kosuke Yanagidaira and
Tetsuaki Utsumi and
T. Kawano and
Yoshikazu Hosomura and
Hiroki Yabe and
M. Kano and
Hiroshi Sugawara and
A. H. Sravan and
K. Hayashi and
Toshiyuki Kouchi and
Y. Watanabe},
title = {A 1Tb 3b/Cell 3D-Flash Memory of more than 17Gb/mm\({}^{\mbox{2}}\)
bit density with 3.2Gbps interface and 205MB/s program throughput},
booktitle = {2023 {IEEE} Symposium on {VLSI} Technology and Circuits {(VLSI} Technology
and Circuits), Kyoto, Japan, June 11-16, 2023},
pages = {1--2},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.23919/VLSITechnologyandCir57934.2023.10185237},
doi = {10.23919/VLSITECHNOLOGYANDCIR57934.2023.10185237},
timestamp = {Fri, 28 Jul 2023 10:40:41 +0200},
biburl = {https://dblp.org/rec/conf/vlsit/SakoNKNFMNKSYUK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KouchiKKSIKTBKK21,
author = {Toshiyuki Kouchi and
Mami Kakoi and
Noriyasu Kumazaki and
Akio Sugahara and
Akihiro Imamoto and
Yasufumi Kajiyama and
Yuri Terada and
Sanad Bushnaq and
Naoaki Kanagawa and
Takuyo Kodama and
Ryo Fukuda and
Hiromitsu Komai and
Norichika Asaoka and
Hidekazu Ohnishi and
Ryosuke Isomura and
Takaya Handa and
Kensuke Yamamoto and
Yuki Ishizaki and
Yoko Deguchi and
Atsushi Okuyama and
Junichi Sato and
Hiroki Yabe and
Cynthia Hsu and
Masahiro Yoshihara},
title = {A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the
Random Read Latency With tProg = 75 {\(\mu\)}s and tR = 4 {\(\mu\)}s},
journal = {{IEEE} J. Solid State Circuits},
volume = {56},
number = {1},
pages = {225--234},
year = {2021},
url = {https://doi.org/10.1109/JSSC.2020.3028393},
doi = {10.1109/JSSC.2020.3028393},
timestamp = {Sat, 09 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/KouchiKKSIKTBKK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/KouchiKYBKIDSIA20,
author = {Toshiyuki Kouchi and
Noriyasu Kumazaki and
Masashi Yamaoka and
Sanad Bushnaq and
Takuyo Kodama and
Yuki Ishizaki and
Yoko Deguchi and
Akio Sugahara and
Akihiro Imamoto and
Norichika Asaoka and
Ryosuke Isomura and
Takaya Handa and
Junichi Sato and
Hiromitsu Komai and
Atsushi Okuyama and
Naoaki Kanagawa and
Yasufumi Kajiyama and
Yuri Terada and
Hidekazu Ohnishi and
Hiroki Yabe and
Cynthia Hsu and
Mami Kakoi and
Masahiro Yoshihara},
title = {13.5 {A} 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve
Random Read Latency with tPROG=75{\(\mathrm{\mu}\)}s and tR=4{\(\mathrm{\mu}\)}s},
booktitle = {2020 {IEEE} International Solid- State Circuits Conference, {ISSCC}
2020, San Francisco, CA, USA, February 16-20, 2020},
pages = {226--228},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISSCC19947.2020.9063154},
doi = {10.1109/ISSCC19947.2020.9063154},
timestamp = {Sat, 18 Apr 2020 17:41:44 +0200},
biburl = {https://dblp.org/rec/conf/isscc/KouchiKYBKIDSIA20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/MaejimaKFTOSSSK18,
author = {Hiroshi Maejima and
Kazushige Kanda and
Susumu Fujimura and
Teruo Takagiwa and
Susumu Ozawa and
Jumpei Sato and
Yoshihiko Shindo and
Manabu Sato and
Naoaki Kanagawa and
Junji Musha and
Satoshi Inoue and
Katsuaki Sakurai and
Naohito Morozumi and
Ryo Fukuda and
Yuui Shimizu and
Toshifumi Hashimoto and
Xu Li and
Yuki Shimizu and
Kenichi Abe and
Tadashi Yasufuku and
Takatoshi Minamoto and
Hiroshi Yoshihara and
Takahiro Yamashita and
Kazuhiko Satou and
Takahiro Sugimoto and
Fumihiro Kono and
Mitsuhiro Abe and
Tomoharu Hashiguchi and
Masatsugu Kojima and
Yasuhiro Suematsu and
Takahiro Shimizu and
Akihiro Imamoto and
Naoki Kobayashi and
Makoto Miakashi and
Kouichirou Yamaguchi and
Sanad Bushnaq and
Hicham Haibi and
Masatsugu Ogawa and
Yusuke Ochi and
Kenro Kubota and
Taichi Wakui and
Dong He and
Weihan Wang and
Hiroe Minagawa and
Tomoko Nishiuchi and
Hao Nguyen and
Kwang{-}Ho Kim and
Ken Cheah and
Yee Lih Koh and
Feng Lu and
Venky Ramachandra and
Srinivas Rajendra and
Steve Choi and
Keyur Payak and
Namas Raghunathan and
Spiros Georgakis and
Hiroshi Sugawara and
Seungpil Lee and
Takuya Futatsuyama and
Koji Hosono and
Noboru Shibata and
Toshiki Hisada and
Tetsuya Kaneko and
Hiroshi Nakamura},
title = {A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology},
booktitle = {2018 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2018, San Francisco, CA, USA, February 11-15, 2018},
pages = {336--338},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISSCC.2018.8310321},
doi = {10.1109/ISSCC.2018.8310321},
timestamp = {Tue, 14 Jan 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/MaejimaKFTOSSSK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KandaSHISSSSKKKOIKSSSFUHKMISHKZCWDOY13,
author = {Kazushige Kanda and
Noboru Shibata and
Toshiki Hisada and
Katsuaki Isobe and
Manabu Sato and
Yui Shimizu and
Takahiro Shimizu and
Takahiro Sugimoto and
Tomohiro Kobayashi and
Naoaki Kanagawa and
Yasuyuki Kajitani and
Takeshi Ogawa and
Kiyoaki Iwasa and
Masatsugu Kojima and
Toshihiro Suzuki and
Yuya Suzuki and
Shintaro Sakai and
Tomofumi Fujimura and
Yuko Utsunomiya and
Toshifumi Hashimoto and
Naoki Kobayashi and
Yuuki Matsumoto and
Satoshi Inoue and
Yoshinao Suzuki and
Yasuhiko Honda and
Yosuke Kato and
Shingo Zaitsu and
Hardwell Chibvongodze and
Mitsuyuki Watanabe and
Hong Ding and
Naoki Ookuma and
Ryuji Yamashita},
title = {A 19 nm 112.8 mm\({}^{\mbox{2}}\) 64 Gb Multi-Level Flash Memory With
400 Mbit/sec/pin 1.8 {V} Toggle Mode Interface},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {1},
pages = {159--167},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2215094},
doi = {10.1109/JSSC.2012.2215094},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KandaSHISSSSKKKOIKSSSFUHKMISHKZCWDOY13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/FukudaWMKSTKSTSOEINMMFYSNHTKMSYSSDWKMMNHLHMLMNH12,
author = {Koichi Fukuda and
Yoshihisa Watanabe and
Eiichi Makino and
Koichi Kawakami and
Jumpei Sato and
Teruo Takagiwa and
Naoaki Kanagawa and
Hitoshi Shiga and
Naoya Tokiwa and
Yoshihiko Shindo and
Takeshi Ogawa and
Toshiaki Edahiro and
Makoto Iwai and
Osamu Nagao and
Junji Musha and
Takatoshi Minamoto and
Yuka Furuta and
Kosuke Yanagidaira and
Yuya Suzuki and
Dai Nakamura and
Yoshikazu Hosomura and
Rieko Tanaka and
Hiromitsu Komai and
Mai Muramoto and
Go Shikata and
Ayako Yuminaka and
Kiyofumi Sakurai and
Manabu Sakai and
Hong Ding and
Mitsuyuki Watanabe and
Yosuke Kato and
Toru Miwa and
Alex Mak and
Masaru Nakamichi and
Gertjan Hemink and
Dana Lee and
Masaaki Higashitani and
Brian Murphy and
Bo Lei and
Yasuhiko Matsunaga and
Kiyomi Naruke and
Takahiko Hara},
title = {A 151-mm\({}^{\mbox{2}}\) 64-Gb 2 Bit/Cell {NAND} Flash Memory in
24-nm {CMOS} Technology},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {1},
pages = {75--84},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2011.2164711},
doi = {10.1109/JSSC.2011.2164711},
timestamp = {Sun, 30 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/FukudaWMKSTKSTSOEINMMFYSNHTKMSYSSDWKMMNHLHMLMNH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/ShibataKH12,
author = {Noboru Shibata and
Kazushige Kanda and
Toshiki Hisada and
Katsuaki Isobe and
Manabu Sato and
Yui Shimizu and
Takahiro Shimizu and
Takahiro Sugimoto and
Tomohiro Kobayashi and
Kazuko Inuzuka and
Naoaki Kanagawa and
Yasuyuki Kajitani and
Takeshi Ogawa and
J. Nakai and
Kiyoaki Iwasa and
Masatsugu Kojima and
Toshihiro Suzuki and
Yuya Suzuki and
Shintaro Sakai and
Tomofumi Fujimura and
Yuko Utsunomiya and
Toshifumi Hashimoto and
Makoto Miakashi and
Naoki Kobayashi and
M. Inagaki and
Yuuki Matsumoto and
Satoshi Inoue and
Yoshinao Suzuki and
D. He and
Yasuhiko Honda and
Junji Musha and
Masaki Nakagawa and
Mitsuaki Honma and
Naofumi Abiko and
Mitsumasa Koyanagi and
Masahiro Yoshihara and
Kazumi Ino and
Mitsuhiro Noguchi and
Teruhiko Kamei and
Yosuke Kato and
Shingo Zaitsu and
Hiroaki Nasu and
Takuya Ariki and
Hardwell Chibvongodze and
Mitsuyuki Watanabe and
Hong Ding and
Naoki Ookuma and
Ryuji Yamashita and
G. Liang and
Gertjan Hemink and
Farookh Moogat and
Cuong Trinh and
Masaaki Higashitani and
Tuan Pham and
Kousuke Kanazawa},
title = {A 19nm 112.8mm\({}^{\mbox{2}}\) 64Gb multi-level flash memory with
400Mb/s/pin 1.8V Toggle Mode interface},
booktitle = {2012 {IEEE} International Solid-State Circuits Conference, {ISSCC}
2012, San Francisco, CA, USA, February 19-23, 2012},
pages = {422--424},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSCC.2012.6177073},
doi = {10.1109/ISSCC.2012.6177073},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isscc/ShibataKH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FukudaWMKSTKSTSEOINMMYSNHKFMTSYSSDWKMMNHLHMLMNH11,
author = {Koichi Fukuda and
Yoshihisa Watanabe and
Eiichi Makino and
Koichi Kawakami and
Jumpei Sato and
Teruo Takagiwa and
Naoaki Kanagawa and
Hitoshi Shiga and
Naoya Tokiwa and
Yoshihiko Shindo and
Toshiaki Edahiro and
Takeshi Ogawa and
Makoto Iwai and
Osamu Nagao and
Junji Musha and
Takatoshi Minamoto and
Kosuke Yanagidaira and
Yuya Suzuki and
Dai Nakamura and
Yoshikazu Hosomura and
Hiromitsu Komai and
Yuka Furuta and
Mai Muramoto and
Rieko Tanaka and
Go Shikata and
Ayako Yuminaka and
Kiyofumi Sakurai and
Manabu Sakai and
Hong Ding and
Mitsuyuki Watanabe and
Yosuke Kato and
Toru Miwa and
Alex Mak and
Masaru Nakamichi and
Gertjan Hemink and
Dana Lee and
Masaaki Higashitani and
Brian Murphy and
Bo Lei and
Yasuhiko Matsunaga and
Kiyomi Naruke and
Takahiko Hara},
title = {A 151mm\({}^{\mbox{2}}\) 64Gb {MLC} {NAND} flash memory in 24nm {CMOS}
technology},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2011,
Digest of Technical Papers, San Francisco, CA, USA, 20-24 February,
2011},
pages = {198--199},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISSCC.2011.5746280},
doi = {10.1109/ISSCC.2011.5746280},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FukudaWMKSTKSTSEOINMMYSNHKFMTSYSSDWKMMNHLHMLMNH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isscc/FutatsuyamaFTSEKNIKFKAMHHLCHSDTSKKSYSNFMNLMLMWHO09,
author = {Takuya Futatsuyama and
Norihiro Fujita and
Naoya Tokiwa and
Yoshihiko Shindo and
Toshiaki Edahiro and
Teruhiko Kamei and
Hiroaki Nasu and
Makoto Iwai and
Koji Kato and
Yasuyuki Fukuda and
Naoaki Kanagawa and
Naofumi Abiko and
Masahide Matsumoto and
Toshihiko Himeno and
Toshifumi Hashimoto and
Yi{-}Ching Liu and
Hardwell Chibvongodze and
Takamitsu Hori and
Manabu Sakai and
Hong Ding and
Yoshiharu Takeuchi and
Hitoshi Shiga and
Norifumi Kajimura and
Yasuyuki Kajitani and
Kiyofumi Sakurai and
Kosuke Yanagidaira and
Toshihiro Suzuki and
Yuko Namiki and
Tomofumi Fujimura and
Man Mui and
Hao Nguyen and
Seungpil Lee and
Alex Mak and
Jeffery Lutze and
Tooru Maruyama and
Toshiharu Watanabe and
Takahiko Hara and
Shigeo Ohshima},
title = {A 113mm2 32Gb 3b/cell {NAND} flash memory},
booktitle = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
2009},
pages = {242--243},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISSCC.2009.4977398},
doi = {10.1109/ISSCC.2009.4977398},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isscc/FutatsuyamaFTSEKNIKFKAMHHLCHSDTSKKSYSNFMNLMLMWHO09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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