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ORCIDBibTeX records: Michitaka Kameyama
@inproceedings{DBLP:conf/idt2/LukacK23,
author = {Martin Lukac and
Michitaka Kameyama},
title = {Verification Based Algorithm Selection},
booktitle = {International Conference on Information and Digital Technologies,
{IDT} 2023, Zilina, Slovakia, June 20-22, 2023},
pages = {25--30},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IDT59031.2023.10194439},
doi = {10.1109/IDT59031.2023.10194439},
timestamp = {Fri, 18 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/idt2/LukacK23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccS/LukacPK22,
author = {Martin Lukac and
Krzysztof Podlaski and
Michitaka Kameyama},
editor = {Derek Groen and
Cl{\'{e}}lia de Mulatier and
Maciej Paszynski and
Valeria V. Krzhizhanovskaya and
Jack J. Dongarra and
Peter M. A. Sloot},
title = {Approximate Function Classification},
booktitle = {Computational Science - {ICCS} 2022 - 22nd International Conference,
London, UK, June 21-23, 2022, Proceedings, Part {II}},
series = {Lecture Notes in Computer Science},
volume = {13351},
pages = {207--213},
publisher = {Springer},
year = {2022},
url = {https://doi.org/10.1007/978-3-031-08754-7\_28},
doi = {10.1007/978-3-031-08754-7\_28},
timestamp = {Tue, 28 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccS/LukacPK22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcsc/LukacKK21,
author = {Martin Lukac and
Pawel Kerntopf and
Michitaka Kameyama},
title = {Optimization of {LNN} Reversible Circuits Using an Analytic Sifting
Method},
journal = {J. Circuits Syst. Comput.},
volume = {30},
number = {9},
pages = {2150166:1--2150166:23},
year = {2021},
url = {https://doi.org/10.1142/S0218126621501668},
doi = {10.1142/S0218126621501668},
timestamp = {Thu, 16 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcsc/LukacKK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icpr/LukacBLAIGK20,
author = {Martin Lukac and
Ayazkhan Bayanov and
Albina Li and
Kamila Abdiyeva and
Nadira Izbassarova and
Magzhan Gabidolla and
Michitaka Kameyama},
editor = {Alberto Del Bimbo and
Rita Cucchiara and
Stan Sclaroff and
Giovanni Maria Farinella and
Tao Mei and
Marco Bertini and
Hugo Jair Escalante and
Roberto Vezzani},
title = {Selecting Algorithms Without Meta-features},
booktitle = {Pattern Recognition. {ICPR} International Workshops and Challenges
- Virtual Event, January 10-15, 2021, Proceedings, Part {IV}},
series = {Lecture Notes in Computer Science},
volume = {12664},
pages = {607--621},
publisher = {Springer},
year = {2020},
url = {https://doi.org/10.1007/978-3-030-68799-1\_44},
doi = {10.1007/978-3-030-68799-1\_44},
timestamp = {Tue, 11 Apr 2023 17:29:51 +0200},
biburl = {https://dblp.org/rec/conf/icpr/LukacBLAIGK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LukacAK18,
author = {Martin Lukac and
Kamila Abdiyeva and
Michitaka Kameyama},
title = {CNOT-Measure Quantum Neural Networks},
booktitle = {48th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2018, Linz, Austria, May 16-18, 2018},
pages = {186--191},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ISMVL.2018.00040},
doi = {10.1109/ISMVL.2018.00040},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LukacAK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smc/TakadaK18,
author = {Kenichi Takada and
Michitaka Kameyama},
title = {High-Accuracy Scene Recognition and Its Application to Highly-Safe
Intelligent Systems},
booktitle = {{IEEE} International Conference on Systems, Man, and Cybernetics,
{SMC} 2018, Miyazaki, Japan, October 7-10, 2018},
pages = {2528--2533},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SMC.2018.00433},
doi = {10.1109/SMC.2018.00433},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/smc/TakadaK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ShimabukuroK17,
author = {Katsuhiko Shimabukuro and
Michitaka Kameyama},
title = {Fine-Grain Pipelined Reconfigurable {VLSI} Architecture Based on Multiple-Valued
Multiplexer Logic},
booktitle = {47th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2017, Novi Sad, Serbia, May 22-24, 2017},
pages = {19--24},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ISMVL.2017.45},
doi = {10.1109/ISMVL.2017.45},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ShimabukuroK17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/smc/LukacKM17,
author = {Martin Lukac and
Michitaka Kameyama and
Yevgeniya Migranova},
title = {Live-feeling communication: Multi-algorithm approach to the estimation
of human intentions},
booktitle = {2017 {IEEE} International Conference on Systems, Man, and Cybernetics,
{SMC} 2017, Banff, AB, Canada, October 5-8, 2017},
pages = {2152--2157},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/SMC.2017.8122938},
doi = {10.1109/SMC.2017.8122938},
timestamp = {Wed, 16 Oct 2019 14:14:51 +0200},
biburl = {https://dblp.org/rec/conf/smc/LukacKM17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/LukacDKP17,
author = {Martin Lukac and
Gerhard W. Dueck and
Michitaka Kameyama and
Anirban Pathak},
title = {Building a Completely Reversible Computer},
journal = {CoRR},
volume = {abs/1702.08715},
year = {2017},
url = {http://arxiv.org/abs/1702.08715},
eprinttype = {arXiv},
eprint = {1702.08715},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/LukacDKP17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1709-00141,
author = {Martin Lukac and
Aigerim Bazarbayeva and
Michitaka Kameyama},
title = {Context Based Visual Content Verification},
journal = {CoRR},
volume = {abs/1709.00141},
year = {2017},
url = {http://arxiv.org/abs/1709.00141},
eprinttype = {arXiv},
eprint = {1709.00141},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1709-00141.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/LukacAK16,
author = {Martin Lukac and
Kamila Abdiyeva and
Michitaka Kameyama},
title = {Reasoning and Algorithm Selection Augmented Symbolic Segmentation},
journal = {CoRR},
volume = {abs/1608.03667},
year = {2016},
url = {http://arxiv.org/abs/1608.03667},
eprinttype = {arXiv},
eprint = {1608.03667},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/LukacAK16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/LukacAK16a,
author = {Martin Lukac and
Kamila Abdiyeva and
Michitaka Kameyama},
title = {On Minimal Accuracy Algorithm Selection in Computer Vision and Intelligent
Systems},
journal = {CoRR},
volume = {abs/1608.03832},
year = {2016},
url = {http://arxiv.org/abs/1608.03832},
eprinttype = {arXiv},
eprint = {1608.03832},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/LukacAK16a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TakeiWHK15,
author = {Yasuhiro Takei and
Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore
Platform with Custom Accelerators},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {98-A},
number = {12},
pages = {2658--2669},
year = {2015},
url = {https://doi.org/10.1587/transfun.E98.A.2658},
doi = {10.1587/TRANSFUN.E98.A.2658},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TakeiWHK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mlc/LukacK15,
author = {Martin Lukac and
Michitaka Kameyama},
title = {An algorithm selection based platform for image understanding using
high-level symbolic feedback and machine learning},
journal = {Int. J. Mach. Learn. Cybern.},
volume = {6},
number = {3},
pages = {417--434},
year = {2015},
url = {https://doi.org/10.1007/s13042-013-0197-x},
doi = {10.1007/S13042-013-0197-X},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mlc/LukacK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiaHK15,
author = {Zhengfan Xia and
Masanori Hariyama and
Michitaka Kameyama},
title = {Asynchronous Domino Logic Pipeline Design Based on Constructed Critical
Data Path},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {23},
number = {4},
pages = {619--630},
year = {2015},
url = {https://doi.org/10.1109/TVLSI.2014.2314685},
doi = {10.1109/TVLSI.2014.2314685},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiaHK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Kameyama15,
author = {Michitaka Kameyama},
title = {Novel {VLSI} Architectures for Real-World Intelligent Systems},
booktitle = {2015 {IEEE} International Symposium on Multiple-Valued Logic, Waterloo,
ON, Canada, May 18-20, 2015},
pages = {132},
publisher = {{IEEE} Computer Society},
year = {2015},
url = {https://doi.org/10.1109/ISMVL.2015.39},
doi = {10.1109/ISMVL.2015.39},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Kameyama15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/LukacAK15,
author = {Martin Lukac and
Kamila Abdiyeva and
Michitaka Kameyama},
title = {Symbolic Segmentation Using Algorithm Selection},
journal = {CoRR},
volume = {abs/1505.07934},
year = {2015},
url = {http://arxiv.org/abs/1505.07934},
eprinttype = {arXiv},
eprint = {1505.07934},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/LukacAK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/LukacSPK14,
author = {Martin Lukac and
Dipal Shah and
Marek A. Perkowski and
Michitaka Kameyama},
title = {Synthesis of Quantum Arrays from Kronecker Functional Lattice Diagrams},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {97-D},
number = {9},
pages = {2262--2269},
year = {2014},
url = {https://doi.org/10.1587/transinf.2013LOP0015},
doi = {10.1587/TRANSINF.2013LOP0015},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/LukacSPK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/BaiK14,
author = {Xu Bai and
Michitaka Kameyama},
title = {Multiple-Valued Fine-Grain Reconfigurable {VLSI} Using a Global Tree
Local X-Net Network},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {97-D},
number = {9},
pages = {2278--2285},
year = {2014},
url = {https://doi.org/10.1587/transinf.2013LOP0006},
doi = {10.1587/TRANSINF.2013LOP0006},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/BaiK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/BaiK14a,
author = {Xu Bai and
Michitaka Kameyama},
title = {Implementation of Voltage-Mode/Current-Mode Hybrid Circuits for a
Low-Power Fine-Grain Reconfigurable {VLSI}},
journal = {{IEICE} Trans. Electron.},
volume = {97-C},
number = {10},
pages = {1028--1035},
year = {2014},
url = {https://doi.org/10.1587/transele.E97.C.1028},
doi = {10.1587/TRANSELE.E97.C.1028},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/BaiK14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jcengi/WaidyasooriyaHT14,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Yasuhiro Takei and
Michitaka Kameyama},
title = {{FDTD} Acceleration for Cylindrical Resonator Design Based on the
Hybrid of Single and Double Precision Floating-Point Computation},
journal = {J. Comput. Eng.},
volume = {2014},
pages = {634269:1--634269:8},
year = {2014},
url = {https://doi.org/10.1155/2014/634269},
doi = {10.1155/2014/634269},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jcengi/WaidyasooriyaHT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/LukacSKM14,
author = {Martin Lukac and
Ben Shuai and
Michitaka Kameyama and
D. Michael Miller},
title = {Reversible, Information-Preserving Logic and Its Application},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {23},
number = {3-4},
pages = {379--406},
year = {2014},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-23-number-3-4-2014/mvlsc-23-3-4-p-379-406/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/LukacSKM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/WaidyasooriyaOHK14,
author = {Hasitha Muthumala Waidyasooriya and
Daisuke Ono and
Masanori Hariyama and
Michitaka Kameyama},
title = {Efficient data transfer scheme using word-pair-encoding-based compression
for large-scale text-data processing},
booktitle = {2014 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2014, Ishigaki, Japan, November 17-20, 2014},
pages = {639--642},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/APCCAS.2014.7032862},
doi = {10.1109/APCCAS.2014.7032862},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/WaidyasooriyaOHK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dsd/LukacHKPK14,
author = {Martin Lukac and
Maher Hawash and
Michitaka Kameyama and
Marek A. Perkowski and
Pawel Kerntopf},
title = {Minimizing Reversible Circuits in the 2n Scheme Using Two and Three
Bits Patterns},
booktitle = {17th Euromicro Conference on Digital System Design, {DSD} 2014, Verona,
Italy, August 27-29, 2014},
pages = {708--711},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/DSD.2014.106},
doi = {10.1109/DSD.2014.106},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dsd/LukacHKPK14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LukacKPKM14,
author = {Martin Lukac and
Michitaka Kameyama and
Marek A. Perkowski and
Pawel Kerntopf and
Claudio Moraga},
title = {Analysis of Faults in Reversible Computing},
booktitle = {{IEEE} 44th International Symposium on Multiple-Valued Logic, {ISMVL}
2014, Bremen, Germany, May 19-21, 2014},
pages = {115--120},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISMVL.2014.28},
doi = {10.1109/ISMVL.2014.28},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LukacKPKM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HaradaBKF14,
author = {Shintaro Harada and
Xu Bai and
Michitaka Kameyama and
Yoshichika Fujioka},
title = {Design of a Logic-in-Memory Multiple-Valued Reconfigurable {VLSI}
Based on a Bit-Serial Packet Data Transfer Scheme},
booktitle = {{IEEE} 44th International Symposium on Multiple-Valued Logic, {ISMVL}
2014, Bremen, Germany, May 19-21, 2014},
pages = {214--219},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/ISMVL.2014.45},
doi = {10.1109/ISMVL.2014.45},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HaradaBKF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/adhoc/NejadJK13,
author = {Keyvan Kashkouli Nejad and
Xiaohong Jiang and
Michitaka Kameyama},
title = {RFID-based localization with Non-Blocking tag scanning},
journal = {Ad Hoc Networks},
volume = {11},
number = {8},
pages = {2264--2272},
year = {2013},
url = {https://doi.org/10.1016/j.adhoc.2013.05.007},
doi = {10.1016/J.ADHOC.2013.05.007},
timestamp = {Thu, 19 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/adhoc/NejadJK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/BaiK13,
author = {Xu Bai and
Michitaka Kameyama},
title = {A Bit-Serial Reconfigurable {VLSI} Based on a Multiple-Valued X-Net
Data Transfer Scheme},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {7},
pages = {1449--1456},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1449},
doi = {10.1587/TRANSINF.E96.D.1449},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/BaiK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/BaiK13a,
author = {Xu Bai and
Michitaka Kameyama},
title = {A Multiple-Valued Reconfigurable {VLSI} Architecture Using Binary-Controlled
Differential-Pair Circuits},
journal = {{IEICE} Trans. Electron.},
volume = {96-C},
number = {8},
pages = {1083--1093},
year = {2013},
url = {https://doi.org/10.1587/transele.E96.C.1083},
doi = {10.1587/TRANSELE.E96.C.1083},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/BaiK13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KomatsuHK13,
author = {Yoshiya Komatsu and
Masanori Hariyama and
Michitaka Kameyama},
title = {Architecture of an Asynchronous {FPGA} for Handshake-Component-Based
Design},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {8},
pages = {1632--1644},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1632},
doi = {10.1587/TRANSINF.E96.D.1632},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KomatsuHK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/TakeiWHK13,
author = {Yasuhiro Takei and
Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Evaluation of an FPGA-Based Heterogeneous Multicore Platform with
{SIMD/MIMD} Custom Accelerators},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {96-A},
number = {12},
pages = {2576--2586},
year = {2013},
url = {https://doi.org/10.1587/transfun.E96.A.2576},
doi = {10.1587/TRANSFUN.E96.A.2576},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/TakeiWHK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijuc/LukacKP13,
author = {Martin Lukac and
Michitaka Kameyama and
Marek A. Perkowski},
title = {Quantum Finite State Machines - a Circuit Based Approach},
journal = {Int. J. Unconv. Comput.},
volume = {9},
number = {3-4},
pages = {267--301},
year = {2013},
url = {http://www.oldcitypublishing.com/journals/ijuc-home/ijuc-issue-contents/ijuc-volume-9-number-3-4-2013/ijuc-9-3-4-p-267-301/},
timestamp = {Thu, 16 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijuc/LukacKP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/IshiharaIHK13,
author = {Shota Ishihara and
Noriaki Idobata and
Masanori Hariyama and
Michitaka Kameyama},
title = {Flexible Ferroelectric-Capacitor Element for Low Power and Compact
Logic-in-Memory Architectures},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {20},
number = {5-6},
pages = {595--623},
year = {2013},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-20-number-5-6-2013/mvlsc-20-5-6-p-595-623/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/IshiharaIHK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ei-iriacv/LukacKH13,
author = {Martin Lukac and
Michitaka Kameyama and
Kosuke Hiura},
editor = {Juha R{\"{o}}ning and
David P. Casasent},
title = {Natural image understanding using algorithm selection and high-level
feedback},
booktitle = {Intelligent Robots and Computer Vision {XXX:} Algorithms and Techniques,
Burlingame, California, USA, February 3-7, 2013},
series = {{SPIE} Proceedings},
volume = {8662},
pages = {86620D},
publisher = {{SPIE}},
year = {2013},
url = {https://doi.org/10.1117/12.2008593},
doi = {10.1117/12.2008593},
timestamp = {Fri, 04 Aug 2023 08:46:10 +0200},
biburl = {https://dblp.org/rec/conf/ei-iriacv/LukacKH13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/embc/WaidyasooriyaHK13,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Implementation of a custom hardware-accelerator for short-read mapping
using Burrows-Wheeler alignment},
booktitle = {35th Annual International Conference of the {IEEE} Engineering in
Medicine and Biology Society, {EMBC} 2013, Osaka, Japan, July 3-7,
2013},
pages = {651--654},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/EMBC.2013.6609584},
doi = {10.1109/EMBC.2013.6609584},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/embc/WaidyasooriyaHK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icawst/LukacK13,
author = {Martin Lukac and
Michitaka Kameyama},
title = {Bayesian Network for algorithm selection: Real-world hierarchy for
nodes reduction},
booktitle = {International Joint Conference on Awareness Science and Technology
{\&} Ubi-Media Computing, iCAST 2013 {\&} {UMEDIA} 2013, Aizuwakamatsu,
Japan, November 2-4, 2013},
pages = {69--75},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ICAwST.2013.6765411},
doi = {10.1109/ICAWST.2013.6765411},
timestamp = {Mon, 09 Aug 2021 14:54:04 +0200},
biburl = {https://dblp.org/rec/conf/icawst/LukacK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HawashLKP13,
author = {Maher Hawash and
Martin Lukac and
Michitaka Kameyama and
Marek A. Perkowski},
title = {Multiple-Valued Reversible Benchmarks and Extensible Quantum Specification
{(XQS)} Format},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {41--46},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.39},
doi = {10.1109/ISMVL.2013.39},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HawashLKP13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BaiK13,
author = {Xu Bai and
Michitaka Kameyama},
title = {Low-Power Multiple-Valued Source-Coupled Logic Circuits Using Dual-Supply
Voltages for a Reconfigurable {VLSI}},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {164--169},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.36},
doi = {10.1109/ISMVL.2013.36},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BaiK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BaiK13a,
author = {Xu Bai and
Michitaka Kameyama},
title = {An Area-Efficient Multiple-Valued Reconfigurable {VLSI} Architecture
Using an X-Net},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {272--277},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.13},
doi = {10.1109/ISMVL.2013.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BaiK13a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LukacKPK13,
author = {Martin Lukac and
Michitaka Kameyama and
Marek A. Perkowski and
Pawel Kerntopf},
title = {Analysis of Reversible and Quantum Finite State Machines Using Homing,
Synchronizing and Distinguishing Input Sequences},
booktitle = {43rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2013, Toyama, Japan, May 22-24, 2013},
pages = {322--327},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/ISMVL.2013.15},
doi = {10.1109/ISMVL.2013.15},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LukacKPK13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaOHK12,
author = {Hasitha Muthumala Waidyasooriya and
Yosuke Ohbayashi and
Masanori Hariyama and
Michitaka Kameyama},
title = {Memory-Access-Driven Context Partitioning for Window-Based Image Processing
on Heterogeneous Multicore Processors},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {354--363},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.354},
doi = {10.1587/TRANSINF.E95.D.354},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaOHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/XiaIHK12,
author = {Zhengfan Xia and
Shota Ishihara and
Masanori Hariyama and
Michitaka Kameyama},
title = {Design of High-Performance Asynchronous Pipeline Using Synchronizing
Logic Gates},
journal = {{IEICE} Trans. Electron.},
volume = {95-C},
number = {8},
pages = {1434--1443},
year = {2012},
url = {https://doi.org/10.1587/transele.E95.C.1434},
doi = {10.1587/TRANSELE.E95.C.1434},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/XiaIHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HiramatsuWHNUK12,
author = {Yoshitaka Hiramatsu and
Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Tohru Nojiri and
Kunio Uchiyama and
Michitaka Kameyama},
title = {Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core
Processor Based on {DTU} Data-Transfer with Data Re-Allocation},
journal = {{IEICE} Trans. Electron.},
volume = {95-C},
number = {12},
pages = {1872--1882},
year = {2012},
url = {https://doi.org/10.1587/transele.E95.C.1872},
doi = {10.1587/TRANSELE.E95.C.1872},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HiramatsuWHNUK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/SunK12,
author = {Bo Sun and
Michitaka Kameyama},
title = {Driver's Intention Estimation Based on Bayesian Networks for a Highly-Safe
Intelligent Vehicle},
journal = {J. Robotics Mechatronics},
volume = {24},
number = {1},
pages = {219--225},
year = {2012},
url = {https://doi.org/10.20965/jrm.2012.p0219},
doi = {10.20965/JRM.2012.P0219},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/SunK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/BaiOK12,
author = {Xu Bai and
Nobuaki Okada and
Michitaka Kameyama},
title = {A Digit-Serial Reconfigurable {VLSI} Based on Quaternary Inter-Cell
Data Transfer Scheme},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {20},
number = {1-2},
pages = {1--18},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-20-number-1-2-2013/mvlsc-20-1-2-p-1-18/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/BaiOK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/LukacKMP12,
author = {Martin Lukac and
Michitaka Kameyama and
D. Michael Miller and
Marek A. Perkowski},
title = {High Speed Genetic Algorithms in Quantum Logic Synthesis: Low Level
Parallelization vs. Representation?},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {20},
number = {1-2},
pages = {89--120},
year = {2012},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-20-number-1-2-2013/mvlsc-20-1-2-p-89-120/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/LukacKMP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/WaidyasooriyaTHK12,
author = {Hasitha Muthumala Waidyasooriya and
Yasuhiro Takei and
Masanori Hariyama and
Michitaka Kameyama},
title = {{FPGA} implementation of heterogeneous multicore platform with {SIMD/MIMD}
custom accelerators},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1339--1342},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271489},
doi = {10.1109/ISCAS.2012.6271489},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/WaidyasooriyaTHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/XiaIHK12,
author = {Zhengfan Xia and
Shota Ishihara and
Masanori Hariyama and
Michitaka Kameyama},
title = {Dual-rail/single-rail hybrid logic design for high-performance asynchronous
circuit},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {3017--3020},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271954},
doi = {10.1109/ISCAS.2012.6271954},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/XiaIHK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KisaraK12,
author = {Shogo Kisara and
Michitaka Kameyama},
editor = {D. Michael Miller and
Vincent C. Gaudet},
title = {Unified Current-Source Control for Low-Power Current-Mode-Logic Bit-Serial
Circuits},
booktitle = {42nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2012, Victoria, BC, Canada, May 14-16, 2012},
pages = {104--109},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISMVL.2012.55},
doi = {10.1109/ISMVL.2012.55},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KisaraK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/BaiK12,
author = {Xu Bai and
Michitaka Kameyama},
editor = {D. Michael Miller and
Vincent C. Gaudet},
title = {Current-Source-Sharing Differential-Pair Circuits for a Low-Power
Fine-Grain Reconfigurable {VLSI} Architecture},
booktitle = {42nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2012, Victoria, BC, Canada, May 14-16, 2012},
pages = {208--213},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/ISMVL.2012.13},
doi = {10.1109/ISMVL.2012.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/BaiK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/FujiokaK12,
author = {Yoshichika Fujioka and
Michitaka Kameyama},
title = {Configuration memory size reduction of a Dynamically Reconfigurable
Processor based on a register-transfer-level packet data transfer
scheme},
booktitle = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
Korea, November 4-7, 2012},
pages = {235--238},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISOCC.2012.6407083},
doi = {10.1109/ISOCC.2012.6407083},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/FujiokaK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaHK11,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Memory Allocation for Window-Based Image Processing on Multiple Memory
Modules with Simple Addressing Functions},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {94-A},
number = {1},
pages = {342--351},
year = {2011},
url = {https://doi.org/10.1587/transfun.E94.A.342},
doi = {10.1587/TRANSFUN.E94.A.342},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IshiharaTKHK11,
author = {Shota Ishihara and
Ryoto Tsuchiya and
Yoshiya Komatsu and
Masanori Hariyama and
Michitaka Kameyama},
title = {Implementation of a Low-Power {FPGA} Based on Synchronous/Asynchronous
Hybrid Architecture},
journal = {{IEICE} Trans. Electron.},
volume = {94-C},
number = {10},
pages = {1669--1679},
year = {2011},
url = {https://doi.org/10.1587/transele.E94.C.1669},
doi = {10.1587/TRANSELE.E94.C.1669},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IshiharaTKHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jip/WatanabeFK11,
author = {Kan Watanabe and
Masaru Fukushi and
Michitaka Kameyama},
title = {Adaptive Group-Based Job Scheduling for High Performance and Reliable
Volunteer Computing},
journal = {J. Inf. Process.},
volume = {19},
pages = {39--51},
year = {2011},
url = {https://doi.org/10.2197/ipsjjip.19.39},
doi = {10.2197/IPSJJIP.19.39},
timestamp = {Tue, 16 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jip/WatanabeFK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcsv/WaidyasooriyaOHK11,
author = {Hasitha Muthumala Waidyasooriya and
Yosuke Ohbayashi and
Masanori Hariyama and
Michitaka Kameyama},
title = {Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer
Bottlenecks in Heterogeneous Multicore Processors},
journal = {{IEEE} Trans. Circuits Syst. Video Technol.},
volume = {21},
number = {10},
pages = {1453--1466},
year = {2011},
url = {https://doi.org/10.1109/TCSVT.2011.2162277},
doi = {10.1109/TCSVT.2011.2162277},
timestamp = {Tue, 25 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcsv/WaidyasooriyaOHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IshiharaHK11,
author = {Shota Ishihara and
Masanori Hariyama and
Michitaka Kameyama},
title = {A Low-Power {FPGA} Based on Autonomous Fine-Grain Power Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {8},
pages = {1394--1406},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2050500},
doi = {10.1109/TVLSI.2010.2050500},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IshiharaHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KomatsuIHK11,
author = {Yoshiya Komatsu and
Shota Ishihara and
Masanori Hariyama and
Michitaka Kameyama},
title = {An implementation of an asychronous {FPGA} based on LEDR/four-phase-dual-rail
hybrid architecture},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {89--90},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722311},
doi = {10.1109/ASPDAC.2011.5722311},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KomatsuIHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icc/NejadJK11,
author = {Keyvan Kashkouli Nejad and
Xiaohong Jiang and
Michitaka Kameyama},
title = {High Performance Tag Singulation for Memory-Less {RFID} Systems},
booktitle = {Proceedings of {IEEE} International Conference on Communications,
{ICC} 2011, Kyoto, Japan, 5-9 June, 2011},
pages = {1--6},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/icc.2011.5962918},
doi = {10.1109/ICC.2011.5962918},
timestamp = {Thu, 19 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icc/NejadJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isda/NejadJK11,
author = {Keyvan Kashkouli Nejad and
Xiaohong Jiang and
Michitaka Kameyama},
editor = {Sebasti{\'{a}}n Ventura and
Ajith Abraham and
Krzysztof J. Cios and
Crist{\'{o}}bal Romero and
Francesco Marcelloni and
Jos{\'{e}} Manuel Ben{\'{\i}}tez and
Eva Lucrecia Gibaja Galindo},
title = {Non-blocking tag scanning for passive {RFID} localization},
booktitle = {11th International Conference on Intelligent Systems Design and Applications,
{ISDA} 2011, C{\'{o}}rdoba, Spain, November 22-24, 2011},
pages = {1140--1145},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISDA.2011.6121812},
doi = {10.1109/ISDA.2011.6121812},
timestamp = {Tue, 23 Aug 2022 09:19:48 +0200},
biburl = {https://dblp.org/rec/conf/isda/NejadJK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/LukacSKM11,
author = {Martin Lukac and
Ben Shuai and
Michitaka Kameyama and
D. Michael Miller},
editor = {Jaakko Astola and
Radomir S. Stankovic},
title = {Information-Preserving Logic Based on Logical Reversibility to Reduce
the Memory Data Transfer Bottleneck and Heat Dissipation},
booktitle = {41st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2011, Tuusula, Finland, May 23-25, 2011},
pages = {131--138},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ISMVL.2011.43},
doi = {10.1109/ISMVL.2011.43},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/LukacSKM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1107-3383,
author = {Maarti nLukac and
Marek A. Perkowski and
Michitaka Kameyama},
title = {Evolutionary Quantum Logic Synthesis of Boolean Reversible Logic Circuits
Embedded in Ternary Quantum Space using Heuristics},
journal = {CoRR},
volume = {abs/1107.3383},
year = {2011},
url = {http://arxiv.org/abs/1107.3383},
eprinttype = {arXiv},
eprint = {1107.3383},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1107-3383.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/NashatJK10,
author = {Dalia Nashat and
Xiaohong Jiang and
Michitaka Kameyama},
title = {Group Testing Based Detection of Web Service DDoS Attackers},
journal = {{IEICE} Trans. Commun.},
volume = {93-B},
number = {5},
pages = {1113--1121},
year = {2010},
url = {https://doi.org/10.1587/transcom.E93.B.1113},
doi = {10.1587/TRANSCOM.E93.B.1113},
timestamp = {Thu, 19 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/NashatJK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IshiharaKHK10,
author = {Shota Ishihara and
Yoshiya Komatsu and
Masanori Hariyama and
Michitaka Kameyama},
title = {An Asynchronous {FPGA} Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture},
journal = {{IEICE} Trans. Electron.},
volume = {93-C},
number = {8},
pages = {1338--1348},
year = {2010},
url = {https://doi.org/10.1587/transele.E93.C.1338},
doi = {10.1587/TRANSELE.E93.C.1338},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IshiharaKHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Kameyama10,
author = {Michitaka Kameyama},
title = {Foreword},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {8},
pages = {2025},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.2025},
doi = {10.1587/TRANSINF.E93.D.2025},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Kameyama10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OkadaK10,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Logic-In-Control-Architecture-Based Reconfigurable {VLSI} Using Multiple-Valued
Differential-Pair Circuits},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {8},
pages = {2126--2133},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.2126},
doi = {10.1587/TRANSINF.E93.D.2126},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OkadaK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IshiharaIHK10,
author = {Shota Ishihara and
Noriaki Idobata and
Masanori Hariyama and
Michitaka Kameyama},
title = {A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor
Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {93-D},
number = {8},
pages = {2134--2144},
year = {2010},
url = {https://doi.org/10.1587/transinf.E93.D.2134},
doi = {10.1587/TRANSINF.E93.D.2134},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IshiharaIHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaOHK10,
author = {Hasitha Muthumala Waidyasooriya and
Daisuke Okumura and
Masanori Hariyama and
Michitaka Kameyama},
title = {Task Allocation with Algorithm Transformation for Reducing Data-Transfer
Bottlenecks in Heterogeneous Multi-Core Processors: {A} Case Study
of {HOG} Descriptor Computation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {93-A},
number = {12},
pages = {2570--2580},
year = {2010},
url = {https://doi.org/10.1587/transfun.E93.A.2570},
doi = {10.1587/TRANSFUN.E93.A.2570},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaOHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cec/LukacPK10,
author = {Martin Lukac and
Marek A. Perkowski and
Michitaka Kameyama},
title = {Evolutionary quantum logic synthesis of Boolean reversible logic circuits
embedded in ternary quantum space using structural restrictions},
booktitle = {Proceedings of the {IEEE} Congress on Evolutionary Computation, {CEC}
2010, Barcelona, Spain, 18-23 July 2010},
pages = {1--8},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/CEC.2010.5585969},
doi = {10.1109/CEC.2010.5585969},
timestamp = {Thu, 16 Dec 2021 14:02:32 +0100},
biburl = {https://dblp.org/rec/conf/cec/LukacPK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/WaidyasooriyaHK10,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks and
David Andrews and
Ronald F. DeMara and
Herman Lam and
Jooheung Lee and
Christian Plessl and
Greg Stitt},
title = {Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor
with SIMD-Accelerator Cores},
booktitle = {Proceedings of the 2010 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2010, July 12-15,
2010, Las Vegas Nevada, {USA}},
pages = {179--186},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Wed, 14 Aug 2019 11:41:16 +0200},
biburl = {https://dblp.org/rec/conf/ersa/WaidyasooriyaHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/HariyamaTIK10,
author = {Masanori Hariyama and
Ryoto Tsuchiya and
Shota Ishihara and
Michitaka Kameyama},
editor = {Toomas P. Plaks and
David Andrews and
Ronald F. DeMara and
Herman Lam and
Jooheung Lee and
Christian Plessl and
Greg Stitt},
title = {An Field-Programmable {VLSI} Based on Synchronous/Asynchronous Hybrid
Architecture},
booktitle = {Proceedings of the 2010 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2010, July 12-15,
2010, Las Vegas Nevada, {USA}},
pages = {271--274},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Wed, 08 Dec 2010 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/HariyamaTIK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/WaidyasooriyaOHK10,
author = {Hasitha Muthumala Waidyasooriya and
Daisuke Okumura and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks and
David Andrews and
Ronald F. DeMara and
Herman Lam and
Jooheung Lee and
Christian Plessl and
Greg Stitt},
title = {Mapping for a Heterogeneous Multi-Core Media Processor Considering
the Data Transfer Time},
booktitle = {Proceedings of the 2010 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2010, July 12-15,
2010, Las Vegas Nevada, {USA}},
pages = {281--284},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Wed, 08 Dec 2010 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/WaidyasooriyaOHK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icai/LukacKP10,
author = {Martin Lukac and
Michitaka Kameyama and
Marek A. Perkowski},
editor = {Hamid R. Arabnia and
David de la Fuente and
Elena B. Kozerenko and
Jos{\'{e}} Angel Olivas and
Rui Chang and
Peter M. LaMonica and
Raymond A. Liuzzi and
Ashu M. G. Solo},
title = {Adaptive Selection of Intelligent Processing Modules and its Applications},
booktitle = {Proceedings of the 2010 International Conference on Artificial Intelligence,
{ICAI} 2010, July 12-15, 2010, Las Vegas Nevada, USA, 2 Volumes},
pages = {513--520},
publisher = {{CSREA} Press},
year = {2010},
timestamp = {Tue, 07 Dec 2010 11:23:59 +0100},
biburl = {https://dblp.org/rec/conf/icai/LukacKP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/IshikawaOK10,
author = {Akitaka Ishikawa and
Nobuaki Okada and
Michitaka Kameyama},
title = {Low-Power Multiple-Valued Reconfigurable {VLSI} Based on Superposition
of Bit-Serial Data and Current-Source Control Signals},
booktitle = {40th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2010, Barcelona, Spain, 26-28 May 2010},
pages = {179--184},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ISMVL.2010.41},
doi = {10.1109/ISMVL.2010.41},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/IshikawaOK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaHK09,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Implementation of a Partially Reconfigurable Multi-Context {FPGA}
Based on Asynchronous Architecture},
journal = {{IEICE} Trans. Electron.},
volume = {92-C},
number = {4},
pages = {539--549},
year = {2009},
url = {https://doi.org/10.1587/transele.E92.C.539},
doi = {10.1587/TRANSELE.E92.C.539},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KobayashiHK09,
author = {Yasuhiro Kobayashi and
Masanori Hariyama and
Michitaka Kameyama},
title = {Optimal Periodic Memory Allocation for Image Processing With Multiple
Windows},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {3},
pages = {403--416},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2004547},
doi = {10.1109/TVLSI.2008.2004547},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KobayashiHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/IshiharaHK09,
author = {Shota Ishihara and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Kazutoshi Wakabayashi},
title = {A low-power {FPGA} based on autonomous fine-grain power-gating},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {119--120},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796461},
doi = {10.1109/ASPDAC.2009.4796461},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/IshiharaHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/IshiharaKHK09,
author = {Shota Ishihara and
Yoshiya Komatsu and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {An Asynchronous Field-Programmable {VLSI} Using LEDR/4-Phase-Dual-Rail
Protocol Converters},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {145--150},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 10:35:19 +0100},
biburl = {https://dblp.org/rec/conf/ersa/IshiharaKHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/HariyamaTK09,
author = {Masanori Hariyama and
Keita Tanji and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {{FPGA} Implementation of a High-Speed Stereo Matching Processor Based
on Recursive Computation},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {263--266},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/HariyamaTK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/IshiharaIHK09,
author = {Shota Ishihara and
Noriaki Idobata and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {A Fine-Grain {SIMD} Architecture Based on Flexible Ferroelectric-Capacitor
Logic},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {271--274},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/IshiharaIHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/WaidyasooriyaHK09,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable
{ALU} Arrays},
booktitle = {Proceedings of the 2009 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2009, July 13-16,
2009, Las Vegas Nevada, {USA}},
pages = {291--294},
publisher = {{CSREA} Press},
year = {2009},
timestamp = {Tue, 03 Nov 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/WaidyasooriyaHK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/OkadaK09,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Multiple-Valued Reconfigurable {VLSI} Processor Based on Superposition
of Data and Control Signals},
booktitle = {{ISMVL} 2009, 39th International Symposium on Multiple-Valued Logic,
21-23 May 2009, Naha, Okinawaw, Japan},
pages = {54--59},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISMVL.2009.62},
doi = {10.1109/ISMVL.2009.62},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/OkadaK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MelisCK09,
author = {Wim J. C. Melis and
Shuhei Chizuwa and
Michitaka Kameyama},
title = {Evaluation of the Hierarchical Temporal Memory as Soft Computing Platform
and its {VLSI} Architecture},
booktitle = {{ISMVL} 2009, 39th International Symposium on Multiple-Valued Logic,
21-23 May 2009, Naha, Okinawaw, Japan},
pages = {233--238},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/ISMVL.2009.11},
doi = {10.1109/ISMVL.2009.11},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MelisCK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaYK08,
author = {Masanori Hariyama and
Naoto Yokoyama and
Michitaka Kameyama},
title = {Design of a Trinocular-Stereo-Vision {VLSI} Processor Based on Optimal
Scheduling},
journal = {{IEICE} Trans. Electron.},
volume = {91-C},
number = {4},
pages = {479--486},
year = {2008},
url = {https://doi.org/10.1093/ietele/e91-c.4.479},
doi = {10.1093/IETELE/E91-C.4.479},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaYK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaCHK08,
author = {Hasitha Muthumala Waidyasooriya and
Weisheng Chong and
Masanori Hariyama and
Michitaka Kameyama},
title = {Multi-Context {FPGA} Using Fine-Grained Interconnection Blocks and
Its {CAD} Environment},
journal = {{IEICE} Trans. Electron.},
volume = {91-C},
number = {4},
pages = {517--525},
year = {2008},
url = {https://doi.org/10.1093/ietele/e91-c.4.517},
doi = {10.1093/IETELE/E91-C.4.517},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaCHK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaIK08,
author = {Masanori Hariyama and
Shota Ishihara and
Michitaka Kameyama},
title = {Evaluation of a Field-Programmable {VLSI} Based on an Asynchronous
Bit-Serial Architecture},
journal = {{IEICE} Trans. Electron.},
volume = {91-C},
number = {9},
pages = {1419--1426},
year = {2008},
url = {https://doi.org/10.1093/ietele/e91-c.9.1419},
doi = {10.1093/IETELE/E91-C.9.1419},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaIK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/OkadaK08,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Fine-Grain Multiple-Valued Reconfigurable {VLSI} Using Series-Gating
Differential-Pair Circuits and Its Evaluation},
journal = {{IEICE} Trans. Electron.},
volume = {91-C},
number = {9},
pages = {1437--1443},
year = {2008},
url = {https://doi.org/10.1093/ietele/e91-c.9.1437},
doi = {10.1093/IETELE/E91-C.9.1437},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/OkadaK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KobayashiHK08,
author = {Yasuhiro Kobayashi and
Masanori Hariyama and
Michitaka Kameyama},
title = {Memory Allocation for Multi-Resolution Image Processing},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {91-D},
number = {10},
pages = {2386--2397},
year = {2008},
url = {https://doi.org/10.1093/ietisy/e91-d.10.2386},
doi = {10.1093/IETISY/E91-D.10.2386},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KobayashiHK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/WaidyasooriyaHK08,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
title = {Evaluation of Interconnect-Complexity-Aware Low-Power {VLSI} Design
Using Multiple Supply and Threshold Voltages},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {91-A},
number = {12},
pages = {3596--3606},
year = {2008},
url = {https://doi.org/10.1093/ietfec/e91-a.12.3596},
doi = {10.1093/IETFEC/E91-A.12.3596},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/WaidyasooriyaHK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/WaidyasooriyaHK08,
author = {Hasitha Muthumala Waidyasooriya and
Masanori Hariyama and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {Implementation of a Multi-Context {FPGA} Based on Flexible-Context-Partitioning},
booktitle = {Proceedings of the 2008 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2008, Las Vegas,
Nevada, USA, July 14-17, 2008},
pages = {201--207},
publisher = {{CSREA} Press},
year = {2008},
timestamp = {Thu, 12 Feb 2009 10:30:38 +0100},
biburl = {https://dblp.org/rec/conf/ersa/WaidyasooriyaHK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ersa/HariyamaIIK08,
author = {Masanori Hariyama and
Shota Ishihara and
Noriaki Idobata and
Michitaka Kameyama},
editor = {Toomas P. Plaks},
title = {Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary
Context Switching Signals},
booktitle = {Proceedings of the 2008 International Conference on Engineering of
Reconfigurable Systems {\&} Algorithms, {ERSA} 2008, Las Vegas,
Nevada, USA, July 14-17, 2008},
pages = {309--310},
publisher = {{CSREA} Press},
year = {2008},
timestamp = {Thu, 12 Feb 2009 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ersa/HariyamaIIK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/HariyamaYK08,
author = {Masanori Hariyama and
Kensaku Yamashita and
Michitaka Kameyama},
title = {{FPGA} implementation of a vehicle detection algorithm using three-dimensional
information},
booktitle = {22nd {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2008, Miami, Florida USA, April 14-18, 2008},
pages = {1--5},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/IPDPS.2008.4536535},
doi = {10.1109/IPDPS.2008.4536535},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/HariyamaYK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/OkadaK08,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Fine-Grain Multiple-Valued Reconfigurable {VLSI} Using Universal-Literal-Based
Cells},
booktitle = {38th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2008), 22-23 May 2008, Dallas, Texas, {USA}},
pages = {180--185},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISMVL.2008.46},
doi = {10.1109/ISMVL.2008.46},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/OkadaK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/Kameyama07,
author = {Michitaka Kameyama},
title = {Special Section on {VLSI} Technology toward Frontiers of New Market},
journal = {{IEICE} Trans. Electron.},
volume = {90-C},
number = {10},
pages = {1849},
year = {2007},
url = {https://doi.org/10.1093/ietele/e90-c.10.1849},
doi = {10.1093/IETELE/E90-C.10.1849},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/Kameyama07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/ItoK07,
author = {Tasuku Ito and
Michitaka Kameyama},
title = {Universal {VLSI} Based on a Redundant Multiple-Valued Sequential Logic
Operation},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {13},
number = {4-6},
pages = {553--568},
year = {2007},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-13-number-4-6-2007/mvlsc-13-4-6-p-553-568/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/ItoK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/OkadaK07,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Low-Power Multiple-Valued Reconfigurable {VLSI} Using Series-Gating
Differential-Pair Circuits},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {13},
number = {4-6},
pages = {619--632},
year = {2007},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-13-number-4-6-2007/mvlsc-13-4-6-p-619-632/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/OkadaK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/OkadaK07,
author = {Nobuaki Okada and
Michitaka Kameyama},
title = {Low-Power Multiple-Valued Reconfigurable {VLSI} Using Series-Gating
Differential-Pair Circuits},
booktitle = {37th International Symposium on Multiple-Valued Logic, {ISMVL} 2007,
13-16 May 2007, Oslo, Norway},
pages = {25},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISMVL.2007.32},
doi = {10.1109/ISMVL.2007.32},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/OkadaK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ItoK07,
author = {Tasuku Ito and
Michitaka Kameyama},
title = {Universal {VLSI} Based on a Redundant Multiple-Valued Sequential Logic
Operation},
booktitle = {37th International Symposium on Multiple-Valued Logic, {ISMVL} 2007,
13-16 May 2007, Oslo, Norway},
pages = {39},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISMVL.2007.58},
doi = {10.1109/ISMVL.2007.58},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ItoK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaYK06,
author = {Masanori Hariyama and
Shigeo Yamadera and
Michitaka Kameyama},
title = {Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment
and Interconnection Simplification},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {11},
pages = {1551--1558},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.11.1551},
doi = {10.1093/IETELE/E89-C.11.1551},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaYK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaOK06,
author = {Masanori Hariyama and
Sho Ogata and
Michitaka Kameyama},
title = {A Multi-Context {FPGA} Using Floating-Gate-MOS Functional Pass-Gates},
journal = {{IEICE} Trans. Electron.},
volume = {89-C},
number = {11},
pages = {1655--1661},
year = {2006},
url = {https://doi.org/10.1093/ietele/e89-c.11.1655},
doi = {10.1093/IETELE/E89-C.11.1655},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaOK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/MuthumalaHK06,
author = {W. H. Muthumala and
Masanori Hariyama and
Michitaka Kameyama},
title = {GA-Based Assignment of Supply and Threshold Voltages and Interconnection
Simplification for Low Power {VLSI} Design},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {1264--1267},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342393},
doi = {10.1109/APCCAS.2006.342393},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/apccas/MuthumalaHK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HariyamaK06,
author = {Masanori Hariyama and
Michitaka Kameyama},
title = {A Multi-Context {FPGA} Using a Floating-Gate-MOS Functional Pass-Gate
and Its {CAD} Environment},
booktitle = {{IEEE} Asia Pacific Conference on Circuits and Systems 2006, {APCCAS}
2006, Singapore, 4-7 December 2006},
pages = {1803--1806},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/APCCAS.2006.342169},
doi = {10.1109/APCCAS.2006.342169},
timestamp = {Wed, 17 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/HariyamaK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/NakataniHK06,
author = {Yoshihiro Nakatani and
Masanori Hariyama and
Michitaka Kameyama},
title = {Architecture of a multi-context {FPGA} using a hybrid multiple-valued/binary
context switching signal},
booktitle = {20th International Parallel and Distributed Processing Symposium {(IPDPS}
2006), Proceedings, 25-29 April 2006, Rhodes Island, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/IPDPS.2006.1639467},
doi = {10.1109/IPDPS.2006.1639467},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/NakataniHK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MunirulHK06,
author = {Haque Mohammad Munirul and
Tomoaki Hasegawa and
Michitaka Kameyama},
title = {Evaluation of Multiple-Valued Packet Multiplexing Scheme for Network-on-Chip
Architecture},
booktitle = {36th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2006), 17-20 May 2006, Singapore},
pages = {6},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISMVL.2006.21},
doi = {10.1109/ISMVL.2006.21},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MunirulHK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MunirulK06,
author = {Haque Mohammad Munirul and
Michitaka Kameyama},
title = {Fine-Grain Cell Design for Multiple-Valued Reconfigurable {VLSI} Using
a Single Differential-Pair Circuit},
booktitle = {36th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2006), 17-20 May 2006, Singapore},
pages = {13},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISMVL.2006.22},
doi = {10.1109/ISMVL.2006.22},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MunirulK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NakataniHK06,
author = {Yoshihiro Nakatani and
Masanori Hariyama and
Michitaka Kameyama},
title = {Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary
Context Switching Signals},
booktitle = {36th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2006), 17-20 May 2006, Singapore},
pages = {17},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISMVL.2006.40},
doi = {10.1109/ISMVL.2006.40},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/NakataniHK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HariyamaKK06,
author = {Masanori Hariyama and
Michitaka Kameyama and
Yasuhiro Kobayashi},
title = {Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors},
booktitle = {2006 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2006), 2-3 March 2006, Karlsruhe, Germany},
pages = {193--198},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISVLSI.2006.69},
doi = {10.1109/ISVLSI.2006.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HariyamaKK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaSK05,
author = {Masanori Hariyama and
Haruka Sasaki and
Michitaka Kameyama},
title = {Architecture of a Stereo Matching {VLSI} Processor Based on Hierarchically
Parallel Memory Access},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {88-D},
number = {7},
pages = {1486--1491},
year = {2005},
url = {https://doi.org/10.1093/ietisy/e88-d.7.1486},
doi = {10.1093/IETISY/E88-D.7.1486},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaSK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ChongHK05,
author = {Weisheng Chong and
Masanori Hariyama and
Michitaka Kameyama},
title = {Low-Power Field-Programmable {VLSI} Using Multiple Supply Voltages},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3298--3305},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3298},
doi = {10.1093/IETFEC/E88-A.12.3298},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ChongHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/HariyamaKSK05,
author = {Masanori Hariyama and
Yasuhiro Kobayashi and
Haruka Sasaki and
Michitaka Kameyama},
title = {{FPGA} Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel
Architecture},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {88-A},
number = {12},
pages = {3516--3522},
year = {2005},
url = {https://doi.org/10.1093/ietfec/e88-a.12.3516},
doi = {10.1093/IETFEC/E88-A.12.3516},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/HariyamaKSK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/KameyamaHA05,
author = {Michitaka Kameyama and
Takahiro Hanyu and
Takafumi Aoki},
title = {Multiple-Valued Logic as a New Computing Paradigm - {A} Brief Survey
of Higuchi's Researchon Multiple-Valued Logic},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {11},
number = {5-6},
pages = {407--436},
year = {2005},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/KameyamaHA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/MochizukiHK05,
author = {Akira Mochizuki and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Design of a Low-Power Multiple-Valued Integrated Circuit Based on
Dynamic Source-Coupled Logic},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {11},
number = {5-6},
pages = {481--497},
year = {2005},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-11-number-5-6-2005/mvlsc-11-5-6-p-481-497/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/MochizukiHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/HanyuKK05,
author = {Takahiro Hanyu and
Shunichi Kaeriyama and
Michitaka Kameyama},
title = {Logic-in-Memory {VLSI} circuit for Fully Parallel Nearest Pattern
Matching Based on Floating-Gate-MOS Pass-Transistor Logic},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {11},
number = {5-6},
pages = {619--632},
year = {2005},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-11-number-5-6-2005/mvlsc-11-5-6-p-619-632/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/HanyuKK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/HariyamaAK05,
author = {Masanori Hariyama and
Tetsuya Aoyama and
Michitaka Kameyama},
title = {Genetic Approach to Minimizing Energy Consumption of {VLSI} Processors
Using Multiple Supply Voltages},
journal = {{IEEE} Trans. Computers},
volume = {54},
number = {6},
pages = {642--650},
year = {2005},
url = {https://doi.org/10.1109/TC.2005.100},
doi = {10.1109/TC.2005.100},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/HariyamaAK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/ChongOHK05,
author = {Weisheng Chong and
Sho Ogata and
Masanori Hariyama and
Michitaka Kameyama},
title = {Architecture of a Multi-Context {FPGA} Using Reconfigurable Context
Memory},
booktitle = {19th International Parallel and Distributed Processing Symposium {(IPDPS}
2005), {CD-ROM} / Abstracts Proceedings, 4-8 April 2005, Denver, CO,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/IPDPS.2005.112},
doi = {10.1109/IPDPS.2005.112},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/ChongOHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HommaKFT05,
author = {Yuya Homma and
Michitaka Kameyama and
Yoshichika Fujioka and
Nobuhiro Tomabechi},
title = {{VLSI} architecture based on packet data transfer scheme and its application},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {1786--1789},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1464955},
doi = {10.1109/ISCAS.2005.1464955},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HommaKFT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HasegawaHK05,
author = {Tomoaki Hasegawa and
Yuya Homma and
Michitaka Kameyama},
title = {Multiple-Valued {VLSI} Architecture for Intra-Chip Packet Data Transfer},
booktitle = {35th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2005), 18-21 May 2005, Calgary, Canada},
pages = {114--119},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISMVL.2005.31},
doi = {10.1109/ISMVL.2005.31},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HasegawaHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MunirulHK05,
author = {Haque Mohammad Munirul and
Tomoaki Hasegawa and
Michitaka Kameyama},
title = {Implementation and Evaluation of a Fine-Grain Multiple-Valued Field
Programmable {VLSI} Based on Source-Coupled Logic},
booktitle = {35th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2005), 18-21 May 2005, Calgary, Canada},
pages = {120--125},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISMVL.2005.20},
doi = {10.1109/ISMVL.2005.20},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MunirulHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HariyamaCOK05,
author = {Masanori Hariyama and
Weisheng Chong and
Sho Ogata and
Michitaka Kameyama},
title = {Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate
for Multi-Context FPGAs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {46--50},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.52},
doi = {10.1109/ISVLSI.2005.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HariyamaCOK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/KimuraHKFNT04,
author = {Hiromitsu Kimura and
Takahiro Hanyu and
Michitaka Kameyama and
Yoshikazu Fujimori and
Takashi Nakamura and
Hidemi Takasu},
title = {Complementary ferroelectric-capacitor logic for low-power logic-in-memory
{VLSI}},
journal = {{IEEE} J. Solid State Circuits},
volume = {39},
number = {6},
pages = {919--926},
year = {2004},
url = {https://doi.org/10.1109/JSSC.2004.827802},
doi = {10.1109/JSSC.2004.827802},
timestamp = {Fri, 22 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/KimuraHKFNT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MunirulK04,
author = {Haque Mohammad Munirul and
Michitaka Kameyama},
title = {Ultra-Fine-Grain Field-Programmable {VLSI} Using Multiple-Valued Source-Coupled
Logic},
booktitle = {34th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2004), 19-22 May 2004, Toronto, Canada},
pages = {26--30},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISMVL.2004.1319915},
doi = {10.1109/ISMVL.2004.1319915},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MunirulK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/MunirulK04a,
author = {Haque Mohammad Munirul and
Michitaka Kameyama},
title = {Multiple-Valued Source-Coupled Logic {VLSI} Based on Adaptive Threshold
Control and Its Applications},
booktitle = {34th {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2004), 19-22 May 2004, Toronto, Canada},
pages = {328--333},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISMVL.2004.1319963},
doi = {10.1109/ISMVL.2004.1319963},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/MunirulK04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ChongHK04,
author = {Weisheng Chong and
Masanori Hariyama and
Michitaka Kameyama},
title = {Low-Power Field-Programmable {VLSI} Processor Using Dynamic Circuits},
booktitle = {2004 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2004), Emerging Trends in {VLSI} Systems Design, 19-20 February 2004,
Lafayette, LA, {USA}},
pages = {243--248},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISVLSI.2004.1339543},
doi = {10.1109/ISVLSI.2004.1339543},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ChongHK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/OhsawaSHK04,
author = {Naotaka Ohsawa and
Osamu Sakamoto and
Masanori Hariyama and
Michitaka Kameyama},
title = {Program-Counter-Less Bit-Serial Field-Programmable {VLSI} Processor
with Mesh-Connected Cellular Array Structure},
booktitle = {2004 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2004), Emerging Trends in {VLSI} Systems Design, 19-20 February 2004,
Lafayette, LA, {USA}},
pages = {258--259},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISVLSI.2004.1339547},
doi = {10.1109/ISVLSI.2004.1339547},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/OhsawaSHK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/IkeHK03,
author = {Tsukasa Ike and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Optimal Design of a Dual-Rail Multiple-Valued Current-Mode Integrated
Circuit Based on Voltage Swing Minimization},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {9},
number = {1},
pages = {5--21},
year = {2003},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-9-number-1-2003/mvlsc-9-1-p-5-21/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/IkeHK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mvl/KimuraHK03,
author = {Hiromitsu Kimura and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Multiple-Valued Logic-in-Memory {VLSI} Using MFSFETs and its Applications},
journal = {J. Multiple Valued Log. Soft Comput.},
volume = {9},
number = {1},
pages = {23--42},
year = {2003},
url = {http://www.oldcitypublishing.com/journals/mvlsc-home/mvlsc-issue-contents/mvlsc-volume-9-number-1-2003/mvlsc-9-1-p-23-42/},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mvl/KimuraHK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuTK03,
author = {Takahiro Hanyu and
Tomohiro Takahashi and
Michitaka Kameyama},
title = {Bidirectional Data Transfer Based Asynchronous {VLSI} System Using
Multiple-Valued Current Mode Logic},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {99--104},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201391},
doi = {10.1109/ISMVL.2003.1201391},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuTK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuMK03,
author = {Takahiro Hanyu and
Akira Mochizuki and
Michitaka Kameyama},
title = {Multiple-Valued Dynamic Source-Coupled Logic},
booktitle = {33rd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2003), 16-19 May 2003, Tokyo, Japan},
pages = {207--212},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ISMVL.2003.1201407},
doi = {10.1109/ISMVL.2003.1201407},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuMK03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KimuraHK02,
author = {Hiromitsu Kimura and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Multiple-Valued Logic-in-Memory {VLSI} Based on Ferroelectric Capacitor
Storage and Charge Addition},
booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2002), May 15-18, 2002, Boston, Massachusetts, {USA}},
pages = {161--167},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISMVL.2002.1011085},
doi = {10.1109/ISMVL.2002.1011085},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KimuraHK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/IkeHK02,
author = {Tsukasa Ike and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Fully Source-Coupled Logic Based Multiple-Valued {VLSI}},
booktitle = {32nd {IEEE} International Symposium on Multiple-Valued Logic {(ISMVL}
2002), May 15-18, 2002, Boston, Massachusetts, {USA}},
pages = {270--275},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISMVL.2002.1011098},
doi = {10.1109/ISMVL.2002.1011098},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/IkeHK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/OhsawaHK02,
author = {Naotaka Ohsawa and
Masanori Hariyama and
Michitaka Kameyama},
title = {High-Performance Field Programmable {VLSI} Processor Based on a Direct
Allocation of a Control/Data Flow Graph},
booktitle = {2002 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2002), 25-26 April 2002, Pittsburgh, PA, {USA}},
pages = {95--100},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/ISVLSI.2002.1016881},
doi = {10.1109/ISVLSI.2002.1016881},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/OhsawaHK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/HariyamaTK01,
author = {Masanori Hariyama and
Toshiki Takeuchi and
Michitaka Kameyama},
title = {{VLSI} Processor for Reliable Stereo Matching Based on Adaptive Window-Size
Selection},
booktitle = {Proceedings of the 2001 {IEEE} International Conference on Robotics
and Automation, {ICRA} 2001, May 21-26, 2001, Seoul, Korea},
pages = {1168--1173},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ROBOT.2001.932769},
doi = {10.1109/ROBOT.2001.932769},
timestamp = {Mon, 22 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icra/HariyamaTK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/IkeHK01,
author = {Tsukasa Ike and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Dual-Rail Multiple-Valued Current-Mode {VLSI} with Biasing Current
Sources},
booktitle = {31st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2001, Warsaw, Poland, May 22-24, 2001, Proceedings},
pages = {21--26},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISMVL.2001.924550},
doi = {10.1109/ISMVL.2001.924550},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/IkeHK01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuKSZ01,
author = {Takahiro Hanyu and
Michitaka Kameyama and
Katsuhiko Shimabukuro and
Chotei Zukeran},
title = {Multiple-Valued Mask-Programmable Logic Array Using One-Transistor
Universal-Literal Circuits},
booktitle = {31st {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2001, Warsaw, Poland, May 22-24, 2001, Proceedings},
pages = {167--172},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ISMVL.2001.924568},
doi = {10.1109/ISMVL.2001.924568},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuKSZ01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ar/HariyamaLK00,
author = {Masanori Hariyama and
Seunghwan Lee and
Michitaka Kameyama},
title = {Architecture of a high-performance stereo vision {VLSI} processor},
journal = {Adv. Robotics},
volume = {14},
number = {5},
pages = {329--332},
year = {2000},
url = {https://doi.org/10.1163/156855300741726},
doi = {10.1163/156855300741726},
timestamp = {Sat, 25 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ar/HariyamaLK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama00,
author = {Michitaka Kameyama},
title = {Editorial: Intelligent Integrated Systems for Human-Oriented Information
Society},
journal = {J. Robotics Mechatronics},
volume = {12},
number = {5},
pages = {501},
year = {2000},
url = {https://doi.org/10.20965/jrm.2000.p0501},
doi = {10.20965/JRM.2000.P0501},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/HariyamaK00,
author = {Masanori Hariyama and
Michitaka Kameyama},
title = {Stereo Vision {VLSI} Processor Based on Pixel-Serial and Window-Parallel
Architecture},
journal = {J. Robotics Mechatronics},
volume = {12},
number = {5},
pages = {521--526},
year = {2000},
url = {https://doi.org/10.20965/jrm.2000.p0521},
doi = {10.20965/JRM.2000.P0521},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/HariyamaK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/HariyamaK00a,
author = {Masanori Hariyama and
Michitaka Kameyama},
title = {Path Planning Based on Distance Transformation and Its {VLSI} Implementation},
journal = {J. Robotics Mechatronics},
volume = {12},
number = {5},
pages = {527--533},
year = {2000},
url = {https://doi.org/10.20965/jrm.2000.p0527},
doi = {10.20965/JRM.2000.P0527},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/HariyamaK00a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/KazamaHK00,
author = {Hideki Kazama and
Masanori Hariyama and
Michitaka Kameyama},
title = {Design of a {VLSI} Processor Based on an Immediate Output Generation
Scheduling for Ball-Trajectory Prediction},
journal = {J. Robotics Mechatronics},
volume = {12},
number = {5},
pages = {534--540},
year = {2000},
url = {https://doi.org/10.20965/jrm.2000.p0534},
doi = {10.20965/JRM.2000.P0534},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/KazamaHK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuIK00,
author = {Takahiro Hanyu and
Tsukasa Ike and
Michitaka Kameyama},
title = {Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using
Multiple Input-Signal Levels},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {382--390},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848647},
doi = {10.1109/ISMVL.2000.848647},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuIK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuKK00,
author = {Takahiro Hanyu and
Hiromitsu Kimura and
Michitaka Kameyama},
title = {DRAM-Cell-Based Multiple-Valued Logic-in-Memory {VLSI} with Charge
Addition and Charge Storage},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {423--429},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848652},
doi = {10.1109/ISMVL.2000.848652},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuKK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KaeriyamaHK00,
author = {Shunichi Kaeriyama and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Arithmetic-Oriented Multiple-Valued Logic-in-Memory {VLSI} Based on
Current-Mode Logic},
booktitle = {30th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
2000, Portland, Oregon, USA, May 23-25, 2000, Proceedings},
pages = {438--446},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ISMVL.2000.848655},
doi = {10.1109/ISMVL.2000.848655},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KaeriyamaHK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/prdc/HanyuIK00,
author = {Takahiro Hanyu and
Tsukasa Ike and
Michitaka Kameyama},
title = {Integration of asynchronous and self-checking multiple-valued current-mode
circuits based on dual-rail differential logic},
booktitle = {2000 Pacific Rim International Symposium on Dependable Computing {(PRDC}
2000), 18-20 December 2000, Los Angeles, CA, {USA}},
pages = {27--36},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/PRDC.2000.897281},
doi = {10.1109/PRDC.2000.897281},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/prdc/HanyuIK00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/FujiokaK99,
author = {Yoshichika Fujioka and
Michitaka Kameyama},
title = {Design of a reconfigurable {VLSI} processor for robot control based
on bit-serial architecture},
journal = {Syst. Comput. Jpn.},
volume = {30},
number = {12},
pages = {43--51},
year = {1999},
url = {https://doi.org/10.1002/(SICI)1520-684X(19991115)30:12\&\#60;43::AID-SCJ5\&\#62;3.0.CO;2-Y},
doi = {10.1002/(SICI)1520-684X(19991115)30:12\&\#60;43::AID-SCJ5\&\#62;3.0.CO;2-Y},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/FujiokaK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuKK99,
author = {Takahiro Hanyu and
Hiromitsu Kimura and
Michitaka Kameyama},
title = {Multiple-Valued Content-Addressable Memory Using Metal-Ferroelectric-Semiconductor
FETs},
booktitle = {29th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings},
pages = {30--35},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ISMVL.1999.779691},
doi = {10.1109/ISMVL.1999.779691},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuKK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuIK99,
author = {Takahiro Hanyu and
Tsukasa Ike and
Michitaka Kameyama},
title = {Self-Checking Multiple-Valued Circuit Based on Dual-Rail Current-Mode
Differential Logic},
booktitle = {29th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings},
pages = {275--279},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/ISMVL.1999.779728},
doi = {10.1109/ISMVL.1999.779728},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuIK99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/SaitoHK98,
author = {Takahiro Saito and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Optimal design of a current-mode deep-submicron multiple-valued integrated
circuit and application},
journal = {Syst. Comput. Jpn.},
volume = {29},
number = {11},
pages = {40--47},
year = {1998},
url = {https://doi.org/10.1002/(SICI)1520-684X(199810)29:11\&\#60;40::AID-SCJ5\&\#62;3.0.CO;2-S},
doi = {10.1002/(SICI)1520-684X(199810)29:11\&\#60;40::AID-SCJ5\&\#62;3.0.CO;2-S},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/SaitoHK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/HanyuTK98,
author = {Takahiro Hanyu and
Kaname Teranishi and
Michitaka Kameyama},
title = {Design and evaluation of a digit-parallel multiple-valued content-addressable
memory},
journal = {Syst. Comput. Jpn.},
volume = {29},
number = {11},
pages = {48--54},
year = {1998},
url = {https://doi.org/10.1002/(SICI)1520-684X(199810)29:11\&\#60;48::AID-SCJ6\&\#62;3.0.CO;2-1},
doi = {10.1002/(SICI)1520-684X(199810)29:11\&\#60;48::AID-SCJ6\&\#62;3.0.CO;2-1},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/HanyuTK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/HariyamaK98,
author = {Masanori Hariyama and
Michitaka Kameyama},
title = {Design of a Collision Detection {VLSI} Processor Based on Minimization
of Area-Time Products},
booktitle = {Proceedings of the {IEEE} International Conference on Robotics and
Automation, ICRA-98, Leuven, Belgium, May 16-20, 1998},
pages = {3691--3696},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ROBOT.1998.681407},
doi = {10.1109/ROBOT.1998.681407},
timestamp = {Mon, 22 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icra/HariyamaK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuSK98,
author = {Takahiro Hanyu and
Takahiro Saito and
Michitaka Kameyama},
title = {Asynchronous Multiple-Valued {VLSI} System Based on Dual-Rail Current-Mode
Differential Logic},
booktitle = {28th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1998, Fukuoka, Japan, May 27-29, 1998, Proceedings},
pages = {134--139},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISMVL.1998.679323},
doi = {10.1109/ISMVL.1998.679323},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuSK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuTK98,
author = {Takahiro Hanyu and
Kaname Teranishi and
Michitaka Kameyama},
title = {Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to
Logic-in-Memory {VLSI}},
booktitle = {28th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1998, Fukuoka, Japan, May 27-29, 1998, Proceedings},
pages = {270--275},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISMVL.1998.679469},
doi = {10.1109/ISMVL.1998.679469},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuTK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/HariyamaAK97,
author = {Masanori Hariyama and
Yuichi Araumi and
Michitaka Kameyama},
title = {A robot vision {VLSI} processor for the rectangular solid representation
of three-dimensional objects},
journal = {Syst. Comput. Jpn.},
volume = {28},
number = {2},
pages = {54--61},
year = {1997},
url = {https://doi.org/10.1002/(SICI)1520-684X(199702)28:2\&\#60;54::AID-SCJ6\&\#62;3.0.CO;2-Q},
doi = {10.1002/(SICI)1520-684X(199702)28:2\&\#60;54::AID-SCJ6\&\#62;3.0.CO;2-Q},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/HariyamaAK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tie/KobayashiK097,
author = {Koji Kobayashi and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Communication network protocol for real-time distributed control and
its {LSI} implementation},
journal = {{IEEE} Trans. Ind. Electron.},
volume = {44},
number = {3},
pages = {418--426},
year = {1997},
url = {https://doi.org/10.1109/41.585841},
doi = {10.1109/41.585841},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tie/KobayashiK097.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HanyuKK97,
author = {Takahiro Hanyu and
Satoshi Kazama and
Michitaka Kameyama},
title = {Low-power multiple-valued current-mode integrated circuit with current-source
control and its application},
booktitle = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
1997},
pages = {413--418},
publisher = {{IEEE}},
year = {1997},
url = {https://doi.org/10.1109/ASPDAC.1997.600277},
doi = {10.1109/ASPDAC.1997.600277},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HanyuKK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuAK97,
author = {Takahiro Hanyu and
Manabu Arakaki and
Michitaka Kameyama},
title = {One-Transistor-Cell 4-Valued Universal-Literal {CAM} for Cellular
Logic Image Processing},
booktitle = {27th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings},
pages = {175--182},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/ISMVL.1997.601393},
doi = {10.1109/ISMVL.1997.601393},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuAK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama96,
author = {Michitaka Kameyama},
title = {Editorial: Integration of Intelligence for Robotics in {VLSI} Chips},
journal = {J. Robotics Mechatronics},
volume = {8},
number = {6},
pages = {491},
year = {1996},
url = {https://doi.org/10.20965/jrm.1996.p0491},
doi = {10.20965/JRM.1996.P0491},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama96a,
author = {Michitaka Kameyama},
title = {Highly-Safe Intelligent Integrated Systems},
journal = {J. Robotics Mechatronics},
volume = {8},
number = {6},
pages = {492--495},
year = {1996},
url = {https://doi.org/10.20965/jrm.1996.p0492},
doi = {10.20965/JRM.1996.P0492},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama96a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/KameyamaF96,
author = {Michitaka Kameyama and
Yoshichika Fujioka},
title = {{VLSI} Processor System for Robotics},
journal = {J. Robotics Mechatronics},
volume = {8},
number = {6},
pages = {496--499},
year = {1996},
url = {https://doi.org/10.20965/jrm.1996.p0496},
doi = {10.20965/JRM.1996.P0496},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/KameyamaF96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/HariyamaAK96,
author = {Masanori Hariyama and
Yuichi Araumi and
Michitaka Kameyama},
title = {Robot Vision {VLSI} Processor for the Rectangular Solid Representation
of 3-Dimensional Objects},
journal = {J. Robotics Mechatronics},
volume = {8},
number = {6},
pages = {501--507},
year = {1996},
url = {https://doi.org/10.20965/jrm.1996.p0501},
doi = {10.20965/JRM.1996.P0501},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/HariyamaAK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/KameyamaS96,
author = {Michitaka Kameyama and
Masayuki Sasaki},
title = {Optimal Design of a {VLSI} Processor with Spatially and Temporally
Parallel Structure},
journal = {J. Robotics Mechatronics},
volume = {8},
number = {6},
pages = {516--523},
year = {1996},
url = {https://doi.org/10.20965/jrm.1996.p0516},
doi = {10.20965/JRM.1996.P0516},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/KameyamaS96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HanyuKK96,
author = {Takahiro Hanyu and
N. Kanagawa and
Michitaka Kameyama},
title = {Design of a one-transistor-cell multiple-valued {CAM}},
journal = {{IEEE} J. Solid State Circuits},
volume = {31},
number = {11},
pages = {1669--1674},
year = {1996},
url = {https://doi.org/10.1109/JSSC.1996.542311},
doi = {10.1109/JSSC.1996.542311},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HanyuKK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HanyuKK96a,
author = {Takahiro Hanyu and
Naoki Kanagawa and
Michitaka Kameyama},
title = {Design of a one-transistor-cell multiple-valued {CAM}},
journal = {{IEEE} J. Solid State Circuits},
volume = {31},
number = {11},
pages = {1669--1674},
year = {1996},
url = {https://doi.org/10.1109/JSSC.1996.671805},
doi = {10.1109/JSSC.1996.671805},
timestamp = {Mon, 18 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HanyuKK96a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KawahitoINKH96,
author = {Shoji Kawahito and
Makoto Ishida and
Tasuro Nakamura and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Author's Reply},
journal = {{IEEE} Trans. Computers},
volume = {45},
number = {5},
pages = {639},
year = {1996},
url = {https://doi.org/10.1109/TC.1996.509919},
doi = {10.1109/TC.1996.509919},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KawahitoINKH96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NakajimaK96,
author = {Masami Nakajima and
Michitaka Kameyama},
title = {Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level
Redundancy},
booktitle = {26th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings},
pages = {104--109},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ISMVL.1996.508344},
doi = {10.1109/ISMVL.1996.508344},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/NakajimaK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuAK96,
author = {Takahiro Hanyu and
Manabu Arakaki and
Michitaka Kameyama},
title = {Quaternary Universal-Literal {CAM} for Cellular Logic Image Processing},
booktitle = {26th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1996, Santiago de Compostela, Spain, May 29-31, 1996, Proceedings},
pages = {224--229},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/ISMVL.1996.508362},
doi = {10.1109/ISMVL.1996.508362},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuAK96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/DengHK95,
author = {Xiaowei Deng and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Quantum-Device-Oriented Multiple-Valued Logic System Based on a Super
Pass Gate},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {78-D},
number = {8},
pages = {951--958},
year = {1995},
url = {http://search.ieice.org/bin/summary.php?id=e78-d\_8\_951},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/DengHK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama95,
author = {Michitaka Kameyama},
title = {Digital Control Parallel {VLSI} Processor},
journal = {J. Robotics Mechatronics},
volume = {7},
number = {5},
pages = {419},
year = {1995},
url = {https://doi.org/10.20965/jrm.1995.p0419},
doi = {10.20965/JRM.1995.P0419},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/HanyuK95,
author = {Takahiro Hanyu and
Michitaka Kameyama},
title = {A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued
{MOS} current-mode circuits with dual-rail source-coupled logic},
journal = {{IEEE} J. Solid State Circuits},
volume = {30},
number = {11},
pages = {1239--1245},
year = {1995},
url = {https://doi.org/10.1109/4.475711},
doi = {10.1109/4.475711},
timestamp = {Wed, 03 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/HanyuK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/RyuK95,
author = {M. Ryu and
Michitaka Kameyama},
title = {Design of a Highly Parallel Multiple-Valued Linear Digital System
for k-Ary Operations Based on Extended Representation Matrices},
booktitle = {25th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings},
pages = {20--27},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ISMVL.1995.513505},
doi = {10.1109/ISMVL.1995.513505},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/RyuK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuMK95,
author = {Takahiro Hanyu and
Akira Mochizuki and
Michitaka Kameyama},
title = {Multiple-Valued Arithmetic Integrated Circuits Based on 1.5V-Supply
Dual-Rail Source-Coupled Logic},
booktitle = {25th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings},
pages = {64--71},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ISMVL.1995.513511},
doi = {10.1109/ISMVL.1995.513511},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuMK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/DengHK95,
author = {Xiaowei Deng and
Takahiro Hanyu and
Michitaka Kameyama},
title = {Quantum Device Model-Based Super Pass Gate for Multiple-Valued Digital
Systems},
booktitle = {25th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1995, Bloomington, Indiana, USA, May 23-25, 1995, Proceedings},
pages = {92--97},
publisher = {{IEEE} Computer Society},
year = {1995},
url = {https://doi.org/10.1109/ISMVL.1995.513515},
doi = {10.1109/ISMVL.1995.513515},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/DengHK95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama94,
author = {Michitaka Kameyama},
title = {Editorial: Intelligent Integrated Systems for Robotics},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {119},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0119},
doi = {10.20965/JRM.1994.P0119},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama94a,
author = {Michitaka Kameyama},
title = {Next-Generation Intelligent Integrated Systems Based on Multiple-Valued
Digital Processing},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {120--123},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0120},
doi = {10.20965/JRM.1994.P0120},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama94a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/FujiokaK094,
author = {Yoshichika Fujioka and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Coordinate Transformation {VLSI} Processor for Redundant Manipulator
Control},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {124--130},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0124},
doi = {10.20965/JRM.1994.P0124},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/FujiokaK094.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/SasakiK94,
author = {Yoshifumi Sasaki and
Michitaka Kameyama},
title = {Design of a Model-Based Robot Vision {VLSI} Processor},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {131--136},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0131},
doi = {10.20965/JRM.1994.P0131},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/SasakiK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/HariyamaK94,
author = {Masanori Hariyama and
Michitaka Kameyama},
title = {Architecture of a CAM-Based Collision Detection {VLSI} Processor for
Intelligent Vehicles},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {137--142},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0137},
doi = {10.20965/JRM.1994.P0137},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/HariyamaK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/KimK94,
author = {Bumchul Kim and
Michitaka Kameyama},
title = {Latency Minimization of Parallel {VLSI} Processors for Robotics Using
Integer Programming},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {143--149},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0143},
doi = {10.20965/JRM.1994.P0143},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/KimK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/AbeK094,
author = {Shigeki Abe and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of an Intelligent Fault-Tolerant System for Real-World Applications},
journal = {J. Robotics Mechatronics},
volume = {6},
number = {2},
pages = {150--154},
year = {1994},
url = {https://doi.org/10.20965/jrm.1994.p0150},
doi = {10.20965/JRM.1994.P0150},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/AbeK094.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KawahitoINKH94,
author = {Shoji Kawahito and
Makoto Ishida and
Tetsuro Nakamura and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {High-Speed Area-Efficient Multiplier Design Using Multiple-Valued
Current-Mode Circuits},
journal = {{IEEE} Trans. Computers},
volume = {43},
number = {1},
pages = {34--42},
year = {1994},
url = {https://doi.org/10.1109/12.250607},
doi = {10.1109/12.250607},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KawahitoINKH94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HanyuMK94,
author = {Takahiro Hanyu and
Akira Mochizuki and
Michitaka Kameyama},
title = {Multiple-Valued Current-Mode {MOS} Integrated Circuits Based on Dual-Rail
Source-Coupled Logic},
booktitle = {24th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1994, Boston, Massachusetts, USA, May 25-27, 1994, Proceedings},
pages = {19--26},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ISMVL.1994.302224},
doi = {10.1109/ISMVL.1994.302224},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HanyuMK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NakajimaK94,
author = {Masami Nakajima and
Michitaka Kameyama},
title = {Design of Multiple-Valued Linear Digital Circuits for Highly Parallel
\emph{k}-Ary Operations},
booktitle = {24th {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1994, Boston, Massachusetts, USA, May 25-27, 1994, Proceedings},
pages = {223--230},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ISMVL.1994.302197},
doi = {10.1109/ISMVL.1994.302197},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/NakajimaK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KaqahitoINMKH93,
author = {Shoui Kaqahito and
Makoto Ishida and
Tetsuro Nakamura and
Kentaro Mizuno and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Multi-valued current-mode parallel multiplier based on redundant positive-digit
number representations},
journal = {Syst. Comput. Jpn.},
volume = {24},
number = {5},
pages = {40--52},
year = {1993},
url = {https://doi.org/10.1002/scj.4690240504},
doi = {10.1002/SCJ.4690240504},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KaqahitoINMKH93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/FujiokaK93,
author = {Yoshichika Fujioka and
Michitaka Kameyama},
title = {2400-MFLOPS Reconfigurable Parallel {VLSI} Processor for Robot Control},
booktitle = {Proceedings of the 1993 {IEEE} International Conference on Robotics
and Automation, Atlanta, Georgia, USA, May 1993},
pages = {149--154},
publisher = {{IEEE} Computer Society Press},
year = {1993},
url = {https://doi.org/10.1109/ROBOT.1993.291857},
doi = {10.1109/ROBOT.1993.291857},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/icra/FujiokaK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/NakajimaK93,
author = {Masami Nakajima and
Michitaka Kameyama},
title = {Design of Multiple-Valued Linear Digital Circuits for Highly Parallel
Unary Operations},
booktitle = {23rd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1993, Sacramento, California, USA, May 24-27, 1993, Proceedings},
pages = {283--288},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/ISMVL.1993.289546},
doi = {10.1109/ISMVL.1993.289546},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/NakajimaK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/AokiKH92,
author = {Takafumi Aoki and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Interconnection-Free Biomolecular Computing},
journal = {Computer},
volume = {25},
number = {11},
pages = {41--50},
year = {1992},
url = {https://doi.org/10.1109/2.166410},
doi = {10.1109/2.166410},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/AokiKH92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/AokiKH92,
author = {Takafumi Aoki and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of an ultrahigher-valued biocomputing system based on set-valued
logic networks},
journal = {Syst. Comput. Jpn.},
volume = {23},
number = {7},
pages = {35--44},
year = {1992},
url = {https://doi.org/10.1002/scj.4690230704},
doi = {10.1002/SCJ.4690230704},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/AokiKH92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/ShimabukuroKH92,
author = {Katsuhiko Shimabukuro and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a Multiple-Valued {VLSI} Processor for Digital Control},
booktitle = {22nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1992, Sendai, Japan, May 27-29, 1992, Proceedings},
pages = {322--329},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ISMVL.1992.186813},
doi = {10.1109/ISMVL.1992.186813},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/ShimabukuroKH92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/HondaKH92,
author = {Makoto Honda and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Residue Arithmetic Based Multiple-Valued {VLSI} Image Processor},
booktitle = {22nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1992, Sendai, Japan, May 27-29, 1992, Proceedings},
pages = {330--336},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ISMVL.1992.186814},
doi = {10.1109/ISMVL.1992.186814},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/HondaKH92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/TamakiKH92,
author = {Saneaki Tamaki and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial
Circuits},
booktitle = {22nd {IEEE} International Symposium on Multiple-Valued Logic, {ISMVL}
1992, Sendai, Japan, May 27-29, 1992, Proceedings},
pages = {382--388},
publisher = {{IEEE} Computer Society},
year = {1992},
url = {https://doi.org/10.1109/ISMVL.1992.186820},
doi = {10.1109/ISMVL.1992.186820},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/TamakiKH92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KasugaKH91,
author = {Takeshi Kasuga and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a robust fault-tolerant multiplier},
journal = {Syst. Comput. Jpn.},
volume = {22},
number = {2},
pages = {10--18},
year = {1991},
url = {https://doi.org/10.1002/scj.4690220202},
doi = {10.1002/SCJ.4690220202},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KasugaKH91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/WeiKHM91,
author = {Shugang Wei and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Performance evaluation of a multivalued rsa encryption vlsi},
journal = {Syst. Comput. Jpn.},
volume = {22},
number = {7},
pages = {12--21},
year = {1991},
url = {https://doi.org/10.1002/scj.4690220702},
doi = {10.1002/SCJ.4690220702},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/WeiKHM91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/KittichaikoonkitKH91,
author = {Somchai Kittichaikoonkit and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {High-Performance {VLSI} Processor for Robot Inverse Dynamics Computation},
booktitle = {Proceedings 1991 {IEEE} International Conference on Computer Design:
{VLSI} in Computer {\&} Processors, {ICCD} '91, Cambridge, MA,
USA, October 14-16, 1991},
pages = {608--611},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ICCD.1991.139984},
doi = {10.1109/ICCD.1991.139984},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/KittichaikoonkitKH91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/AokiKH91,
author = {Takafumi Aoki and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of Interconnection-Free Biomolecular Computing System},
booktitle = {Proceedings of the 21st International Symposium on Multiple-Valued
Logic, {ISMVL} 1991, Victoria, BC, Canada, May 26-29, 1991},
pages = {173--180},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/ISMVL.1991.130724},
doi = {10.1109/ISMVL.1991.130724},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/AokiKH91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama90,
author = {Michitaka Kameyama},
title = {Editorial: Computer Architecture for Robotics},
journal = {J. Robotics Mechatronics},
volume = {2},
number = {6},
pages = {417},
year = {1990},
url = {https://doi.org/10.20965/jrm.1990.p0417},
doi = {10.20965/JRM.1990.P0417},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/AmadaK090,
author = {Tadao Amada and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a Parallel Collision Detection Check {VLSI} Processor for
Robot Manipulator},
journal = {J. Robotics Mechatronics},
volume = {2},
number = {6},
pages = {418--423},
year = {1990},
url = {https://doi.org/10.20965/jrm.1990.p0418},
doi = {10.20965/JRM.1990.P0418},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/AmadaK090.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kittichaikoonkit90,
author = {Somchai Kittichaikoonkit and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a Matrix Multiply-Addition {VLSI} Processor for Robot control},
journal = {J. Robotics Mechatronics},
volume = {2},
number = {6},
pages = {424--430},
year = {1990},
url = {https://doi.org/10.20965/jrm.1990.p0424},
doi = {10.20965/JRM.1990.P0424},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kittichaikoonkit90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/0001K90,
author = {Tatsuo Higuchi and
Michitaka Kameyama},
title = {Robot Electronics System},
journal = {J. Robotics Mechatronics},
volume = {2},
number = {6},
pages = {471--473},
year = {1990},
url = {https://doi.org/10.20965/jrm.1990.p0471},
doi = {10.20965/JRM.1990.P0471},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/0001K90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KameyamaWH90,
author = {Michitaka Kameyama and
Shugang Wei and
Tatsuo Higuchi},
title = {Design of an {RSA} Encryption Processor Based on Signed-Digit Multivalued
Arithmetic Circuits},
journal = {Syst. Comput. Jpn.},
volume = {21},
number = {6},
pages = {21--31},
year = {1990},
url = {https://doi.org/10.1002/scj.4690210603},
doi = {10.1002/SCJ.4690210603},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KameyamaWH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KasugaKH90,
author = {Takeshi Kasuga and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a fault-tolerant arithmetic circuit based on distributed
coding and its evaluation},
journal = {Syst. Comput. Jpn.},
volume = {21},
number = {8},
pages = {59--71},
year = {1990},
url = {https://doi.org/10.1002/scj.4690210806},
doi = {10.1002/SCJ.4690210806},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KasugaKH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KameyamaAH90,
author = {Michitaka Kameyama and
Takafumi Aoki and
Tatsuo Higuchi},
title = {Design of a Highly Parallel Ultrahigher-Valued Logic Network Based
on a Bio-Device Model},
journal = {Syst. Comput. Jpn.},
volume = {21},
number = {9},
pages = {1--12},
year = {1990},
url = {https://doi.org/10.1002/scj.4690210901},
doi = {10.1002/SCJ.4690210901},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KameyamaAH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/Kameyama90,
author = {Michitaka Kameyama},
title = {Toward the Age of Beyond-Binary Electronics and Systems},
booktitle = {Proceedings of the 20th International Symposium on Multiple-Valued
Logic, {ISMVL} 1990, Charlotte, NC, USA, May 23-25, 1990},
pages = {162--166},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/ISMVL.1990.122613},
doi = {10.1109/ISMVL.1990.122613},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/Kameyama90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ismvl/KameyamaNH90,
author = {Michitaka Kameyama and
Masahiro Nomura and
Tatsuo Higuchi},
title = {Modular Design of Multiple-Valued Arithmetic {VLSI} System Using Signed-Digit
Number System},
booktitle = {Proceedings of the 20th International Symposium on Multiple-Valued
Logic, {ISMVL} 1990, Charlotte, NC, USA, May 23-25, 1990},
pages = {355--362},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/ISMVL.1990.122647},
doi = {10.1109/ISMVL.1990.122647},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ismvl/KameyamaNH90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jrm/Kameyama089,
author = {Michitaka Kameyama and
Tatsuo Higuchi},
title = {{VLSI} Computer for Robotics},
journal = {J. Robotics Mechatronics},
volume = {1},
number = {1},
pages = {68--73},
year = {1989},
url = {https://doi.org/10.20965/jrm.1989.p0068},
doi = {10.20965/JRM.1989.P0068},
timestamp = {Wed, 01 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jrm/Kameyama089.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KameyamaKH89,
author = {Michitaka Kameyama and
Shoji Kawahito and
Tatsuo Higuchi},
title = {Bi-directional current-mode basic circuits for the multilevel signed-digit
arithmetic and their evaluation},
journal = {Syst. Comput. Jpn.},
volume = {20},
number = {6},
pages = {69--79},
year = {1989},
url = {https://doi.org/10.1002/scj.4690200608},
doi = {10.1002/SCJ.4690200608},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KameyamaKH89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/KameyamaMEH89,
author = {Michitaka Kameyama and
Takao Matsumoto and
Hideki Egami and
Tatsuo Higuchi},
title = {Implementation of a high performance {LSI} for inverse kinematics
computation},
booktitle = {Proceedings of the 1989 {IEEE} International Conference on Robotics
and Automation, Scottsdale, Arizona, USA, May 14-19, 1989},
pages = {757--762},
publisher = {{IEEE} Computer Society},
year = {1989},
url = {https://doi.org/10.1109/ROBOT.1989.100075},
doi = {10.1109/ROBOT.1989.100075},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/icra/KameyamaMEH89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/KameyamaKH88,
author = {Michitaka Kameyama and
Shoji Kawahito and
Tatsuo Higuchi},
title = {A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode
Logic Circuits},
journal = {Computer},
volume = {21},
number = {4},
pages = {43--56},
year = {1988},
url = {https://doi.org/10.1109/2.50},
doi = {10.1109/2.50},
timestamp = {Wed, 12 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/KameyamaKH88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/HuangKH88,
author = {Xi Yue Huang and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of a time-optimal digital control system for a dc-servomotor
with amplitude limitation},
journal = {Syst. Comput. Jpn.},
volume = {19},
number = {2},
pages = {64--73},
year = {1988},
url = {https://doi.org/10.1002/scj.4690190207},
doi = {10.1002/SCJ.4690190207},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/HuangKH88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KameyamaZH88,
author = {Michitaka Kameyama and
Li Zheng and
Tatsuo Higuchi},
title = {Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach
and Its Application to a Digital Control System},
journal = {Syst. Comput. Jpn.},
volume = {19},
number = {12},
pages = {81--91},
year = {1988},
url = {https://doi.org/10.1002/scj.4690191209},
doi = {10.1002/SCJ.4690191209},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KameyamaZH88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/HanyuKH87,
author = {Takahiro Hanyu and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design and implementation of an nmos image processor based on quaternary
logic},
journal = {Syst. Comput. Jpn.},
volume = {18},
number = {3},
pages = {92--106},
year = {1987},
url = {https://doi.org/10.1002/scj.4690180309},
doi = {10.1002/SCJ.4690180309},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/HanyuKH87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/KawahitoKH87,
author = {Shoji Kawahito and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using
multiple-valued logic},
journal = {Syst. Comput. Jpn.},
volume = {18},
number = {4},
pages = {41--52},
year = {1987},
url = {https://doi.org/10.1002/scj.4690180405},
doi = {10.1002/SCJ.4690180405},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/KawahitoKH87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/ZukeranAKH87,
author = {Chotei Zukeran and
Chushin Afuso and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of micropower {CMOS} quaternary memory circuits},
journal = {Syst. Comput. Jpn.},
volume = {18},
number = {11},
pages = {61--69},
year = {1987},
url = {https://doi.org/10.1002/scj.4690181107},
doi = {10.1002/SCJ.4690181107},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/ZukeranAKH87.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/ZukeranAK086,
author = {Chotei Zukeran and
Chushin Afuso and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of low-power quaternary {CMOS} logic circuits},
journal = {Syst. Comput. Jpn.},
volume = {17},
number = {3},
pages = {93--101},
year = {1986},
url = {https://doi.org/10.1002/scj.4690170311},
doi = {10.1002/SCJ.4690170311},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/ZukeranAK086.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/scjapan/TomabechiK086,
author = {Nobuhiro Tomabechi and
Michitaka Kameyama and
Tatsuo Higuchi},
title = {Design of lsi-oriented digital signal processing system Based on Pulse-Train
Residue Arithmetic Circuits},
journal = {Syst. Comput. Jpn.},
volume = {17},
number = {6},
pages = {76--84},
year = {1986},
url = {https://doi.org/10.1002/scj.4690170609},
doi = {10.1002/SCJ.4690170609},
timestamp = {Wed, 13 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/scjapan/TomabechiK086.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/HiguchiK77,
author = {Tatsuo Higuchi and
Michitaka Kameyama},
title = {Static-Hazard-Free \emph{T}-Gate for Ternary Memory Element and Its
Application to Ternary Counters},
journal = {{IEEE} Trans. Computers},
volume = {26},
number = {12},
pages = {1212--1221},
year = {1977},
url = {https://doi.org/10.1109/TC.1977.1674782},
doi = {10.1109/TC.1977.1674782},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/HiguchiK77.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KameyamaH77,
author = {Michitaka Kameyama and
Tatsuo Higuchi},
title = {Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal
Logic Module},
journal = {{IEEE} Trans. Computers},
volume = {26},
number = {12},
pages = {1297--1302},
year = {1977},
url = {https://doi.org/10.1109/TC.1977.1674797},
doi = {10.1109/TC.1977.1674797},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KameyamaH77.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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