BibTeX records: Takayuki Kamei

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@inproceedings{DBLP:conf/ijcnn/KameiOKK12,
  author       = {Takayuki Kamei and
                  Keiko Ono and
                  Masahito Kumano and
                  Masahiro Kimura},
  title        = {Predicting missing links in social networks with hierarchical dirichlet
                  processes},
  booktitle    = {The 2012 International Joint Conference on Neural Networks (IJCNN),
                  Brisbane, Australia, June 10-15, 2012},
  pages        = {1--8},
  publisher    = {{IEEE}},
  year         = {2012},
  url          = {https://doi.org/10.1109/IJCNN.2012.6252619},
  doi          = {10.1109/IJCNN.2012.6252619},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/ijcnn/KameiOKK12.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/IshiwataYTSKMYT03,
  author       = {Shunichi Ishiwata and
                  Tomoo Yamakage and
                  Yoshiro Tsuboi and
                  Takayoshi Shimazawa and
                  Tomoko Kitazawa and
                  Shuji Michinaka and
                  Kunihiko Yahagi and
                  Hideki Takeda and
                  Akihiro Oue and
                  Tomoya Kodama and
                  Nobu Matsumoto and
                  Takayuki Kamei and
                  Mitsuo Saito and
                  Takashi Miyamori and
                  Goichi Ootomo and
                  Masataka Matsui},
  title        = {A single-chip {MPEG-2} codec based on customizable media embedded
                  processor},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {38},
  number       = {3},
  pages        = {530--540},
  year         = {2003},
  url          = {https://doi.org/10.1109/JSSC.2002.808291},
  doi          = {10.1109/JSSC.2002.808291},
  timestamp    = {Wed, 20 Apr 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/IshiwataYTSKMYT03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/cicc/IshiwataYTSKMYT02,
  author       = {Shunichi Ishiwata and
                  Tomoo Yamakage and
                  Yoshiro Tsuboi and
                  Takayoshi Shimazawa and
                  Tomoko Kitazawa and
                  Shuji Michinaka and
                  Kunihiko Yahagi and
                  Hideki Takeda and
                  Akihiro Oue and
                  Tomoya Kodama and
                  Nobu Matsumoto and
                  Takayuki Kamei and
                  Takashi Miyamori and
                  Goichi Ootomo and
                  Masataka Matsui},
  title        = {A single-chip {MPEG-2} codec based on customizable media microprocessor},
  booktitle    = {Proceedings of the {IEEE} 2002 Custom Integrated Circuits Conference,
                  {CICC} 2002, Orlando, FL, USA, May 12-15, 2002},
  pages        = {163--166},
  publisher    = {{IEEE}},
  year         = {2002},
  url          = {https://doi.org/10.1109/CICC.2002.1012789},
  doi          = {10.1109/CICC.2002.1012789},
  timestamp    = {Tue, 04 Oct 2022 22:39:17 +0200},
  biburl       = {https://dblp.org/rec/conf/cicc/IshiwataYTSKMYT02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/jssc/IdeHEYMKSKOS00,
  author       = {Nobuhiro Ide and
                  Masashi Hirano and
                  Yukio Endo and
                  Shin{-}ichi Yoshioka and
                  Hiroaki Murakami and
                  Atsushi Kunimatsu and
                  Toshinori Sato and
                  Takayuki Kamei and
                  Toyoshi Okada and
                  Masakazu Suzuoki},
  title        = {2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance
                  3D graphics computing},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {35},
  number       = {7},
  pages        = {1025--1033},
  year         = {2000},
  url          = {https://doi.org/10.1109/4.848212},
  doi          = {10.1109/4.848212},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/IdeHEYMKSKOS00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/micro/KunimatsuISEMKHITOOYOS00,
  author       = {Atsushi Kunimatsu and
                  Nobuhiro Ide and
                  Toshinori Sato and
                  Yukio Endo and
                  Hiroaki Murakami and
                  Takayuki Kamei and
                  Masashi Hirano and
                  Fujio Ishihara and
                  Haruyuki Tago and
                  Masaaki Oka and
                  Akio Ohba and
                  Teiji Yutaka and
                  Toyoshi Okada and
                  Masakazu Suzuoki},
  title        = {Vector Unit Architecture for Emotion Synthesis},
  journal      = {{IEEE} Micro},
  volume       = {20},
  number       = {2},
  pages        = {40--47},
  year         = {2000},
  url          = {https://doi.org/10.1109/40.848471},
  doi          = {10.1109/40.848471},
  timestamp    = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/micro/KunimatsuISEMKHITOOYOS00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/KameiTOSTKNISMIEAK00,
  author       = {Takayuki Kamei and
                  Hideaki Takeda and
                  Yukio Ootaguro and
                  Takayoshi Shimazawa and
                  Kazuhiko Tachibana and
                  Shin'ichi Kawakami and
                  Seiji Norimatsu and
                  Fujio Ishihara and
                  Toshinori Sato and
                  Hiroaki Murakami and
                  Nobuhiro Ide and
                  Yukio Endo and
                  Akira Aono and
                  Atsushi Kunimatsu},
  title        = {300MHz design methodology of {VU} for emotion synthesis},
  booktitle    = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
                  Conference 2000, Yokohama, Japan},
  pages        = {635--640},
  publisher    = {{ACM}},
  year         = {2000},
  url          = {https://doi.org/10.1145/368434.368847},
  doi          = {10.1145/368434.368847},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/aspdac/KameiTOSTKNISMIEAK00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/pc/YamamotoFKKHA99,
  author       = {Junji Yamamoto and
                  Takashi Fujiwara and
                  T. Komeda and
                  Takayuki Kamei and
                  Toshihiro Hanawa and
                  Hideharu Amano},
  title        = {Performance evaluation of {SNAIL:} {A} multiprocessor based on the
                  simple serial synchronized multistage interconnection network architecture},
  journal      = {Parallel Comput.},
  volume       = {25},
  number       = {9},
  pages        = {1081--1103},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0167-8191(99)00038-1},
  doi          = {10.1016/S0167-8191(99)00038-1},
  timestamp    = {Sat, 22 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/pc/YamamotoFKKHA99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/MidorikawaKHA98,
  author       = {Takashi Midorikawa and
                  Takayuki Kamei and
                  Toshihiro Hanawa and
                  Hideharu Amano},
  title        = {The {MINC} (Multistage Interconnection Network with Cache Control
                  Mechanism) Chip},
  booktitle    = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
                  Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
                  1998},
  pages        = {337--338},
  publisher    = {{IEEE}},
  year         = {1998},
  url          = {https://doi.org/10.1109/ASPDAC.1998.669494},
  doi          = {10.1109/ASPDAC.1998.669494},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/MidorikawaKHA98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/KameiSA97,
  author       = {Takayuki Kamei and
                  Masashi Sasahara and
                  Hideharu Amano},
  title        = {An {LSI} implementation of the simple serial synchronized multistage
                  interconnection network},
  booktitle    = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
                  Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
                  1997},
  pages        = {673--674},
  publisher    = {{IEEE}},
  year         = {1997},
  url          = {https://doi.org/10.1109/ASPDAC.1997.600358},
  doi          = {10.1109/ASPDAC.1997.600358},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/KameiSA97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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