Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Masahiro Iida
@article{DBLP:journals/ieiceta/KugaZNAI23,
author = {Morihiro Kuga and
Qian Zhao and
Yuya Nakazato and
Motoki Amagasaki and
Masahiro Iida},
title = {An eFPGA Generation Suite with Customizable Architecture and {IDE}},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {106},
number = {3},
pages = {560--574},
year = {2023},
url = {https://doi.org/10.1587/transfun.2022vlp0008},
doi = {10.1587/TRANSFUN.2022VLP0008},
timestamp = {Thu, 09 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceta/KugaZNAI23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/NakaharaKAZI22,
author = {Yasuhiro Nakahara and
Masato Kiyama and
Motoki Amagasaki and
Qian Zhao and
Masahiro Iida},
title = {Reconfigurable Neural Network Accelerator and Simulator for Model
Implementation},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {105-A},
number = {3},
pages = {448--458},
year = {2022},
url = {https://doi.org/10.1587/transfun.2021vlp0012},
doi = {10.1587/TRANSFUN.2021VLP0012},
timestamp = {Thu, 12 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/NakaharaKAZI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/NakaharaMKAI22,
author = {Yasuhiro Nakahara and
Yuta Masuda and
Masato Kiyama and
Motoki Amagasaki and
Masahiro Iida},
title = {A Posit Based Multiply-accumulate Unit with Small Quire Size for Deep
Neural Networks},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {15},
pages = {16--19},
year = {2022},
url = {https://doi.org/10.2197/ipsjtsldm.15.16},
doi = {10.2197/IPSJTSLDM.15.16},
timestamp = {Fri, 24 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/NakaharaMKAI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KugaIA22,
author = {Morihiro Kuga and
Masahiro Iida and
Hideharu Amano},
title = {{FPL} Demo: An {FPGA-IP} Prototype Chip for {MEC} devices},
booktitle = {32nd International Conference on Field-Programmable Logic and Applications,
{FPL} 2022, Belfast, United Kingdom, August 29 - Sept. 2, 2022},
pages = {467},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/FPL57034.2022.00083},
doi = {10.1109/FPL57034.2022.00083},
timestamp = {Mon, 20 Feb 2023 17:38:16 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KugaIA22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/TaguchiSI22,
author = {Kaito Taguchi and
Kouichi Sakurai and
Masahiro Iida},
title = {Towards the Design of Locally Differential Private Hardware System
for Edge Computing},
booktitle = {Tenth International Symposium on Computing and Networking, {CANDAR}
2022, Himeji, Japan, November 21-24, 2022},
pages = {186--191},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/CANDAR57322.2022.00033},
doi = {10.1109/CANDAR57322.2022.00033},
timestamp = {Mon, 13 Feb 2023 21:53:10 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/TaguchiSI22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NakazatoA0IK21,
author = {Yuya Nakazato and
Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga},
editor = {Christian Plessl and
Paul Chow and
Marco Platzner},
title = {Automation of Domain-specific {FPGA-IP} Generation and Test},
booktitle = {{HEART} '21: 11th International Symposium on Highly Efficient Accelerators
and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June,
2021},
pages = {4:1--4:6},
publisher = {{ACM}},
year = {2021},
url = {https://doi.org/10.1145/3468044.3468048},
doi = {10.1145/3468044.3468048},
timestamp = {Tue, 03 Aug 2021 16:44:55 +0200},
biburl = {https://dblp.org/rec/conf/heart/NakazatoA0IK21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/MasudaNAI21,
author = {Yuta Masuda and
Yasuhiro Nakahara and
Motoki Amagasaki and
Masahiro Iida},
title = {Automatic executable code generation for {DNN} accelerator ReNA},
booktitle = {Ninth International Symposium on Computing and Networking, {CANDAR}
2021 - Workshops, Matsue, Japan, 23-26 November 2021},
pages = {107--113},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/CANDARW53999.2021.00025},
doi = {10.1109/CANDARW53999.2021.00025},
timestamp = {Fri, 18 Feb 2022 10:36:44 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/MasudaNAI21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2106-08892,
author = {Masato Kiyama and
Motoki Amagasaki and
Masahiro Iida},
title = {Development of Quantized {DNN} Library for Exact Hardware Emulation},
journal = {CoRR},
volume = {abs/2106.08892},
year = {2021},
url = {https://arxiv.org/abs/2106.08892},
eprinttype = {arXiv},
eprint = {2106.08892},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2106-08892.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicetd/NakaharaKAI20,
author = {Yasuhiro Nakahara and
Masato Kiyama and
Motoki Amagasaki and
Masahiro Iida},
title = {Relationship between Recognition Accuracy and Numerical Precision
in Convolutional Neural Network Models},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {103-D},
number = {12},
pages = {2528--2529},
year = {2020},
url = {https://doi.org/10.1587/transinf.2020PAL0002},
doi = {10.1587/TRANSINF.2020PAL0002},
timestamp = {Mon, 18 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieicetd/NakaharaKAI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AmagasakiOFIYI20,
author = {Motoki Amagasaki and
Hiroki Oyama and
Yuichiro Fujishiro and
Masahiro Iida and
Hiroaki Yasuda and
Hiroto Ito},
title = {{R-GCN} Based Function Inference for Gate-level Netlist},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {13},
pages = {69--71},
year = {2020},
url = {https://doi.org/10.2197/ipsjtsldm.13.69},
doi = {10.2197/IPSJTSLDM.13.69},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AmagasakiOFIYI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/0001AIY20,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Takaichi Yoshida},
title = {Architecture-aware Cost Function for 3D {FPGA} Placement Using Convolutional
Neural Network},
booktitle = {Eighth International Symposium on Computing and Networking, {CANDAR}
2020, Naha, Japan, November 24-27, 2020},
pages = {235--241},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/CANDAR51075.2020.00040},
doi = {10.1109/CANDAR51075.2020.00040},
timestamp = {Fri, 16 Apr 2021 10:58:06 +0200},
biburl = {https://dblp.org/rec/conf/ic-nc/0001AIY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/0001NAIY20,
author = {Qian Zhao and
Yasuhiro Nakahara and
Motoki Amagasaki and
Masahiro Iida and
Takaichi Yoshida},
title = {A Microcode-based Control Unit for Deep Learning Processors},
booktitle = {2020 {IEEE} International Parallel and Distributed Processing Symposium
Workshops, {IPDPSW} 2020, New Orleans, LA, USA, May 18-22, 2020},
pages = {139--142},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/IPDPSW50202.2020.00031},
doi = {10.1109/IPDPSW50202.2020.00031},
timestamp = {Wed, 05 Aug 2020 14:05:53 +0200},
biburl = {https://dblp.org/rec/conf/ipps/0001NAIY20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/tencon/DianaAI20,
author = {Mery Diana and
Motoki Amagasaki and
Masahiro Iida},
title = {Image Search System Based on Feature Vectors of Convolutional Neural
Network},
booktitle = {2020 {IEEE} Region 10 Conference, {TENCON} 2020, Osaka, Japan, November
16-19, 2020},
pages = {934--939},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/TENCON50793.2020.9293773},
doi = {10.1109/TENCON50793.2020.9293773},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/tencon/DianaAI20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceee/MyintAZI19,
author = {Theingi Myint and
Motoki Amagasaki and
Qian Zhao and
Masahiro Iida},
title = {A SLM-based overlay architecture for fine-grained virtual {FPGA}},
journal = {{IEICE} Electron. Express},
volume = {16},
number = {24},
pages = {20190610},
year = {2019},
url = {https://doi.org/10.1587/elex.16.20190610},
doi = {10.1587/ELEX.16.20190610},
timestamp = {Fri, 12 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ieiceee/MyintAZI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/ZhaoOIY19,
author = {Qian Zhao and
Yoshimasa Ohnishi and
Masahiro Iida and
Takaichi Yoshida},
editor = {Christian Hochberger and
Brent Nelson and
Andreas Koch and
Roger F. Woods and
Pedro C. Diniz},
title = {A Resource Reduced Application-Specific {FPGA} Switch},
booktitle = {Applied Reconfigurable Computing - 15th International Symposium, {ARC}
2019, Darmstadt, Germany, April 9-11, 2019, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {11444},
pages = {58--67},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-17227-5\_5},
doi = {10.1007/978-3-030-17227-5\_5},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/ZhaoOIY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ic-nc/KiyamaNAI19,
author = {Masato Kiyama and
Yasuhiro Nakahara and
Motoki Amagasaki and
Masahiro Iida},
title = {A Quantized Neural Network Library for Proper Implementation of Hardware
Emulation},
booktitle = {Seventh International Symposium on Computing and Networking Workshops,
{CANDAR} 2019 Workshops, Nagasaki, Japan, November 26-29, 2019},
pages = {136--140},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/CANDARW.2019.00032},
doi = {10.1109/CANDARW.2019.00032},
timestamp = {Tue, 04 Feb 2020 15:59:02 +0100},
biburl = {https://dblp.org/rec/conf/ic-nc/KiyamaNAI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/MyintA0IK19,
author = {Theingi Myint and
Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Masato Kiyama},
title = {A Novel SLM-Based Virtual {FPGA} Overlay Architecture},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {74--80},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00018},
doi = {10.1109/MCSOC.2019.00018},
timestamp = {Tue, 26 Nov 2019 20:28:29 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/MyintA0IK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mcsoc/KiyamaAI19,
author = {Masato Kiyama and
Motoki Amagasaki and
Masahiro Iida},
title = {Deep Learning Framework with Arbitrary Numerical Precision},
booktitle = {13th {IEEE} International Symposium on Embedded Multicore/Many-core
Systems-on-Chip, MCSoC 2019, Singapore, Singapore, October 1-4, 2019},
pages = {81--86},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/MCSoC.2019.00019},
doi = {10.1109/MCSOC.2019.00019},
timestamp = {Tue, 26 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mcsoc/KiyamaAI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AmagasakiIZIS18,
author = {Motoki Amagasaki and
Masato Ikebe and
Qian Zhao and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Three Dimensional {FPGA} Architecture with Fewer TSVs},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {2},
pages = {278--287},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017RCP0008},
doi = {10.1587/TRANSINF.2017RCP0008},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AmagasakiIZIS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhaoAIKS18,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Enabling FPGA-as-a-Service in the Cloud with hCODE Platform},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {2},
pages = {335--343},
year = {2018},
url = {https://doi.org/10.1587/transinf.2017RCP0004},
doi = {10.1587/TRANSINF.2017RCP0004},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhaoAIKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/KitasukaMI18,
author = {Teruaki Kitasuka and
Takayuki Matsuzaki and
Masahiro Iida},
title = {Order Adjustment Approach Using Cayley Graphs for the Order/Degree
Problem},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {101-D},
number = {12},
pages = {2908--2915},
year = {2018},
url = {https://doi.org/10.1587/transinf.2018PAP0008},
doi = {10.1587/TRANSINF.2018PAP0008},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/KitasukaMI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/18/Iida18,
author = {Masahiro Iida},
editor = {Hideharu Amano},
title = {What Is an FPGA?},
booktitle = {Principles and Structures of FPGAs},
pages = {23--45},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-0824-6\_2},
doi = {10.1007/978-981-13-0824-6\_2},
timestamp = {Tue, 11 Sep 2018 08:33:58 +0200},
biburl = {https://dblp.org/rec/books/sp/18/Iida18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/18/Iida18a,
author = {Masahiro Iida},
editor = {Hideharu Amano},
title = {Design Methodology},
booktitle = {Principles and Structures of FPGAs},
pages = {117--135},
publisher = {Springer},
year = {2018},
url = {https://doi.org/10.1007/978-981-13-0824-6\_5},
doi = {10.1007/978-981-13-0824-6\_5},
timestamp = {Tue, 11 Sep 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/books/sp/18/Iida18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AmagasakiNIIKS17,
author = {Motoki Amagasaki and
Yuki Nishitani and
Kazuki Inoue and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Physical Fault Detection and Recovery Methods for System-LSI Loaded
{FPGA-IP} Core},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {100-D},
number = {4},
pages = {633--644},
year = {2017},
url = {https://doi.org/10.1587/transinf.2016AWI0005},
doi = {10.1587/TRANSINF.2016AWI0005},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AmagasakiNIIKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/ZhaoAIKS17,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Towards Open-HW: {A} Platform to Design, Share and Deploy {FPGA} Accelerators
in Low Cost},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {10},
pages = {63--70},
year = {2017},
url = {https://doi.org/10.2197/ipsjtsldm.10.63},
doi = {10.2197/IPSJTSLDM.10.63},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/ZhaoAIKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asplos/0001IS17,
author = {Qian Zhao and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A Study of {FPGA} Virtualization and Accelerator Scheduling},
booktitle = {Proceedings of the first Workshop on Emerging Technologies for software-defined
and reconfigurable hardware-accelerated Cloud Datacenters, ETCD@ASPLOS
2017, Xi'an, China, April 8, 2017},
pages = {3:1--3:4},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3129457.3129503},
doi = {10.1145/3129457.3129503},
timestamp = {Tue, 06 Nov 2018 11:07:42 +0100},
biburl = {https://dblp.org/rec/conf/asplos/0001IS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/0001HAIKS17,
author = {Qian Zhao and
Hendarmawan and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled
clouds},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {267--270},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280157},
doi = {10.1109/FPT.2017.8280157},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/0001HAIKS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/AmagasakiMKIS17,
author = {Motoki Amagasaki and
Futoshi Murase and
Morihiro Kuga and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Diana G{\"{o}}hringer and
Michael H{\"{u}}bner},
title = {{FPGA} based {ASIC} Emulator with High Speed Optical Serial Links},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
Germany, June 7-9, 2017},
pages = {18:1--18:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3120895.3120913},
doi = {10.1145/3120895.3120913},
timestamp = {Wed, 28 Apr 2021 16:06:55 +0200},
biburl = {https://dblp.org/rec/conf/heart/AmagasakiMKIS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KugaFAIS17,
author = {Morihiro Kuga and
Kansuke Fukuda and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Diana G{\"{o}}hringer and
Michael H{\"{u}}bner},
title = {High-level Synthesis based on Parallel Design Patterns using a Functional
Language},
booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
Germany, June 7-9, 2017},
pages = {23:1--23:6},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3120895.3120918},
doi = {10.1145/3120895.3120918},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/heart/KugaFAIS17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AmagasakiAIS16,
author = {Motoki Amagasaki and
Ryo Araki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {{SLM:} {A} Scalable Logic Module Architecture with Less Configuration
Memory},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {99-A},
number = {12},
pages = {2500--2506},
year = {2016},
url = {https://doi.org/10.1587/transfun.E99.A.2500},
doi = {10.1587/TRANSFUN.E99.A.2500},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AmagasakiAIS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ZhaoAIKS16,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A Study of Heterogeneous Computing Design Method based on Virtualization
Technology},
journal = {{SIGARCH} Comput. Archit. News},
volume = {44},
number = {4},
pages = {86--91},
year = {2016},
url = {https://doi.org/10.1145/3039902.3039918},
doi = {10.1145/3039902.3039918},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/ZhaoAIKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhaoNAIKS16,
author = {Qian Zhao and
Takuya Nakamichi and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Yuchen Song and
Shaojun Wang and
Brent Nelson and
Junbao Li and
Yu Peng},
title = {hCODE: An open-source platform for {FPGA} accelerators},
booktitle = {2016 International Conference on Field-Programmable Technology, {FPT}
2016, Xi'an, China, December 7-9, 2016},
pages = {205--208},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/FPT.2016.7929534},
doi = {10.1109/FPT.2016.7929534},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/ZhaoNAIKS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/AmagasakiNTIS16,
author = {Motoki Amagasaki and
Yuji Nakamura and
Takuya Teraoka and
Masahiro Iida and
Toshinori Sueyoshi},
title = {An area compact soft error resident circuit for {FPGA}},
booktitle = {International Conference on {IC} Design and Technology, {ICICDT} 2016,
Ho Chi Minh, Vietnam, June 27-29, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICICDT.2016.7542046},
doi = {10.1109/ICICDT.2016.7542046},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/AmagasakiNTIS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/KitasukaI16,
author = {Teruaki Kitasuka and
Masahiro Iida},
title = {A heuristic method of generating diameter 3 graphs for order/degree
problem (invited paper)},
booktitle = {Tenth {IEEE/ACM} International Symposium on Networks-on-Chip, {NOCS}
2016, Nara, Japan, August 31 - September 2, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/NOCS.2016.7579334},
doi = {10.1109/NOCS.2016.7579334},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/nocs/KitasukaI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmagasakiNTIS16,
author = {Motoki Amagasaki and
Yuji Nakamura and
Takuya Teraoka and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A novel soft error tolerant {FPGA} architecture},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753574},
doi = {10.1109/VLSI-SOC.2016.7753574},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmagasakiNTIS16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/KitasukaI16,
author = {Teruaki Kitasuka and
Masahiro Iida},
title = {A Heuristic Method of Generating Diameter 3 Graphs for Order/Degree
Problem},
journal = {CoRR},
volume = {abs/1609.03136},
year = {2016},
url = {http://arxiv.org/abs/1609.03136},
eprinttype = {arXiv},
eprint = {1609.03136},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/KitasukaI16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/AmagasakiZIKS15,
author = {Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Fault-Tolerant {FPGA:} Architectures and Design for Programmable Logic
Intellectual Property Core in SoC},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {98-D},
number = {2},
pages = {252--261},
year = {2015},
url = {https://doi.org/10.1587/transinf.2014RCP0009},
doi = {10.1587/TRANSINF.2014RCP0009},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/AmagasakiZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/AmagasakiZIKS15,
author = {Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A 3D {FPGA} Architecture to Realize Simple Die Stacking},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {8},
pages = {116--122},
year = {2015},
url = {https://doi.org/10.2197/ipsjtsldm.8.116},
doi = {10.2197/IPSJTSLDM.8.116},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/AmagasakiZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icicdt/AmagasakiZIKS15,
author = {Motoki Amagasaki and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Simple wafer stacking 3D-FPGA architecture},
booktitle = {2015 International Conference on {IC} Design {\&} Technology,
{ICICDT} 2015, Leuven, Belgium, June 1-3, 2015},
pages = {1--4},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICICDT.2015.7165917},
doi = {10.1109/ICICDT.2015.7165917},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/icicdt/AmagasakiZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmagasakiTZIKS15,
author = {Motoki Amagasaki and
Yuto Takeuchi and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Architecture exploration of 3D {FPGA} to minimize internal layer connection},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {110--115},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314401},
doi = {10.1109/VLSI-SOC.2015.7314401},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmagasakiTZIKS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhaoYAIKS14,
author = {Qian Zhao and
Kyosei Yanagida and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A logic cell architecture exploiting the shannon expansion for the
reduction of configuration memory},
booktitle = {24th International Conference on Field Programmable Logic and Applications,
{FPL} 2014, Munich, Germany, 2-4 September, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPL.2014.6927460},
doi = {10.1109/FPL.2014.6927460},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ZhaoYAIKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/MashimoAIKS14,
author = {Susumu Mashimo and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Zyndroid: An Android platform for software/hardware coprocessing},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {272--275},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082792},
doi = {10.1109/FPT.2014.7082792},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/MashimoAIKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KajiwaraZAIKS14,
author = {Takuya Kajiwara and
Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morituro Kuga and
Toshinori Sueyoshi},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {A novel three-dimensional {FPGA} architecture with high-speed serial
communication links},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {306--309},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082805},
doi = {10.1109/FPT.2014.7082805},
timestamp = {Wed, 18 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/KajiwaraZAIKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/MashimoFAIKS14,
author = {Susumu Mashimo and
Kansuke Fukuda and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Jialin Chen and
Wenbo Yin and
Yuichiro Shibata and
Lingli Wang and
Hayden Kwok{-}Hay So and
Yuchun Ma},
title = {Blokus Duo engine on a Zynq},
booktitle = {2014 International Conference on Field-Programmable Technology, {FPT}
2014, Shanghai, China, December 10-12, 2014},
pages = {374--377},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/FPT.2014.7082824},
doi = {10.1109/FPT.2014.7082824},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpt/MashimoFAIKS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ZhaoIAIKS13,
author = {Qian Zhao and
Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {{FPGA} Design Framework Combined with Commercial {VLSI} {CAD}},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {96-D},
number = {8},
pages = {1602--1612},
year = {2013},
url = {https://doi.org/10.1587/transinf.E96.D.1602},
doi = {10.1587/TRANSINF.E96.D.1602},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ZhaoIAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/OgawaIAKS13,
author = {Yuki Ogawa and
Masahiro Iida and
Motoki Amagasaki and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A reconfigurable Java accelerator with software compatibility for
embedded systems},
journal = {{SIGARCH} Comput. Archit. News},
volume = {41},
number = {5},
pages = {71--76},
year = {2013},
url = {https://doi.org/10.1145/2641361.2641373},
doi = {10.1145/2641361.2641373},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/OgawaIAKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhaoIAIKS13,
author = {Qian Zhao and
Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Brad L. Hutchings and
Vaughn Betz},
title = {A novel {FPGA} design framework with {VLSI} post-routing performance
analysis (abstract only)},
booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable
Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013},
pages = {271},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2435264.2435327},
doi = {10.1145/2435264.2435327},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZhaoIAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmagasakiIZIKS13,
author = {Motoki Amagasaki and
Kazuki Inoue and
Qian Zhao and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Defect-robust {FPGA} architectures for intellectual property cores
in system {LSI}},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--7},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645499},
doi = {10.1109/FPL.2013.6645499},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmagasakiIZIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ZhaoAIKS13,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {An automatic {FPGA} design and implementation framework},
booktitle = {23rd International Conference on Field programmable Logic and Applications,
{FPL} 2013, Porto, Portugal, September 2-4, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/FPL.2013.6645593},
doi = {10.1109/FPL.2013.6645593},
timestamp = {Wed, 18 Oct 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ZhaoAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/recosoc/ZhaoAIKS13,
author = {Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {An {FPGA} design and implementation framework combined with commercial
{VLSI} CADs},
booktitle = {2013 8th International Workshop on Reconfigurable and Communication-Centric
Systems-on-Chip (ReCoSoC), Darmstadt, Germany, July 10-12, 2013},
pages = {1--7},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ReCoSoC.2013.6581534},
doi = {10.1109/RECOSOC.2013.6581534},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/recosoc/ZhaoAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HamadaZAIKS13,
author = {Tetsuro Hamada and
Qian Zhao and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Three-dimensional stacking {FPGA} architecture using face-to-face
integration},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
pages = {192--197},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673274},
doi = {10.1109/VLSI-SOC.2013.6673274},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/HamadaZAIKS13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IidaAOZS12,
author = {Masahiro Iida and
Motoki Amagasaki and
Yasuhiro Okamoto and
Qian Zhao and
Toshinori Sueyoshi},
title = {{COGRE:} {A} Novel Compact Logic Cell Architecture for Area Minimization},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {294--302},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.294},
doi = {10.1587/TRANSINF.E95.D.294},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IidaAOZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/InoueKAIISIS12,
author = {Kazuki Inoue and
Masahiro Koga and
Motoki Amagasaki and
Masahiro Iida and
Yoshinobu Ichida and
Mitsuro Saji and
Jun Iida and
Toshinori Sueyoshi},
title = {An Easily Testable Routing Architecture and Prototype Chip},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {95-D},
number = {2},
pages = {303--313},
year = {2012},
url = {https://doi.org/10.1587/transinf.E95.D.303},
doi = {10.1587/TRANSINF.E95.D.303},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/InoueKAIISIS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IchinomiyaKAKIS12,
author = {Yoshihiro Ichinomiya and
Tsuyoshi Kimura and
Motoki Amagasaki and
Morihiro Kuga and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Fault-Injection Analysis to Estimate {SEU} Failure in Time by Using
Frame-Based Partial Reconfiguration},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {95-A},
number = {12},
pages = {2347--2356},
year = {2012},
url = {https://doi.org/10.1587/transfun.E95.A.2347},
doi = {10.1587/TRANSFUN.E95.A.2347},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IchinomiyaKAKIS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/IchinomiyaUAIKS12,
author = {Yoshihiro Ichinomiya and
Sadaki Usagawa and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Designing Flexible Reconfigurable Regions to Relocate Partial Bitstreams},
booktitle = {2012 {IEEE} 20th Annual International Symposium on Field-Programmable
Custom Computing Machines, {FCCM} 2012, 29 April - 1 May 2012, Toronto,
Ontario, Canada},
pages = {241},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/FCCM.2012.51},
doi = {10.1109/FCCM.2012.51},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/IchinomiyaUAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/InoueNAIKS12,
author = {Kazuki Inoue and
Yuki Nishitani and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Dirk Koch and
Satnam Singh and
Jim T{\o}rresen},
title = {Fault detection and avoidance of {FPGA} in various granularities},
booktitle = {22nd International Conference on Field Programmable Logic and Applications
(FPL), Oslo, Norway, August 29-31, 2012},
pages = {539--542},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPL.2012.6339274},
doi = {10.1109/FPL.2012.6339274},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/InoueNAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/IchinomiyaTAKIS12,
author = {Yoshihiro Ichinomiya and
Kohei Takano and
Motoki Amagasaki and
Morihiro Kuga and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Accelerated evaluation of {SEU} failure-in-time using frame-based
partial reconfiguration},
booktitle = {2012 International Conference on Field-Programmable Technology, {FPT}
2012, Seoul, Korea (South), December 10-12, 2012},
pages = {220--223},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/FPT.2012.6412137},
doi = {10.1109/FPT.2012.6412137},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/IchinomiyaTAKIS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ica3pp/IchinomiyaAIKS12,
author = {Yoshihiro Ichinomiya and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Yang Xiang and
Ivan Stojmenovic and
Bernady O. Apduhan and
Guojun Wang and
Koji Nakano and
Albert Y. Zomaya},
title = {A Bitstream Relocation Technique to Improve Flexibility of Partial
Reconfiguration},
booktitle = {Algorithms and Architectures for Parallel Processing - 12th International
Conference, {ICA3PP} 2012, Fukuoka, Japan, September 4-7, 2012, Proceedings,
Part {I}},
series = {Lecture Notes in Computer Science},
volume = {7439},
pages = {139--152},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-33078-0\_11},
doi = {10.1007/978-3-642-33078-0\_11},
timestamp = {Fri, 31 Jul 2020 08:38:49 +0200},
biburl = {https://dblp.org/rec/conf/ica3pp/IchinomiyaAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ica3pp/FujinoTIAKIS12,
author = {Makoto Fujino and
Hiroki Tanaka and
Yoshihiro Ichinomiya and
Motoki Amagasaki and
Morihiro Kuga and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Yang Xiang and
Ivan Stojmenovic and
Bernady O. Apduhan and
Guojun Wang and
Koji Nakano and
Albert Y. Zomaya},
title = {Fault Recovery Technique for {TMR} Softcore Processor System Using
Partial Reconfiguration},
booktitle = {Algorithms and Architectures for Parallel Processing - 12th International
Conference, {ICA3PP} 2012, Fukuoka, Japan, September 4-7, 2012, Proceedings,
Part {I}},
series = {Lecture Notes in Computer Science},
volume = {7439},
pages = {392--404},
publisher = {Springer},
year = {2012},
url = {https://doi.org/10.1007/978-3-642-33078-0\_28},
doi = {10.1007/978-3-642-33078-0\_28},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ica3pp/FujinoTIAKIS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/reconfig/NishitaniIAIKS12,
author = {Yuki Nishitani and
Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {A novel physical defects recovery technique for {FPGA-IP} cores},
booktitle = {2012 International Conference on Reconfigurable Computing and FPGAs,
ReConFig 2012, Cancun, Mexico, December 5-7, 2012},
pages = {1--7},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ReConFig.2012.6416766},
doi = {10.1109/RECONFIG.2012.6416766},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/reconfig/NishitaniIAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NishitaniIAIKS12,
author = {Yuki Nishitani and
Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {Evaluation of fault tolerant technique based on homogeneous {FPGA}
architecture},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {225--230},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6379034},
doi = {10.1109/VLSI-SOC.2012.6379034},
timestamp = {Tue, 06 Sep 2022 16:02:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NishitaniIAIKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esl/ZhaoIAIS11,
author = {Qian Zhao and
Yoshihiro Ichinomiya and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable
Systems},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {3},
number = {3},
pages = {89--92},
year = {2011},
url = {https://doi.org/10.1109/LES.2011.2167213},
doi = {10.1109/LES.2011.2167213},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/ZhaoIAIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/IidaKIAISIS11,
author = {Masahiro Iida and
Masahiro Koga and
Kazuki Inoue and
Motoki Amagasaki and
Yoshinobu Ichida and
Mitsuro Saji and
Jun Iida and
Toshinori Sueyoshi},
title = {A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells},
journal = {{IEICE} Trans. Electron.},
volume = {94-C},
number = {4},
pages = {548--556},
year = {2011},
url = {https://doi.org/10.1587/transele.E94.C.548},
doi = {10.1587/TRANSELE.E94.C.548},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/IidaKIAISIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jnit/IchinomiyaAIKS11,
author = {Yoshihiro Ichinomiya and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Improving the Soft-error Tolerability of a Soft-core Processor on},
journal = {J. Next Gener. Inf. Technol.},
volume = {2},
number = {3},
pages = {35--48},
year = {2011},
url = {https://doi.org/10.4156/jnit.vol2.issue3.3},
doi = {10.4156/JNIT.VOL2.ISSUE3.3},
timestamp = {Wed, 18 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jnit/IchinomiyaAIKS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SawadaKAIS11,
author = {Hiroomi Sawada and
Morihiro Kuga and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Parallelization of the channel width search for {FPGA} routing},
journal = {{SIGARCH} Comput. Archit. News},
volume = {39},
number = {4},
pages = {82--85},
year = {2011},
url = {https://doi.org/10.1145/2082156.2082177},
doi = {10.1145/2082156.2082177},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/SawadaKAIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/3dic/ZhaoIAIS11,
author = {Qian Zhao and
Yusuke Iwai and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Mitsumasa Koyanagi and
Morihiro Kada},
title = {A novel reconfigurable logic device base on 3D stack technology},
booktitle = {2011 {IEEE} International 3D Systems Integration Conference (3DIC),
Osaka, Japan, January 31 - February 2, 2012},
pages = {1--4},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/3DIC.2012.6263022},
doi = {10.1109/3DIC.2012.6263022},
timestamp = {Wed, 16 Oct 2019 14:14:50 +0200},
biburl = {https://dblp.org/rec/conf/3dic/ZhaoIAIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/InoueYAIS11,
author = {Kazuki Inoue and
Hiroki Yosho and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {An Easily Testable Routing Architecture and Efficient Test Technique},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2011, September 5-7, Chania, Crete, Greece},
pages = {291--294},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/FPL.2011.59},
doi = {10.1109/FPL.2011.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/InoueYAIS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/IidaIAS11,
author = {Masahiro Iida and
Kazuki Inoue and
Motoki Amagasaki and
Toshinori Sueyoshi},
title = {An easily testable routing architecture of {FPGA}},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {106--109},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081661},
doi = {10.1109/VLSISOC.2011.6081661},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/IidaIAS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/InoueZOYAIS10,
author = {Kazuki Inoue and
Qian Zhao and
Yasuhiro Okamoto and
Hiroki Yosho and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable
{IP} Core},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {4},
number = {1},
pages = {5:1--5:24},
year = {2010},
url = {https://doi.org/10.1145/1857927.1857932},
doi = {10.1145/1857927.1857932},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/InoueZOYAIS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/IchinomiyaTAIKS10,
author = {Yoshihiro Ichinomiya and
Shiro Tanoue and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
editor = {Ron Sass and
Russell Tessier},
title = {Improving the Robustness of a Softcore Processor against SEUs by Using
{TMR} and Partial Reconfiguration},
booktitle = {18th {IEEE} Annual International Symposium on Field-Programmable Custom
Computing Machines, {FCCM} 2010, Charlotte, North Carolina, USA, 2-4
May 2010},
pages = {47--54},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FCCM.2010.16},
doi = {10.1109/FCCM.2010.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/IchinomiyaTAIKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/KogaIAISIS10,
author = {Masahiro Koga and
Masahiro Iida and
Motoki Amagasaki and
Yoshinobu Ichida and
Mitsuro Saji and
Jun Iida and
Toshinori Sueyoshi},
title = {First Prototype of a Genuine Power-Gatable Reconfigurable Logic Chip
with FeRAM Cells},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2010, August 31 2010 - September 2, 2010, Milano, Italy},
pages = {298--303},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FPL.2010.67},
doi = {10.1109/FPL.2010.67},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/KogaIAISIS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/OkamotoIAIS10,
author = {Yasuhiro Okamoto and
Yoshihiro Ichinomiya and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
title = {{COGRE:} {A} Configuration Memory Reduced Reconfigurable Logic Cell
Architecture for Area Minimization},
booktitle = {International Conference on Field Programmable Logic and Applications,
{FPL} 2010, August 31 2010 - September 2, 2010, Milano, Italy},
pages = {304--309},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/FPL.2010.68},
doi = {10.1109/FPL.2010.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/OkamotoIAIS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/ZhaoIOAIS10,
author = {Qian Zhao and
Yoshihiro Ichinomiya and
Yasuhiro Okamoto and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {A robust reconfigurable logic device based on less configuration memory
logic cell},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {162--169},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681775},
doi = {10.1109/FPT.2010.5681775},
timestamp = {Thu, 01 Feb 2018 14:20:39 +0100},
biburl = {https://dblp.org/rec/conf/fpt/ZhaoIOAIS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NishidaEAIKS10,
author = {Shoichi Nishida and
Jyunya Eto and
Motoki Amagasaki and
Masahiro Iida and
Morihiro Kuga and
Toshinori Sueyoshi},
title = {Power-aware {FPGA} routing fabrics and design tools},
booktitle = {18th {IEEE/IFIP} VLSI-SoC 2010, {IEEE/IFIP} {WG} 10.5 International
Conference on Very Large Scale Integration of System-on-Chip, Madrid,
Spain, 27-29 September 2010},
pages = {67--72},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/VLSISOC.2010.5642621},
doi = {10.1109/VLSISOC.2010.5642621},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NishidaEAIKS10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/InoueAIS09,
author = {Kazuki Inoue and
Motoki Amagasaki and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {J{\"{u}}rgen Becker and
Roger F. Woods and
Peter M. Athanas and
Fearghal Morgan},
title = {A Novel Local Interconnect Architecture for Variable Grain Logic Cell},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 5th
International Workshop, {ARC} 2009, Karlsruhe, Germany, March 16-18,
2009. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5453},
pages = {97--109},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-00641-8\_12},
doi = {10.1007/978-3-642-00641-8\_12},
timestamp = {Fri, 19 Jul 2019 13:02:47 +0200},
biburl = {https://dblp.org/rec/conf/arc/InoueAIS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/pdcat/NakanoIS09,
author = {Mitsutaka Nakano and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Improvement of Execution Efficiency on the {MX} Core},
booktitle = {2009 International Conference on Parallel and Distributed Computing,
Applications and Technologies, {PDCAT} 2009, Higashi Hiroshima, Japan,
8-11 December 2009},
pages = {420--425},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/PDCAT.2009.81},
doi = {10.1109/PDCAT.2009.81},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/pdcat/NakanoIS09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijrc/AmagasakiYKIS08,
author = {Motoki Amagasaki and
Ryoichi Yamaguchi and
Masahiro Koga and
Masahiro Iida and
Toshinori Sueyoshi},
title = {An Embedded Reconfigurable {IP} Core with Variable Grain Logic Cell
Architecture},
journal = {Int. J. Reconfigurable Comput.},
volume = {2008},
pages = {180216:1--180216:14},
year = {2008},
url = {https://doi.org/10.1155/2008/180216},
doi = {10.1155/2008/180216},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijrc/AmagasakiYKIS08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/ShinoharaMIS07,
author = {Hiroshi Shinohara and
Hideaki Monji and
Masahiro Iida and
Toshinori Sueyoshi},
title = {A Novel Technique to Design Energy-Efficient Contexts for Reconfigurable
Logic Devices},
journal = {{IEICE} Trans. Inf. Syst.},
volume = {90-D},
number = {12},
pages = {1986--1989},
year = {2007},
url = {https://doi.org/10.1093/ietisy/e90-d.12.1986},
doi = {10.1093/IETISY/E90-D.12.1986},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/ShinoharaMIS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/MatsuyamaANYIS07,
author = {Kazunori Matsuyama and
Motoki Amagasaki and
Hideaki Nakayama and
Ryoichi Yamaguchi and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Pedro C. Diniz and
Eduardo Marques and
Koen Bertels and
Marcio Merino Fernandes and
Jo{\~{a}}o M. P. Cardoso},
title = {Evaluating Variable-Grain Logic Cells Using Heterogeneous Technology
Mapping},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, Third
International Workshop, {ARC} 2007, Mangaratiba, Brazil, March 27-29,
2007},
series = {Lecture Notes in Computer Science},
volume = {4419},
pages = {142--154},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-71431-6\_14},
doi = {10.1007/978-3-540-71431-6\_14},
timestamp = {Tue, 14 May 2019 10:00:49 +0200},
biburl = {https://dblp.org/rec/conf/arc/MatsuyamaANYIS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ShinoharaMIS07,
author = {Hiroshi Shinohara and
Hideaki Monji and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Kenneth L. Pocek and
Duncan A. Buell},
title = {A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable
Logic},
booktitle = {{IEEE} Symposium on Field-Programmable Custom Computing Machines,
{FCCM} 2007, 23-25 April 2007, Napa, California, {USA}},
pages = {285--286},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/FCCM.2007.21},
doi = {10.1109/FCCM.2007.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ShinoharaMIS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fccm/ShinoharaMIS07a,
author = {Hiroshi Shinohara and
Hideaki Monji and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Kenneth L. Pocek and
Duncan A. Buell},
title = {A Novel Technique to Create Energy-Efficient Contexts for Reconfigurable
Logic},
booktitle = {{IEEE} Symposium on Field-Programmable Custom Computing Machines,
{FCCM} 2007, 23-25 April 2007, Napa, California, {USA}},
pages = {309--310},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/FCCM.2007.15},
doi = {10.1109/FCCM.2007.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fccm/ShinoharaMIS07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/AmagasakiYMIS07,
author = {Motoki Amagasaki and
Ryoichi Yamaguchi and
Kazunori Matsuyama and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Koen Bertels and
Walid A. Najjar and
Arjan J. van Genderen and
Stamatis Vassiliadis},
title = {A Variable Grain Logic Cell Architecture for Reconfigurable Logic
Cores},
booktitle = {{FPL} 2007, International Conference on Field Programmable Logic and
Applications, Amsterdam, The Netherlands, 27-29 August 2007},
pages = {550--553},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPL.2007.4380714},
doi = {10.1109/FPL.2007.4380714},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/fpl/AmagasakiYMIS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/SatouAMMYIS07,
author = {Yoshiaki Satou and
Motoki Amagasaki and
Hiroshi Miura and
Kazunori Matsuyama and
Ryoichi Yamaguchi and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Hideharu Amano and
Andy Ye and
Takeshi Ikenaga},
title = {An Embedded Reconfigurable Logic Core based on Variable Grain Logic
Cell Architecture},
booktitle = {2007 International Conference on Field-Programmable Technology, {ICFPT}
2007, Kitakyushu, Japan, December 12-14, 2007},
pages = {241--244},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/FPT.2007.4439256},
doi = {10.1109/FPT.2007.4439256},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/fpt/SatouAMMYIS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KobataIS06,
author = {Masaki Kobata and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Steven J. E. Wilton and
Andr{\'{e}} DeHon},
title = {Effective clustering technique to optimize routability of outer cluster
nets},
booktitle = {Proceedings of the {ACM/SIGDA} 14th International Symposium on Field
Programmable Gate Arrays, {FPGA} 2006, Monterey, California, USA,
February 22-24, 2006},
pages = {229},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1117201.1117247},
doi = {10.1145/1117201.1117247},
timestamp = {Tue, 06 Nov 2018 16:58:23 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KobataIS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/AmagasakiSMYNHIS06,
author = {Motoki Amagasaki and
Takurou Shimokawa and
Kazunori Matsuyama and
Ryoichi Yamaguchi and
Hideaki Nakayama and
Naoto Hamabe and
Masahiro Iida and
Toshinori Sueyoshi},
title = {Evaluation of Variable Grain Logic Cell Architecture for Reconfigurable
Device},
booktitle = {{IFIP} VLSI-SoC 2006, {IFIP} {WG} 10.5 International Conference on
Very Large Scale Integration of System-on-Chip, Nice, France, 16-18
October 2006},
pages = {198--203},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/VLSISOC.2006.313233},
doi = {10.1109/VLSISOC.2006.313233},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/AmagasakiSMYNHIS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/TsukiashiIS05,
author = {Hisashi Tsukiashi and
Masahiro Iida and
Toshinori Sueyoshi},
editor = {Tero Rissa and
Steven J. E. Wilton and
Philip Heng Wai Leong},
title = {Applying the Small-World Network to Routing Structure of FPGAs},
booktitle = {Proceedings of the 2005 International Conference on Field Programmable
Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
pages = {65--70},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/FPL.2005.1515700},
doi = {10.1109/FPL.2005.1515700},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpl/TsukiashiIS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieiceta/SueyoshiI02,
author = {Toshinori Sueyoshi and
Masahiro Iida},
title = {Configurable and Reconfigurable Computing for Digital Signal Processing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {85-A},
number = {3},
pages = {591--599},
year = {2002},
url = {http://search.ieice.org/bin/summary.php?id=e85-a\_3\_591},
timestamp = {Wed, 09 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieiceta/SueyoshiI02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-21 17:45 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
