BibTeX records: D. Heslinga

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@inproceedings{DBLP:conf/mtdt/DevoivreLJCFTVGBHVTRGPTGRBPNPDLHH02,
  author       = {Thierry Devoivre and
                  M. Lunenborg and
                  C. Julien and
                  J.{-}P. Carrere and
                  P. Ferreira and
                  W. J. Toren and
                  A. VandeGoor and
                  P. Gayet and
                  T. Berger and
                  O. Hinsinger and
                  P. Vannier and
                  Y. Trouiller and
                  Y. Rody and
                  P.{-}J. Goirand and
                  R. Palla and
                  I. Thomas and
                  F. Guyader and
                  David Roy and
                  B. Borot and
                  Nicolas Planes and
                  Sylvie Naudet and
                  F. Pico and
                  D. Duca and
                  F. Lalanne and
                  D. Heslinga and
                  M. Haond},
  title        = {Validated 90nm {CMOS} Technology Platform with Low-k Copper Interconnects
                  for Advanced System-on-Chip (SoC)},
  booktitle    = {10th {IEEE} International Workshop on Memory Technology, Design, and
                  Testing {(MTDT} 2002), 10-12 July 2002, Isle of Bendor, France},
  pages        = {157--162},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/MTDT.2002.1029778},
  doi          = {10.1109/MTDT.2002.1029778},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/mtdt/DevoivreLJCFTVGBHVTRGPTGRBPNPDLHH02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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