BibTeX records: Graham R. Hellestrand

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@inproceedings{DBLP:conf/syscon/Hellestrand13,
  author       = {Graham R. Hellestrand},
  title        = {Engineering safe autonomous mobile systems of systems using specification
                  (model) based systems architecture {\&} engineering},
  booktitle    = {{IEEE} International Systems Conference, SysCon 2013, Orlando, FL,
                  USA, April 15-18, 2013},
  pages        = {599--605},
  publisher    = {{IEEE}},
  year         = {2013},
  url          = {https://doi.org/10.1109/SysCon.2013.6549944},
  doi          = {10.1109/SYSCON.2013.6549944},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/syscon/Hellestrand13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/pieee/AbdallahFHKW10,
  author       = {Ahmed Abdallah and
                  Eric M. Feron and
                  Graham R. Hellestrand and
                  Philip J. Koopman Jr. and
                  Marilyn Wolf},
  title        = {Hardware/Software Codesign of Aerospace and Automotive Systems},
  journal      = {Proc. {IEEE}},
  volume       = {98},
  number       = {4},
  pages        = {584--602},
  year         = {2010},
  url          = {https://doi.org/10.1109/JPROC.2009.2036747},
  doi          = {10.1109/JPROC.2009.2036747},
  timestamp    = {Fri, 02 Oct 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/pieee/AbdallahFHKW10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dsd/AbdallahWH08,
  author       = {Ahmed Abdallah and
                  Wayne H. Wolf and
                  Graham R. Hellestrand},
  editor       = {Luca Fanucci},
  title        = {Using Empirical Science to Engineer Systems: Optimizing Cache for
                  Power and Performance},
  booktitle    = {11th Euromicro Conference on Digital System Design: Architectures,
                  Methods and Tools, {DSD} 2008, Parma, Italy, September 3-5, 2008},
  pages        = {325--333},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/DSD.2008.121},
  doi          = {10.1109/DSD.2008.121},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/dsd/AbdallahWH08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/wises/AbdallahWH08,
  author       = {Ahmed Abdallah and
                  Wayne H. Wolf and
                  Graham R. Hellestrand},
  editor       = {Markus Kucera and
                  Richard Roth and
                  Massimo Conti},
  title        = {Statistical characterization of execution time through simulation},
  booktitle    = {International Workshop on Intelligent Solutions in Embedded Systems,
                  {WISES} 2008, Regensburg, Germany, July 10-11, 2008},
  pages        = {1--13},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/WISES.2008.4623312},
  doi          = {10.1109/WISES.2008.4623312},
  timestamp    = {Wed, 16 Oct 2019 14:14:56 +0200},
  biburl       = {https://dblp.org/rec/conf/wises/AbdallahWH08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/computer/Hellestrand05,
  author       = {Graham R. Hellestrand},
  title        = {The Engineering of Supersystems},
  journal      = {Computer},
  volume       = {38},
  number       = {1},
  pages        = {103--105},
  year         = {2005},
  url          = {https://doi.org/10.1109/MC.2005.37},
  doi          = {10.1109/MC.2005.37},
  timestamp    = {Wed, 12 Aug 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/computer/Hellestrand05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/emsoft/Hellestrand05,
  author       = {Graham R. Hellestrand},
  editor       = {Wayne H. Wolf},
  title        = {Systems architecture: the empirical way: abstract architectures to
                  'optimal' systems},
  booktitle    = {{EMSOFT} 2005, September 18-22, 2005, Jersey City, NJ, USA, 5th {ACM}
                  International Conference On Embedded Software, Proceedings},
  pages        = {147--158},
  publisher    = {{ACM}},
  year         = {2005},
  url          = {https://doi.org/10.1145/1086228.1086257},
  doi          = {10.1145/1086228.1086257},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/emsoft/Hellestrand05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/Hellestrand99,
  author       = {Graham R. Hellestrand},
  title        = {Designing system on a chip products using systems engineering tools},
  booktitle    = {Proceedings of the 1999 International Symposium on Circuits and Systems,
                  {ISCAS} 1999, Orlando, Florida, USA, May 30 - June 2, 1999},
  pages        = {468--473},
  publisher    = {{IEEE}},
  year         = {1999},
  url          = {https://doi.org/10.1109/ISCAS.1999.780196},
  doi          = {10.1109/ISCAS.1999.780196},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/Hellestrand99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/CheungHK97,
  author       = {Tommy King{-}Yin Cheung and
                  Graham R. Hellestrand and
                  Prasert Kanthamanon},
  title        = {A transformational codesign methodology},
  booktitle    = {Proceedings of the {ASP-DAC} '97 Asia and South Pacific Design Automation
                  Conference, Nippon Convention Center, Chiba, Japan, January 28-31,
                  1997},
  pages        = {299--305},
  publisher    = {{IEEE}},
  year         = {1997},
  url          = {https://doi.org/10.1109/ASPDAC.1997.600162},
  doi          = {10.1109/ASPDAC.1997.600162},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/CheungHK97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsid/NagallaH97,
  author       = {Radhakrishna Nagalla and
                  Graham R. Hellestrand},
  title        = {A Visual Approach for Asynchronous Circuit Synthesis},
  booktitle    = {10th International Conference on {VLSI} Design {(VLSI} Design 1997),
                  4-7 January 1997, Hyderabad, India},
  pages        = {329--335},
  publisher    = {{IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/ICVD.1997.568099},
  doi          = {10.1109/ICVD.1997.568099},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/NagallaH97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/codes/CheungHK96,
  author       = {Tommy King{-}Yin Cheung and
                  Graham R. Hellestrand and
                  Prasert Kanthamanon},
  title        = {A Multi-Level Transformation Approach to {HW/SW} Codesign: {A} Case
                  Study},
  booktitle    = {Proceedings of the Forth International Workshop on Hardware/Software
                  Codesign, {CODES} 1996, Pittsburgh, PA, USA, March 18-20, 1996},
  pages        = {10--17},
  publisher    = {{IEEE} Computer Society},
  year         = {1996},
  url          = {https://doi.ieeecomputersociety.org/10.1109/HCS.1996.492221},
  doi          = {10.1109/HCS.1996.492221},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/codes/CheungHK96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/vlsid/NagallaH96,
  author       = {Radhakrishna Nagalla and
                  Graham R. Hellestrand},
  title        = {Elimination of Dynamic Hazards from Signal Transition Graphs},
  booktitle    = {9th International Conference on {VLSI} Design {(VLSI} Design 1996),
                  3-6 January 1996, Bangalore, India},
  pages        = {382--388},
  publisher    = {{IEEE} Computer Society},
  year         = {1996},
  url          = {https://doi.org/10.1109/ICVD.1996.489639},
  doi          = {10.1109/ICVD.1996.489639},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/vlsid/NagallaH96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/cg/DoggettH95,
  author       = {Michael C. Doggett and
                  Graham R. Hellestrand},
  title        = {A hardware architecture for video rate smooth shading of volume data},
  journal      = {Comput. Graph.},
  volume       = {19},
  number       = {5},
  pages        = {695--704},
  year         = {1995},
  url          = {https://doi.org/10.1016/0097-8493(95)00048-8},
  doi          = {10.1016/0097-8493(95)00048-8},
  timestamp    = {Wed, 19 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/cg/DoggettH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aspdac/ZamaniH95,
  author       = {Morteza Saheb Zamani and
                  Graham R. Hellestrand},
  editor       = {Isao Shirakawa},
  title        = {A neural network approach to the placement problem},
  booktitle    = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
                  Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
  publisher    = {{ACM}},
  year         = {1995},
  url          = {https://doi.org/10.1145/224818.224942},
  doi          = {10.1145/224818.224942},
  timestamp    = {Wed, 16 Oct 2019 14:14:52 +0200},
  biburl       = {https://dblp.org/rec/conf/aspdac/ZamaniH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/icnn/ZamaniH95,
  author       = {Morteza Saheb Zamani and
                  Graham R. Hellestrand},
  title        = {Placement with self-organising neural networks},
  booktitle    = {Proceedings of International Conference on Neural Networks (ICNN'95),
                  Perth, WA, Australia, November 27 - December 1, 1995},
  pages        = {2185--2189},
  publisher    = {{IEEE}},
  year         = {1995},
  url          = {https://doi.org/10.1109/ICNN.1995.487699},
  doi          = {10.1109/ICNN.1995.487699},
  timestamp    = {Thu, 29 Aug 2019 08:54:05 +0200},
  biburl       = {https://dblp.org/rec/conf/icnn/ZamaniH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/ZamaniH95,
  author       = {Morteza Saheb Zamani and
                  Graham R. Hellestrand},
  title        = {A Stepwise Refinement Algorithm for Integrated Floorplanning, Placement
                  and Routing of Hierarchical Designs},
  booktitle    = {1995 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  1995, Seattle, Washington, USA, April 30 - May 3, 1995},
  pages        = {49--52},
  publisher    = {{IEEE}},
  year         = {1995},
  url          = {https://doi.org/10.1109/ISCAS.1995.521448},
  doi          = {10.1109/ISCAS.1995.521448},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/ZamaniH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/DoggettH95,
  author       = {Michael C. Doggett and
                  Graham R. Hellestrand},
  title        = {A Hardware Architecture for Video Rate Shading of Volume Data},
  booktitle    = {1995 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  1995, Seattle, Washington, USA, April 30 - May 3, 1995},
  pages        = {433--436},
  publisher    = {{IEEE}},
  year         = {1995},
  url          = {https://doi.org/10.1109/ISCAS.1995.521543},
  doi          = {10.1109/ISCAS.1995.521543},
  timestamp    = {Fri, 26 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/DoggettH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iwann/ZamaniH95,
  author       = {Morteza Saheb Zamani and
                  Graham R. Hellestrand},
  editor       = {Jos{\'{e}} Mira and
                  Francisco Sandoval Hern{\'{a}}ndez},
  title        = {A New Neural Network Approach to the Floorplanning of Hierarchical
                  {VLSI} Designs},
  booktitle    = {From Natural to Artificial Neural Computation, International Workshop
                  on Artificial Neural Networks, {IWANN} '95, Malaga-Torremolinos, Spain,
                  June 7-9, 1995, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {930},
  pages        = {1128--1134},
  publisher    = {Springer},
  year         = {1995},
  url          = {https://doi.org/10.1007/3-540-59497-3\_294},
  doi          = {10.1007/3-540-59497-3\_294},
  timestamp    = {Tue, 14 May 2019 10:00:51 +0200},
  biburl       = {https://dblp.org/rec/conf/iwann/ZamaniH95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/fmsd/NagallaH94,
  author       = {Radhakrishna Nagalla and
                  Graham R. Hellestrand},
  title        = {Signal Transition Graph Constraints for Synthesis of Hazard-Free Asynchronous
                  Circuits with Unbounded-Gate Delays},
  journal      = {Formal Methods Syst. Des.},
  volume       = {5},
  number       = {3},
  pages        = {245--273},
  year         = {1994},
  url          = {https://doi.org/10.1007/BF01383833},
  doi          = {10.1007/BF01383833},
  timestamp    = {Fri, 13 Mar 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/fmsd/NagallaH94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/egh/DoggettH94,
  author       = {Michael C. Doggett and
                  Graham R. Hellestrand},
  editor       = {Wolfgang Stra{\ss}er},
  title        = {A hardware architecture for video rate smooth shading of Volume data},
  booktitle    = {{EGGH94:} Eurographics Workshop on Graphics Hardware 1994},
  pages        = {95--102},
  publisher    = {The Eurographics Association},
  year         = {1994},
  url          = {https://doi.org/10.2312/EGGH/EGGH94/095-102},
  doi          = {10.2312/EGGH/EGGH94/095-102},
  timestamp    = {Wed, 24 May 2017 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/egh/DoggettH94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iscas/FesharakiH94,
  author       = {Mehdi N. Fesharaki and
                  Graham R. Hellestrand},
  title        = {A Real-Time Edge Detection {ASIC} Design},
  booktitle    = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
                  1994, London, England, UK, May 30 - June 2, 1994},
  pages        = {81--84},
  publisher    = {{IEEE}},
  year         = {1994},
  url          = {https://doi.org/10.1109/ISCAS.1994.409108},
  doi          = {10.1109/ISCAS.1994.409108},
  timestamp    = {Wed, 16 Oct 2019 14:14:49 +0200},
  biburl       = {https://dblp.org/rec/conf/iscas/FesharakiH94.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/cg/BickerstaffH91,
  author       = {Mark A. Bickerstaff and
                  Graham R. Hellestrand},
  title        = {A highly parallel architecture for real time collision detection in
                  flight simulation},
  journal      = {Comput. Graph.},
  volume       = {15},
  number       = {3},
  pages        = {355--363},
  year         = {1991},
  url          = {https://doi.org/10.1016/0097-8493(91)90005-3},
  doi          = {10.1016/0097-8493(91)90005-3},
  timestamp    = {Wed, 19 Feb 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/cg/BickerstaffH91.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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