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ORCIDBibTeX records: Bah-Hwee Gwee
@article{DBLP:journals/expert/TeeCSLG24,
author = {Yee{-}Yang Tee and
Deruo Cheng and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee},
title = {Integrated Circuit Mask-Generative Adversarial Network for Circuit
Annotation With Targeted Data Augmentation},
journal = {{IEEE} Intell. Syst.},
volume = {39},
number = {1},
pages = {37--45},
year = {2024},
url = {https://doi.org/10.1109/MIS.2023.3306599},
doi = {10.1109/MIS.2023.3306599},
timestamp = {Sat, 16 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/expert/TeeCSLG24.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tai/HongLSG23,
author = {Xuenong Hong and
Tong Lin and
Yiqiong Shi and
Bah{-}Hwee Gwee},
title = {GraphClusNet: {A} Hierarchical Graph Neural Network for Recovered
Circuit Netlist Partitioning},
journal = {{IEEE} Trans. Artif. Intell.},
volume = {4},
number = {5},
pages = {1199--1213},
year = {2023},
url = {https://doi.org/10.1109/TAI.2022.3198930},
doi = {10.1109/TAI.2022.3198930},
timestamp = {Sat, 14 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tai/HongLSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/TeeHCCSLG23,
author = {Yee{-}Yang Tee and
Xuenong Hong and
Deruo Cheng and
Chye{-}Soon Chee and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee},
title = {Patch-Based Adversarial Training for Error-Aware Circuit Annotation
of Delayered {IC} Images},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {70},
number = {9},
pages = {3694--3698},
year = {2023},
url = {https://doi.org/10.1109/TCSII.2023.3265050},
doi = {10.1109/TCSII.2023.3265050},
timestamp = {Thu, 14 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/TeeHCCSLG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aicas/ChengSTSWWG23,
author = {Deruo Cheng and
Yiqiong Shi and
Yee{-}Yang Tee and
Jingsi Song and
Xue Wang and
Bihan Wen and
Bah{-}Hwee Gwee},
title = {Deep-learning-based X-ray {CT} Slice Analysis for Layout Verification
in Printed Circuit Boards},
booktitle = {5th {IEEE} International Conference on Artificial Intelligence Circuits
and Systems, {AICAS} 2023, Hangzhou, China, June 11-13, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AICAS57966.2023.10168608},
doi = {10.1109/AICAS57966.2023.10168608},
timestamp = {Mon, 24 Jul 2023 15:56:17 +0200},
biburl = {https://dblp.org/rec/conf/aicas/ChengSTSWWG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/HuangHLSG23,
author = {Erdong Huang and
Xuenong Hong and
Tong Lin and
Yiqiong Shi and
Bah{-}Hwee Gwee},
title = {{GRACER:} Graph-Based Standard Cell Recognition in {IC} Images for
Hardware Assurance},
booktitle = {49th Annual Conference of the {IEEE} Industrial Electronics Society,
{IECON} 2023, Singapore, October 16-19, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/IECON51785.2023.10312021},
doi = {10.1109/IECON51785.2023.10312021},
timestamp = {Sat, 25 Nov 2023 16:52:31 +0100},
biburl = {https://dblp.org/rec/conf/iecon/HuangHLSG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/0001SG23,
author = {Tong Lin and
Yiqiong Shi and
Bah{-}Hwee Gwee},
title = {{SEM2GDS:} {A} Deep-Learning Based Framework To Detect Malicious Modifications
In {IC} Layout},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181578},
doi = {10.1109/ISCAS46773.2023.10181578},
timestamp = {Mon, 31 Jul 2023 09:04:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/0001SG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenTG0RL23,
author = {Yongming Chen and
Yuzhou Tong and
Bah{-}Hwee Gwee and
Qi Cao and
Sirajudeen Gulam Razul and
Zhiping Lin},
title = {Real-time Traffic Classification in Encrypted Wireless Communication
Network},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181886},
doi = {10.1109/ISCAS46773.2023.10181886},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenTG0RL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LeeATXGC23,
author = {Jinhen Lee and
Victor Adrian and
Sun{-}Yang Tay and
Yanshan Xie and
Bah{-}Hwee Gwee and
Joseph Chang},
title = {A 3D-Printed Fourth-Order Stacked Filter for Integrated {DC-DC} Converters},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10182210},
doi = {10.1109/ISCAS46773.2023.10182210},
timestamp = {Mon, 31 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LeeATXGC23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NgCWKCLG23,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Si Wu and
Nay Aung Kyaw and
Kwen{-}Siong Chong and
Zhiping Lin and
Bah{-}Hwee Gwee},
title = {Improving FPGA-based Async-logic {AES} Accelerator with the Integration
of Sync-logic Block RAMs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181344},
doi = {10.1109/ISCAS46773.2023.10181344},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/NgCWKCLG23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/Zhou0HCGL23,
author = {Zixiang Zhou and
Lei Sun and
Hangcheng Han and
Juncheng Chen and
Bah{-}Hwee Gwee and
Zhiping Lin},
title = {A Residual-Remainder Coupled Unlimited Sampling Framework for High
Dynamic Range Signal Conversion},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181587},
doi = {10.1109/ISCAS46773.2023.10181587},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/Zhou0HCGL23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/ChengSLGT22,
author = {Deruo Cheng and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee and
Kar{-}Ann Toh},
title = {Delayered {IC} image analysis with template-based Tanimoto Convolution
and Morphological Decision},
journal = {{IET} Circuits Devices Syst.},
volume = {16},
number = {2},
pages = {169--177},
year = {2022},
url = {https://doi.org/10.1049/cds2.12093},
doi = {10.1049/CDS2.12093},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cds/ChengSLGT22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NgCCCG22,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Kwen{-}Siong Chong and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {A Highly Secure FPGA-Based Dual-Hiding Asynchronous-Logic {AES} Accelerator
Against Side-Channel Attacks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {30},
number = {9},
pages = {1144--1157},
year = {2022},
url = {https://doi.org/10.1109/TVLSI.2022.3175180},
doi = {10.1109/TVLSI.2022.3175180},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/NgCCCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asianhost/ChenNKZCLG22,
author = {Juncheng Chen and
Jun{-}Sheng Ng and
Nay Aung Kyaw and
Zhili Zou and
Kwen{-}Siong Chong and
Zhiping Lin and
Bah{-}Hwee Gwee},
title = {Incremental Linear Regression Attack},
booktitle = {Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2022,
Singapore, Singapore, December 14-16, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/AsianHOST56390.2022.10022167},
doi = {10.1109/ASIANHOST56390.2022.10022167},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asianhost/ChenNKZCLG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenNKLCLCG22,
author = {Juncheng Chen and
Jun{-}Sheng Ng and
Nay Aung Kyaw and
Ne Kyaw Zwa Lwin and
Kwen{-}Siong Chong and
Zhiping Lin and
Joseph Sylvester Chang and
Bah{-}Hwee Gwee},
title = {Non-profiling based Correlation Optimization Deep Learning Analysis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2246--2250},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937217},
doi = {10.1109/ISCAS48785.2022.9937217},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenNKLCLCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NgCKLCCG22,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Nay Aung Kyaw and
Ne Kyaw Zwa Lwin and
Kwen{-}Siong Chong and
Joseph Chang and
Bah{-}Hwee Gwee},
title = {An Asynchronous-Logic Masked Advanced Encryption Standard {(AES)}
Accelerator and its Side-Channel Attack Evaluations},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {2256--2260},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937684},
doi = {10.1109/ISCAS48785.2022.9937684},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/NgCKLCCG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TayACLG22,
author = {Sun{-}Yang Tay and
Victor Adrian and
Joseph Chang and
Jinhen Lee and
Bah{-}Hwee Gwee},
title = {A Versatile and Accurate Vector-Based Method for Modeling and Analyzing
Planar Air-Core Inductors},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {3063--3067},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937970},
doi = {10.1109/ISCAS48785.2022.9937970},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/TayACLG22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2209-13479,
author = {Yee{-}Yang Tee and
Deruo Cheng and
Chye{-}Soon Chee and
Tong Lin and
Yiqiong Shi and
Bah{-}Hwee Gwee},
title = {Unsupervised Domain Adaptation with Histogram-gated Image Translation
for Delayered {IC} Image Analysis},
journal = {CoRR},
volume = {abs/2209.13479},
year = {2022},
url = {https://doi.org/10.48550/arXiv.2209.13479},
doi = {10.48550/ARXIV.2209.13479},
eprinttype = {arXiv},
eprint = {2209.13479},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2209-13479.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChongNCLKHCG21,
author = {Kwen{-}Siong Chong and
Jun{-}Sheng Ng and
Juncheng Chen and
Ne Kyaw Zwa Lwin and
Nay Aung Kyaw and
Weng{-}Geng Ho and
Joseph Sylvester Chang and
Bah{-}Hwee Gwee},
title = {Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic
{AES:} Design, Countermeasures and Evaluation},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {11},
number = {2},
pages = {343--356},
year = {2021},
url = {https://doi.org/10.1109/JETCAS.2021.3077887},
doi = {10.1109/JETCAS.2021.3077887},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/ChongNCLKHCG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcasII/HoCKG21,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Tony Tae{-}Hyoung Kim and
Bah{-}Hwee Gwee},
title = {A Power-Aware Toggling-Frequency Actuator in Data-Toggling {SRAM}
for Secure Data Protection},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {68},
number = {6},
pages = {2122--2126},
year = {2021},
url = {https://doi.org/10.1109/TCSII.2020.3047106},
doi = {10.1109/TCSII.2020.3047106},
timestamp = {Tue, 15 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcasII/HoCKG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/ChenNCLG21,
author = {Juncheng Chen and
Jun{-}Sheng Ng and
Kwen{-}Siong Chong and
Zhiping Lin and
Bah{-}Hwee Gwee},
title = {A Novel Normalized Variance-Based Differential Power Analysis Against
Masking Countermeasures},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {16},
pages = {3767--3779},
year = {2021},
url = {https://doi.org/10.1109/TIFS.2021.3093783},
doi = {10.1109/TIFS.2021.3093783},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/ChenNCLG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icip/HuangCYLSYGW21,
author = {Ling Huang and
Deruo Cheng and
Xulei Yang and
Tong Lin and
Yiqiong Shi and
Kaiyi Yang and
Bah{-}Hwee Gwee and
Bihan Wen},
title = {Joint Anomaly Detection and Inpainting for Microscopy Images Via Deep
Self-Supervised Learning},
booktitle = {2021 {IEEE} International Conference on Image Processing, {ICIP} 2021,
Anchorage, AK, USA, September 19-22, 2021},
pages = {3497--3501},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ICIP42928.2021.9506454},
doi = {10.1109/ICIP42928.2021.9506454},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icip/HuangCYLSYGW21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenNKLHCLCG21,
author = {Juncheng Chen and
Jun{-}Sheng Ng and
Nay Aung Kyaw and
Ne Kyaw Zwa Lwin and
Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Zhiping Lin and
Joseph Sylvester Chang and
Bah{-}Hwee Gwee},
title = {Normalized Differential Power Analysis - for Ghost Peaks Mitigation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2021,
Daegu, South Korea, May 22-28, 2021},
pages = {1--5},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/ISCAS51556.2021.9401487},
doi = {10.1109/ISCAS51556.2021.9401487},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenNKLHCLCG21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HoNKLCG20,
author = {Weng{-}Geng Ho and
Chuan{-}Seng Ng and
Nay Aung Kyaw and
Ne Kyaw Zwa Lwin and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {High Efficiency Early-Complete Brute Force Elimination Method for
Security Analysis of Camouflage {IC}},
booktitle = {2020 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2020, Ha Long, Vietnam, December 8-10, 2020},
pages = {161--164},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/APCCAS50809.2020.9301666},
doi = {10.1109/APCCAS50809.2020.9301666},
timestamp = {Wed, 27 Jan 2021 14:35:03 +0100},
biburl = {https://dblp.org/rec/conf/apccas/HoNKLCG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/Gwee20,
author = {Bah{-}Hwee Gwee},
title = {Hardware Attack and Assurance with Machine Learning: {A} Security
Threat to Circuits and Systems},
booktitle = {2020 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2020, Ha Long, Vietnam, December 8-10, 2020},
pages = {i},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/APCCAS50809.2020.9301658},
doi = {10.1109/APCCAS50809.2020.9301658},
timestamp = {Wed, 27 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/apccas/Gwee20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoCKG20,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Tony Tae{-}Hyoung Kim and
Bah{-}Hwee Gwee},
title = {A Secure Data-Toggling {SRAM} for Confidential Data Protection},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180698},
doi = {10.1109/ISCAS45731.2020.9180698},
timestamp = {Mon, 18 Jan 2021 08:38:59 +0100},
biburl = {https://dblp.org/rec/conf/iscas/HoCKG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoLKNCCGC20,
author = {Weng{-}Geng Ho and
Ne Kyaw Zwa Lwin and
Nay Aung Kyaw and
Jun{-}Sheng Ng and
Juncheng Chen and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling
for Multicore Cryptographic Applications},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180849},
doi = {10.1109/ISCAS45731.2020.9180849},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/HoLKNCCGC20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/NgCKLHCG20,
author = {Jun{-}Sheng Ng and
Juncheng Chen and
Nay Aung Kyaw and
Ne Kyaw Zwa Lwin and
Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {A Highly Efficient Power Model for Correlation Power Analysis {(CPA)}
of Pipelined Advanced Encryption Standard {(AES)}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2020,
Sevilla, Spain, October 10-21, 2020},
pages = {1--5},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISCAS45731.2020.9180778},
doi = {10.1109/ISCAS45731.2020.9180778},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/NgCKLHCG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HoPLCG20,
author = {Weng{-}Geng Ho and
Ali Akbar Pammu and
Ne Kyaw Zwa Lwin and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {High Throughput and Secure Authentication-Encryption on Asynchronous
Multicore Processor for Edge Computing IoT Applications},
booktitle = {International SoC Design Conference, {ISOCC} 2020, Yeosu, South Korea,
October 21-24, 2020},
pages = {173--174},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ISOCC50952.2020.9333008},
doi = {10.1109/ISOCC50952.2020.9333008},
timestamp = {Fri, 12 Feb 2021 11:57:12 +0100},
biburl = {https://dblp.org/rec/conf/isocc/HoPLCG20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/expert/ChengSGTL19,
author = {Deruo Cheng and
Yiqiong Shi and
Bah{-}Hwee Gwee and
Kar{-}Ann Toh and
Tong Lin},
title = {A Hierarchical Multiclassifier System for Automated Analysis of Delayered
{IC} Images},
journal = {{IEEE} Intell. Syst.},
volume = {34},
number = {2},
pages = {36--43},
year = {2019},
url = {https://doi.org/10.1109/MIS.2018.2886669},
doi = {10.1109/MIS.2018.2886669},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/expert/ChengSGTL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/HoCKG19,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Tony Tae{-}Hyoung Kim and
Bah{-}Hwee Gwee},
title = {A Secure Data-Toggling {SRAM} for Confidential Data Protection},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {66-I},
number = {11},
pages = {4186--4199},
year = {2019},
url = {https://doi.org/10.1109/TCSI.2019.2927363},
doi = {10.1109/TCSI.2019.2927363},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/HoCKG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/PammuCWG19,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Yi Wang and
Bah{-}Hwee Gwee},
title = {A Highly Efficient Side Channel Attack with Profiling through Relevance-Learning
on Physical Leakage Information},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {16},
number = {3},
pages = {376--387},
year = {2019},
url = {https://doi.org/10.1109/TDSC.2018.2864727},
doi = {10.1109/TDSC.2018.2864727},
timestamp = {Fri, 22 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tdsc/PammuCWG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tifs/PammuHLCG19,
author = {Ali Akbar Pammu and
Weng{-}Geng Ho and
Ne Kyaw Zwa Lwin and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {A High Throughput and Secure Authentication-Encryption {AES-CCM} Algorithm
on Asynchronous Multicore Processor},
journal = {{IEEE} Trans. Inf. Forensics Secur.},
volume = {14},
number = {4},
pages = {1023--1036},
year = {2019},
url = {https://doi.org/10.1109/TIFS.2018.2869344},
doi = {10.1109/TIFS.2018.2869344},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tifs/PammuHLCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asianhost/ChongSLKHWZGC19,
author = {Kwen{-}Siong Chong and
Aparna Shreedhar and
Ne Kyaw Zwa Lwin and
Nay Aung Kyaw and
Weng{-}Geng Ho and
Chao Wang and
Jun Zhou and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic {AES} Accelerator
Based on Standard Library Cells},
booktitle = {Asian Hardware Oriented Security and Trust Symposium, AsianHOST 2019,
Xi'an, China, December 16-17, 2019},
pages = {1--7},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/AsianHOST47458.2019.9006690},
doi = {10.1109/ASIANHOST47458.2019.9006690},
timestamp = {Thu, 24 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/asianhost/ChongSLKHWZGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChengSLGT19,
author = {Deruo Cheng and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee and
Kar{-}Ann Toh},
title = {Global Template Projection and Matching Method for Training-Free Analysis
of Delayered {IC} Images},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702676},
doi = {10.1109/ISCAS.2019.8702676},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChengSLGT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ShreedharCLKNSC19,
author = {Aparna Shreedhar and
Kwen{-}Siong Chong and
Ne Kyaw Zwa Lwin and
Nay Aung Kyaw and
L. Nalangilli and
W. Shu and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {Low Gate-Count Ultra-Small Area Nano Advanced Encryption Standard
{(AES)} Design},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702450},
doi = {10.1109/ISCAS.2019.8702450},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ShreedharCLKNSC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/HoPNCG19,
author = {Weng{-}Geng Ho and
Ali Akbar Pammu and
Kyaw Zwa Lwin Ne and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Reconfigurable Routing Paths As Noise Generators Using NoC Platform
for Hardware Security Applications},
booktitle = {32nd {IEEE} International System-on-Chip Conference, {SOCC} 2019,
Singapore, September 3-6, 2019},
pages = {86--91},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/SOCC46988.2019.1570557958},
doi = {10.1109/SOCC46988.2019.1570557958},
timestamp = {Tue, 19 May 2020 13:56:11 +0200},
biburl = {https://dblp.org/rec/conf/socc/HoPNCG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KeerAGC18,
author = {Cui Keer and
Victor Adrian and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A Noise-Shaped Randomized Modulation for Switched-Mode {DC-DC} Converters},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {65-I},
number = {1},
pages = {394--405},
year = {2018},
url = {https://doi.org/10.1109/TCSI.2017.2719700},
doi = {10.1109/TCSI.2017.2719700},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/KeerAGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChengSLGT18,
author = {Deruo Cheng and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee and
Kar{-}Ann Toh},
title = {Hybrid K-Means Clustering and Support Vector Machine Method for via
and Metal Line Detections in Delayered {IC} Images},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {65-II},
number = {12},
pages = {1849--1853},
year = {2018},
url = {https://doi.org/10.1109/TCSII.2018.2827044},
doi = {10.1109/TCSII.2018.2827044},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/ChengSLGT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HoCNGC18,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Kyaw Zwa Lwin Ne and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Asynchronous-Logic {QDI} Quad-Rail Sense-Amplifier Half-Buffer Approach
for NoC Router Design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {196--200},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2750171},
doi = {10.1109/TVLSI.2017.2750171},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HoCNGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/HoZCG18,
author = {Weng{-}Geng Ho and
Zixian Zheng and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {A Comparative Analysis of 65nm {CMOS} {SRAM} and Commercial SRAMs
in Security Vulnerability Evaluation},
booktitle = {23rd {IEEE} International Conference on Digital Signal Processing,
{DSP} 2018, Shanghai, China, November 19-21, 2018},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICDSP.2018.8631874},
doi = {10.1109/ICDSP.2018.8631874},
timestamp = {Mon, 31 Oct 2022 09:05:23 +0100},
biburl = {https://dblp.org/rec/conf/icdsp/HoZCG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icdsp/HongCSLG18,
author = {Xuenong Hong and
Deruo Cheng and
Yiqiong Shi and
Tong Lin and
Bah{-}Hwee Gwee},
title = {Deep Learning for Automatic {IC} Image Analysis},
booktitle = {23rd {IEEE} International Conference on Digital Signal Processing,
{DSP} 2018, Shanghai, China, November 19-21, 2018},
pages = {1--5},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICDSP.2018.8631555},
doi = {10.1109/ICDSP.2018.8631555},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icdsp/HongCSLG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChongHLGC17,
author = {Kwen{-}Siong Chong and
Weng{-}Geng Ho and
Tong Lin and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Sense Amplifier Half-Buffer {(SAHB)} {A} Low-Power High-Performance
Asynchronous Logic {QDI} Cell Template},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {2},
pages = {402--415},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2016.2583118},
doi = {10.1109/TVLSI.2016.2583118},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChongHLGC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LimHCG17,
author = {James Lim and
Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {DPA-resistant {QDI} dual-rail {AES} S-Box based on power-balanced
weak-conditioned half-buffer},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050749},
doi = {10.1109/ISCAS.2017.8050749},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LimHCG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiuAGC17,
author = {Qianqian Liu and
Victor Adrian and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A class-E {RF} power amplifier with a novel matching network for high-efficiency
dynamic load modulation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050498},
doi = {10.1109/ISCAS.2017.8050498},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiuAGC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PammuCG17,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Highly secured state-shift local clock circuit to countermeasure against
side channel attack},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2017,
Baltimore, MD, USA, May 28-31, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISCAS.2017.8050845},
doi = {10.1109/ISCAS.2017.8050845},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/PammuCG17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/KeerASGC17,
author = {Cui Keer and
Victor Adrian and
Yin Sun and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A low-harmonics low-noise randomized modulation scheme for multi-phase
{DC-DC} converters},
booktitle = {15th {IEEE} International New Circuits and Systems Conference, {NEWCAS}
2017, Strasbourg, France, June 25-28, 2017},
pages = {165--168},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/NEWCAS.2017.8010131},
doi = {10.1109/NEWCAS.2017.8010131},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/newcas/KeerASGC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/PammuCLHLG16,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Ne Kyaw Zwa Lwin and
Weng{-}Geng Ho and
Nan Liu and
Bah{-}Hwee Gwee},
title = {Success rate model for fully {AES-128} in correlation power analysis},
booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2016, Jeju, South Korea, October 25-28, 2016},
pages = {115--118},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/APCCAS.2016.7803910},
doi = {10.1109/APCCAS.2016.7803910},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/PammuCLHLG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/PammuCHG16,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Weng{-}Geng Ho and
Bah{-}Hwee Gwee},
title = {Interceptive side channel attack on {AES-128} wireless communications
for IoT applications},
booktitle = {2016 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2016, Jeju, South Korea, October 25-28, 2016},
pages = {650--653},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/APCCAS.2016.7804081},
doi = {10.1109/APCCAS.2016.7804081},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/PammuCHG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LiuCHGC16,
author = {Nan Liu and
Kwen{-}Siong Chong and
Weng{-}Geng Ho and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Low normalized energy derivation asynchronous circuit synthesis flow
through fork-join slack matching for cryptographic applications},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {850--853},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459427/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LiuCHGC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoNSCKG16,
author = {Weng{-}Geng Ho and
Kyaw Zwa Lwin Ne and
N. Prashanth Srinivas and
Kwen{-}Siong Chong and
Tony Tae{-}Hyoung Kim and
Bah{-}Hwee Gwee},
title = {Area-efficient and low stand-by power 1k-byte transmission-gate-based
non-imprinting high-speed erase {(TNIHE)} {SRAM}},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {698--701},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7527336},
doi = {10.1109/ISCAS.2016.7527336},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoNSCKG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoLNCGC16,
author = {Weng{-}Geng Ho and
Nan Liu and
Kyaw Zwa Lwin Ne and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {High performance low overhead template-based Cell-Interleave Pipeline
{(TCIP)} for asynchronous-logic {QDI} circuits},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2016,
Montr{\'{e}}al, QC, Canada, May 22-25, 2016},
pages = {1762--1765},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISCAS.2016.7538909},
doi = {10.1109/ISCAS.2016.7538909},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoLNCGC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/HoPLNCG16,
author = {Weng{-}Geng Ho and
Ali Akbar Pammu and
Nan Liu and
Kyaw Zwa Lwin Ne and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Security analysis of asynchronous-logic {QDI} cell approach for differential
power analysis attack},
booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
December 12-14, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISICIR.2016.7829712},
doi = {10.1109/ISICIR.2016.7829712},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/HoPLNCG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/LiuAGC16,
author = {Qianqian Liu and
Victor Adrian and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A high-efficiency Class-E polar power-amplifier with a novel digitally-controlled
output matching network},
booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
December 12-14, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISICIR.2016.7829692},
doi = {10.1109/ISICIR.2016.7829692},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/LiuAGC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/PammuCG16,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Highly secured arithmetic hiding based S-Box on {AES-128} implementation},
booktitle = {International Symposium on Integrated Circuits, {ISIC} 2016, Singapore,
December 12-14, 2016},
pages = {1--4},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISICIR.2016.7829736},
doi = {10.1109/ISICIR.2016.7829736},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/PammuCG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nas/PammuCG16,
author = {Ali Akbar Pammu and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Secured Low Power Overhead Compensator Look-Up-Table {(LUT)} Substitution
Box (S-Box) Architecture},
booktitle = {{IEEE} International Conference on Networking, Architecture and Storage
(NAS), Long Beach, CA, USA, August 8-10, 2016},
pages = {1--7},
publisher = {{IEEE} Computer Society},
year = {2016},
url = {https://doi.org/10.1109/NAS.2016.7549420},
doi = {10.1109/NAS.2016.7549420},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/nas/PammuCG16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/HoCGC15,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit
arithmetic and logic unit based on autonomous signal-validity half-buffer},
journal = {{IET} Circuits Devices Syst.},
volume = {9},
number = {4},
pages = {309--318},
year = {2015},
url = {https://doi.org/10.1049/iet-cds.2014.0103},
doi = {10.1049/IET-CDS.2014.0103},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/HoCGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/YinGLKRS15,
author = {Hongxu Yin and
Bah{-}Hwee Gwee and
Zhiping Lin and
Achanna Anil Kumar and
Sirajudeen Gulam Razul and
Chong Meng Samson See},
title = {Novel real-time system design for floating-point sub-Nyquist multi-coset
signal blind reconstruction},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {954--957},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7168793},
doi = {10.1109/ISCAS.2015.7168793},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/YinGLKRS15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoCLGC15,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Ne Kyaw Zwa Lwin and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {High robustness energy- and area-efficient dynamic-voltage-scaling
4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {1913--1916},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169046},
doi = {10.1109/ISCAS.2015.7169046},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoCLGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhouCLGC15,
author = {Rong Zhou and
Kwen{-}Siong Chong and
Tong Lin and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A single-VDD half-clock-tolerant fine-grained dynamic voltage scaling
pipeline},
booktitle = {2015 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2015, Lisbon, Portugal, May 24-27, 2015},
pages = {2589--2592},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ISCAS.2015.7169215},
doi = {10.1109/ISCAS.2015.7169215},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ZhouCLGC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cssp/ChenCG14,
author = {Junchao Chen and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee},
title = {Ultra-Low Power Read-Decoupled SRAMs with Ultra-Low Write-Bitline
Voltage Swing},
journal = {Circuits Syst. Signal Process.},
volume = {33},
number = {10},
pages = {3317--3329},
year = {2014},
url = {https://doi.org/10.1007/s00034-014-9791-8},
doi = {10.1007/S00034-014-9791-8},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cssp/ChenCG14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouCGC14,
author = {Rong Zhou and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A Low Overhead Quasi-Delay-Insensitive {(QDI)} Asynchronous Data Path
Synthesis Based on Microcell-Interleaving Genetic Algorithm {(MIGA)}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {33},
number = {7},
pages = {989--1002},
year = {2014},
url = {https://doi.org/10.1109/TCAD.2014.2309859},
doi = {10.1109/TCAD.2014.2309859},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhouCGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apccas/HoCGC14,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Low delay-variation sub-/near-threshold asynchronous-to-synchronous
interface controller for {GALS} Network-on-Chips},
booktitle = {2014 {IEEE} Asia Pacific Conference on Circuits and Systems, {APCCAS}
2014, Ishigaki, Japan, November 17-20, 2014},
pages = {5--8},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/APCCAS.2014.7032705},
doi = {10.1109/APCCAS.2014.7032705},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/apccas/HoCGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ZhouCGCH14,
author = {Rong Zhou and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang and
Weng{-}Geng Ho},
title = {Synthesis of asynchronous {QDI} circuits using synchronous coding
specifications},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {153--156},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865088},
doi = {10.1109/ISCAS.2014.6865088},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ZhouCGCH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AdrianKGC14,
author = {Victor Adrian and
Cui Keer and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A Randomized Modulation scheme for filterless digital Class {D} audio
amplifiers},
booktitle = {{IEEE} International Symposium on Circuits and Systemss, {ISCAS} 2014,
Melbourne, Victoria, Australia, June 1-5, 2014},
pages = {774--777},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISCAS.2014.6865250},
doi = {10.1109/ISCAS.2014.6865250},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AdrianKGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/HoCGCL14,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang and
Ne Kyaw Zwa Lwin},
title = {A dynamic-voltage-scaling 1kbyte{\texttimes}8-bit non-imprinting Master-Slave
{SRAM} with high speed erase for low-power operation},
booktitle = {2014 International Symposium on Integrated Circuits (ISIC), Singapore,
December 10-12, 2014},
pages = {320--323},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISICIR.2014.7029479},
doi = {10.1109/ISICIR.2014.7029479},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/HoCGCL14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/NashitAKMGC14,
author = {Salma Nashit and
Victor Adrian and
Cui Keer and
Quoc{-}An Mai and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A self-oscillating class {D} audio amplifier with dual voltage and
current feedback},
booktitle = {2014 International Symposium on Integrated Circuits (ISIC), Singapore,
December 10-12, 2014},
pages = {480--483},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISICIR.2014.7029507},
doi = {10.1109/ISICIR.2014.7029507},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/NashitAKMGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isicir/NgSAGC14,
author = {Tian{-}Shun Ng and
Yin Sun and
Victor Adrian and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Design of an output stage for high switching frequency {DC-DC} converters},
booktitle = {2014 International Symposium on Integrated Circuits (ISIC), Singapore,
December 10-12, 2014},
pages = {488--491},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ISICIR.2014.7029505},
doi = {10.1109/ISICIR.2014.7029505},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isicir/NgSAGC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChangCGC13,
author = {Kok{-}Leong Chang and
Joseph S. Chang and
Bah{-}Hwee Gwee and
Kwen{-}Siong Chong},
title = {Synchronous-Logic and Asynchronous-Logic 8051 Microcontroller Cores
for Realizing the Internet of Things: {A} Comparative Study on Dynamic
Voltage Scaling and Variation Effects},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {3},
number = {1},
pages = {23--34},
year = {2013},
url = {https://doi.org/10.1109/JETCAS.2013.2243031},
doi = {10.1109/JETCAS.2013.2243031},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/ChangCGC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/LinCCG13,
author = {Tong Lin and
Kwen{-}Siong Chong and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {An Ultra-Low Power Asynchronous-Logic In-Situ Self-Adaptive V\({}_{\mbox{DD}}\)
System for Wireless Sensor Networks},
journal = {{IEEE} J. Solid State Circuits},
volume = {48},
number = {2},
pages = {573--586},
year = {2013},
url = {https://doi.org/10.1109/JSSC.2012.2223971},
doi = {10.1109/JSSC.2012.2223971},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jssc/LinCCG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoCGC13,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Low power sub-threshold asynchronous {QDI} Static Logic Transistor-level
Implementation {(SLTI)} 32-bit {ALU}},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {353--356},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6571853},
doi = {10.1109/ISCAS.2013.6571853},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoCGC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangLHCGC13,
author = {Kok{-}Leong Chang and
Tong Lin and
Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A dual-core 8051 microcontroller system based on synchronous-logic
and asynchronous-logic},
booktitle = {2013 {IEEE} International Symposium on Circuits and Systems (ISCAS2013),
Beijing, China, May 19-23, 2013},
pages = {3022--3025},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISCAS.2013.6572515},
doi = {10.1109/ISCAS.2013.6572515},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangLHCGC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/newcas/ShiG13,
author = {Yiqiong Shi and
Bah{-}Hwee Gwee},
title = {Designing globally-asynchronous-locally-system from multi-rate Simulink
model},
booktitle = {{IEEE} 11th International New Circuits and Systems Conference, {NEWCAS}
2013, Paris, France, June 16-19, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/NEWCAS.2013.6573565},
doi = {10.1109/NEWCAS.2013.6573565},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/newcas/ShiG13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChongCGC12,
author = {Kwen{-}Siong Chong and
Kok{-}Leong Chang and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous {(GALS)}
Acoustic Digital Signal Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {47},
number = {3},
pages = {769--780},
year = {2012},
url = {https://doi.org/10.1109/JSSC.2011.2181678},
doi = {10.1109/JSSC.2011.2181678},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChongCGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoCLGC12,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Tong Lin and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Energy-delay efficient asynchronous-logic 16{\texttimes}16-bit pipelined
multiplier based on Sense Amplifier-Based Pass Transistor Logic},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {492--495},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6272073},
doi = {10.1109/ISCAS.2012.6272073},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoCLGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangLHCGC12,
author = {Kok{-}Leong Chang and
Tong Lin and
Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {A comparative study on asynchronous Quasi-Delay-Insensitive templates},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1819--1822},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271621},
doi = {10.1109/ISCAS.2012.6271621},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangLHCGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenCGC12,
author = {Junchao Chen and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {An Ultra-Dynamic Voltage Scalable {(U-DVS)} 10T {SRAM} with bit-interleaving
capability},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {1835--1838},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6271625},
doi = {10.1109/ISCAS.2012.6271625},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenCGC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscit/ShiGRPT12,
author = {Yiqiong Shi and
Bah{-}Hwee Gwee and
Ye Ren and
Thet Khaing Phone and
Chan Wai Ting},
title = {Extracting functional modules from flattened gate-level netlist},
booktitle = {International Symposium on Communications and Information Technologies,
{ISCIT} 2012, Gold Coast, Australia, October 2-5, 2012},
pages = {538--543},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCIT.2012.6380958},
doi = {10.1109/ISCIT.2012.6380958},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscit/ShiGRPT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/ShiGC11,
author = {Yiqiong Shi and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Asynchronous {DSP} for low-power energy-efficient embedded systems},
journal = {Microprocess. Microsystems},
volume = {35},
number = {3},
pages = {318--328},
year = {2011},
url = {https://doi.org/10.1016/j.micpro.2011.02.001},
doi = {10.1016/J.MICPRO.2011.02.001},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mam/ShiGC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LawGC11,
author = {Chong{-}Fatt Law and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Modeling and Synthesis of Asynchronous Pipelines},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {4},
pages = {682--695},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2039501},
doi = {10.1109/TVLSI.2009.2039501},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LawGC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChenCGC11,
author = {Junchao Chen and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A low-power dual-rail inputs write method for bit-interleaved memory
cells},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {325--328},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5937568},
doi = {10.1109/ISCAS.2011.5937568},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChenCGC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/HoCGCSC11,
author = {Weng{-}Geng Ho and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang and
Yin Sun and
Kok{-}Leong Chang},
title = {Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor
Logic with high speed and low power operation},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2011), May
15-19 2011, Rio de Janeiro, Brazil},
pages = {1936--1939},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISCAS.2011.5937968},
doi = {10.1109/ISCAS.2011.5937968},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/HoCGCSC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/AdrianCG10,
author = {Victor Adrian and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {A Randomized Wrapped-Around Pulse Position Modulation Scheme for {DC-DC}
Converters},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {57-I},
number = {9},
pages = {2320--2333},
year = {2010},
url = {https://doi.org/10.1109/TCSI.2010.2043997},
doi = {10.1109/TCSI.2010.2043997},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/AdrianCG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ShiTGR10,
author = {Yiqiong Shi and
Chan Wai Ting and
Bah{-}Hwee Gwee and
Ye Ren},
title = {A highly efficient method for extracting FSMs from flattened gate-level
netlist},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2010), May
30 - June 2, 2010, Paris, France},
pages = {2610--2613},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ISCAS.2010.5537093},
doi = {10.1109/ISCAS.2010.5537093},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ShiTGR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/AdrianCG09,
author = {Victor Adrian and
Joseph S. Chang and
Bah{-}Hwee Gwee},
title = {A Low-Voltage Micropower Digital Class-D Amplifier Modulator for Hearing
Aids},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {2},
pages = {337--349},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2001831},
doi = {10.1109/TCSI.2008.2001831},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/AdrianCG09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GweeCSCC09,
author = {Bah{-}Hwee Gwee and
Joseph S. Chang and
Yiqiong Shi and
Chien{-}Chung Chua and
Kwen{-}Siong Chong},
title = {A Low-Voltage Micropower Asynchronous Multiplier With Shift-Add Multiplication
Approach},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {56-I},
number = {7},
pages = {1349--1359},
year = {2009},
url = {https://doi.org/10.1109/TCSI.2008.2006649},
doi = {10.1109/TCSI.2008.2006649},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/GweeCSCC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangGZ09,
author = {Kok{-}Leong Chang and
Bah{-}Hwee Gwee and
Yuanjin Zheng},
title = {A Performance Comparison on Asynchronous Matched-delay Templates},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
May 2009, Taipei, Taiwan},
pages = {1008--1011},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISCAS.2009.5117929},
doi = {10.1109/ISCAS.2009.5117929},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangGZ09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LinCGC09,
author = {Tong Lin and
Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Fine-grained Power Gating for Leakage and Short-circuit Power Reduction
by using Asynchronous-logic},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2009), 24-17
May 2009, Taipei, Taiwan},
pages = {3162--3165},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ISCAS.2009.5118474},
doi = {10.1109/ISCAS.2009.5118474},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LinCGC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LawGC08,
author = {Chong{-}Fatt Law and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {6},
pages = {985--998},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.923238},
doi = {10.1109/TCAD.2008.923238},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LawGC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangGZ08,
author = {Kok{-}Leong Chang and
Bah{-}Hwee Gwee and
Yuanjin Zheng},
title = {A semi-custom memory design for an asynchronous 8051 microcontroller},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {3398--3401},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4542188},
doi = {10.1109/ISCAS.2008.4542188},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangGZ08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangZG08,
author = {Kok{-}Leong Chang and
Yao Zhu and
Bah{-}Hwee Gwee},
title = {De-synchronization of a point-of-sales digital-logic controller},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {3402--3405},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4542189},
doi = {10.1109/ISCAS.2008.4542189},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangZG08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/ChongGC07,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Design of several asynchronous-logic macrocells for a low-voltage
micropower cell library},
journal = {{IET} Circuits Devices Syst.},
volume = {1},
number = {2},
pages = {161--169},
year = {2007},
url = {https://doi.org/10.1049/iet-cds:20060014},
doi = {10.1049/IET-CDS:20060014},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/ChongGC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cds/ChongGC07a,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Low energy 16-bit Booth leapfrog array multiplier using dynamic adders},
journal = {{IET} Circuits Devices Syst.},
volume = {1},
number = {2},
pages = {170--174},
year = {2007},
url = {https://doi.org/10.1049/iet-cds:20060109},
doi = {10.1049/IET-CDS:20060109},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cds/ChongGC07a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/LawGC07,
author = {Chong{-}Fatt Law and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Fast and memory-efficient invariant computation of ordinary Petri
nets},
journal = {{IET} Comput. Digit. Tech.},
volume = {1},
number = {5},
pages = {612--624},
year = {2007},
url = {https://doi.org/10.1049/iet-cdt:20060071},
doi = {10.1049/IET-CDT:20060071},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/iet-cdt/LawGC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jssc/ChongGC07,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Energy-Efficient Synchronous-Logic and Asynchronous-Logic {FFT/IFFT}
Processors},
journal = {{IEEE} J. Solid State Circuits},
volume = {42},
number = {9},
pages = {2034--2045},
year = {2007},
url = {https://doi.org/10.1109/JSSC.2007.903039},
doi = {10.1109/JSSC.2007.903039},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jssc/ChongGC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChongGC07,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A Low Energy {FFT/IFFT} Processor for Hearing Aids},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1169--1172},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378258},
doi = {10.1109/ISCAS.2007.378258},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChongGC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangGZ07,
author = {Kok{-}Leong Chang and
Bah{-}Hwee Gwee and
Yuanjin Zheng},
title = {An Asynchronous Dual-Rail Multiplier based on Energy-Efficient {STFB}
Templates},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3267--3270},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378169},
doi = {10.1109/ISCAS.2007.378169},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangGZ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/MukherjeeG07,
author = {Kunal Mukherjee and
Bah{-}Hwee Gwee},
title = {A 32-point {FFT} based Noise Reduction Algorithm for Single Channel
Speech Signals},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {3928--3931},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378659},
doi = {10.1109/ISCAS.2007.378659},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/MukherjeeG07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/ChongGC06,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A 16-Channel Low-Power Nonuniform Spaced Filter Bank Core for Digital
Hearing Aids},
journal = {{IEEE} Trans. Circuits Syst. {II} Express Briefs},
volume = {53-II},
number = {9},
pages = {853--857},
year = {2006},
url = {https://doi.org/10.1109/TCSII.2006.881821},
doi = {10.1109/TCSII.2006.881821},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/ChongGC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ACISicis/LawGC06,
author = {Chong{-}Fatt Law and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {Optimized Algorithm for Computing Invariants of Ordinary Petri Nets},
booktitle = {5th Annual {IEEE/ACIS} International Conference on Computer and Information
Science {(ICIS} 2006) and 1st {IEEE/ACIS} International Workshop on
Component-Based Software Engineering, Software Architecture and Reuse
{(COMSAR} 2006), 10-12 July 2006, Honolulu, Hawaii, {USA}},
pages = {23--28},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ICIS-COMSAR.2006.66},
doi = {10.1109/ICIS-COMSAR.2006.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ACISicis/LawGC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AdrianGC06,
author = {Victor Adrian and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {An acoustic noise suppression system with reduced musical artifacts},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693138},
doi = {10.1109/ISCAS.2006.1693138},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AdrianGC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangG06,
author = {Kok{-}Leong Chang and
Bah{-}Hwee Gwee},
title = {A low-energy low-voltage asynchronous 8051 microcontroller core},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1693301},
doi = {10.1109/ISCAS.2006.1693301},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangG06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijcat/GweeL05,
author = {Bah{-}Hwee Gwee and
Meng{-}Hiot Lim},
title = {An evolution search algorithm for solving N-queen problems},
journal = {Int. J. Comput. Appl. Technol.},
volume = {24},
number = {1},
pages = {43--48},
year = {2005},
url = {https://doi.org/10.1504/IJCAT.2005.007204},
doi = {10.1504/IJCAT.2005.007204},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/ijcat/GweeL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/GweeCA05,
author = {Bah{-}Hwee Gwee and
Joseph Sylvester Chang and
Victor Adrian},
title = {A micropower low-distortion digital class-D amplifier based on an
algorithmic pulsewidth modulator},
journal = {{IEEE} Trans. Circuits Syst. {I} Regul. Pap.},
volume = {52-I},
number = {10},
pages = {2007--2022},
year = {2005},
url = {https://doi.org/10.1109/TCSI.2005.852920},
doi = {10.1109/TCSI.2005.852920},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcas/GweeCA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChongGC05,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A micropower low-voltage multiplier with reduced spurious switching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {255--265},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840765},
doi = {10.1109/TVLSI.2004.840765},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChongGC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChongGC05,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Low-voltage micropower multipliers with reduced spurious switching},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {4078--4081},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465527},
doi = {10.1109/ISCAS.2005.1465527},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChongGC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AdrianGC05,
author = {Victor Adrian and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A combined interpolatorless interpolation and high accuracy sampling
process for digital class {D} amplifiers},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2005), 23-26
May 2005, Kobe, Japan},
pages = {5405--5408},
publisher = {{IEEE}},
year = {2005},
url = {https://doi.org/10.1109/ISCAS.2005.1465858},
doi = {10.1109/ISCAS.2005.1465858},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AdrianGC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AdrianGC04,
author = {Victor Adrian and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A novel combined first and second order Lagrange interpolation sampling
process for a digital class {D} amplifier},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {233--260},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ISCAS.2004.1328726},
doi = {10.1109/ISCAS.2004.1328726},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AdrianGC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChongGC04,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A low power 16-bit Booth Leapfrog array multiplier using Dynamic Adders},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {437--440},
publisher = {{IEEE}},
year = {2004},
timestamp = {Fri, 20 May 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChongGC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/his/GweeC03,
author = {Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
editor = {Ajith Abraham and
Mario K{\"{o}}ppen and
Katrin Franke},
title = {A Hybrid Genetic Hill-climbing Algorithm for Four-Coloring Map Problems},
booktitle = {Design and Application of Hybrid Intelligent Systems, HIS03, the Third
International Conference on Hybrid Intelligent Systems, Melbourne,
Australia, December 14-17, 2003},
series = {Frontiers in Artificial Intelligence and Applications},
volume = {105},
pages = {252--261},
publisher = {{IOS} Press},
year = {2003},
timestamp = {Wed, 04 Jan 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/his/GweeC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChuaGC03,
author = {Chien{-}Chung Chua and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A low-voltage micropower asynchronous multiplier for a multiplierless
{FIR} filter},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {381--384},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1206287},
doi = {10.1109/ISCAS.2003.1206287},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChuaGC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/GweeCAA03,
author = {Bah{-}Hwee Gwee and
Joseph Sylvester Chang and
Victor Adrian and
H. Amir},
title = {A novel sampling process and pulse generator for a low distortion
digital pulse-width modulator for digital class {D} amplifiers},
booktitle = {Proceedings of the 2003 International Symposium on Circuits and Systems,
{ISCAS} 2003, Bangkok, Thailand, May 25-28, 2003},
pages = {504--507},
publisher = {{IEEE}},
year = {2003},
url = {https://doi.org/10.1109/ISCAS.2003.1205936},
doi = {10.1109/ISCAS.2003.1205936},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/GweeCAA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChangGC03,
author = {Khia{-}Ho Chang and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
editor = {Hamid R. Arabnia and
Laurence Tianruo Yang},
title = {A Low Voltage Micropower 16-Word by 16-Bit 3-Port Asynchronous Register
File},
booktitle = {Proceedings of the International Conference on VLSI, {VLSI} '03, June
23 - 26, 2003, Las Vegas, Nevada, {USA}},
pages = {166--172},
publisher = {{CSREA} Press},
year = {2003},
timestamp = {Wed, 04 Jan 2006 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChangGC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChongGC02,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Low-voltage micropower asynchronous multiplier for hearing instruments},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {865--868},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1009978},
doi = {10.1109/ISCAS.2002.1009978},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChongGC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChongGC02a,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {Low-voltage asynchronous adders for low power and high speed applications},
booktitle = {Proceedings of the 2002 International Symposium on Circuits and Systems,
{ISCAS} 2002, Scottsdale, Arizona, USA, May 26-29, 2002},
pages = {873--876},
publisher = {{IEEE}},
year = {2002},
url = {https://doi.org/10.1109/ISCAS.2002.1009980},
doi = {10.1109/ISCAS.2002.1009980},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChongGC02a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChangGLT01,
author = {Joseph Sylvester Chang and
Bah{-}Hwee Gwee and
Yong Seng Lon and
Meng Tong Tan},
title = {A novel low-power low-voltage Class {D} amplifier with feedback for
improving THD, power efficiency and gain linearity},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {635--638},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.921936},
doi = {10.1109/ISCAS.2001.921936},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChangGLT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/LiGC01,
author = {Huiyun Li and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A digital Class {D} amplifier design embodying a novel sampling process
and pulse generator},
booktitle = {Proceedings of the 2001 International Symposium on Circuits and Systems,
{ISCAS} 2001, Sydney, Australia, May 6-9, 2001},
pages = {826--829},
publisher = {{IEEE}},
year = {2001},
url = {https://doi.org/10.1109/ISCAS.2001.922365},
doi = {10.1109/ISCAS.2001.922365},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/LiGC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/GweeL00,
author = {Bah{-}Hwee Gwee and
Meng{-}Hiot Lim},
title = {A {GA} with heuristic-based decoder for {IC} floorplanning},
journal = {Integr.},
volume = {28},
number = {2},
pages = {157--172},
year = {2000},
url = {https://doi.org/10.1016/S0167-9260(99)00015-2},
doi = {10.1016/S0167-9260(99)00015-2},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/GweeL00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/TanCGC00,
author = {Meng Tong Tan and
Hock{-}Chuan Chua and
Bah{-}Hwee Gwee and
Joseph S. Chang},
title = {An investigation on the parameters affecting total harmonic distortion
in class {D} amplifiers},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {193--196},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.858721},
doi = {10.1109/ISCAS.2000.858721},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/TanCGC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/coap/GweeL96,
author = {Bah{-}Hwee Gwee and
M. H. Lim},
title = {Polyominoes tiling by a genetic algorithm},
journal = {Comput. Optim. Appl.},
volume = {6},
number = {3},
pages = {273--291},
year = {1996},
url = {https://doi.org/10.1007/BF00247795},
doi = {10.1007/BF00247795},
timestamp = {Tue, 27 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/coap/GweeL96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fss/LimRG96,
author = {M. H. Lim and
Susanto Rahardja and
Bah{-}Hwee Gwee},
title = {A {GA} paradigm for learning fuzzy rules},
journal = {Fuzzy Sets Syst.},
volume = {82},
number = {2},
pages = {177--186},
year = {1996},
url = {https://doi.org/10.1016/0165-0114(95)00254-5},
doi = {10.1016/0165-0114(95)00254-5},
timestamp = {Tue, 27 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fss/LimRG96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jim/LimGK93,
author = {M. H. Lim and
Bah{-}Hwee Gwee and
Y. Kawada},
title = {Intelligent monitoring of a frequency-trimming process},
journal = {J. Intell. Manuf.},
volume = {4},
number = {6},
pages = {375--383},
year = {1993},
url = {https://doi.org/10.1007/BF00123951},
doi = {10.1007/BF00123951},
timestamp = {Tue, 27 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jim/LimGK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/annes/GweeLH93,
author = {Bah{-}Hwee Gwee and
Meng{-}Hiot Lim and
Jiun{-}Sien Ho},
title = {Solving four-colouring map problem using genetic algorithm},
booktitle = {First New Zealand International Two-Stream Conference on Artificial
Neural Networks and Expert Systems, {ANNES} '93, Dunedin, New Zealand,
November 24-26, 1993},
pages = {332--333},
publisher = {{IEEE}},
year = {1993},
url = {https://doi.org/10.1109/ANNES.1993.323010},
doi = {10.1109/ANNES.1993.323010},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/annes/GweeLH93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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