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BibTeX records: Pallav Gupta
@inproceedings{DBLP:conf/itc/Gupta18, author = {Pallav Gupta}, title = {An Effective Methodology for Automated Diagnosis of Functional Pattern Failures to Support Silicon Debug}, booktitle = {{IEEE} International Test Conference, {ITC} 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018}, pages = {1--8}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/TEST.2018.8624881}, doi = {10.1109/TEST.2018.8624881}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/itc/Gupta18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/itc/HuangGLG18, author = {I{-}De Huang and Pallav Gupta and Loganathan Lingappan and Vijay Gangaram}, title = {Online Scan Diagnosis : {A} Novel Approach to Volume Diagnosis}, booktitle = {{IEEE} International Test Conference, {ITC} 2018, Phoenix, AZ, USA, October 29 - Nov. 1, 2018}, pages = {1--10}, publisher = {{IEEE}}, year = {2018}, url = {https://doi.org/10.1109/TEST.2018.8624686}, doi = {10.1109/TEST.2018.8624686}, timestamp = {Sat, 26 Jan 2019 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/itc/HuangGLG18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiangZHYG15, author = {Hao Liang and Wei Zhang and Jiale Huang and Shengqi Yang and Pallav Gupta}, title = {Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {23}, number = {4}, pages = {731--742}, year = {2015}, url = {https://doi.org/10.1109/TVLSI.2014.2321182}, doi = {10.1109/TVLSI.2014.2321182}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiangZHYG15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jetc/YangWH0GC13, author = {Shengqi Yang and Wenping Wang and Mark Hagan and Wei Zhang and Pallav Gupta and Yu Cao}, title = {NBTI-aware circuit node criticality computation}, journal = {{ACM} J. Emerg. Technol. Comput. Syst.}, volume = {9}, number = {3}, pages = {23:1--23:19}, year = {2013}, url = {https://doi.org/10.1145/2491681}, doi = {10.1145/2491681}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jetc/YangWH0GC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jetc/HuangZYGZRGH12, author = {Jiale Huang and Minhao Zhu and Shengqi Yang and Pallav Gupta and Wei Zhang and Steven M. Rubin and Gilda Garret{\'{o}}n and Jin He}, title = {A physical design tool for carbon nanotube field-effect transistor circuits}, journal = {{ACM} J. Emerg. Technol. Comput. Syst.}, volume = {8}, number = {3}, pages = {25:1--25:20}, year = {2012}, url = {https://doi.org/10.1145/2287696.2287708}, doi = {10.1145/2287696.2287708}, timestamp = {Fri, 01 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jetc/HuangZYGZRGH12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tecs/YangGWSNX12, author = {Shengqi Yang and Pallav Gupta and Marilyn Wolf and Dimitrios N. Serpanos and Vijaykrishnan Narayanan and Yuan Xie}, title = {Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling}, journal = {{ACM} Trans. Embed. Comput. Syst.}, volume = {11}, number = {3}, pages = {62:1--62:16}, year = {2012}, url = {https://doi.org/10.1145/2345770.2345774}, doi = {10.1145/2345770.2345774}, timestamp = {Tue, 08 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tecs/YangGWSNX12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/KarimiCGP12, author = {Naghmeh Karimi and Krishnendu Chakrabarty and Pallav Gupta and Srinivas Patil}, editor = {Wolfgang Rosenstiel and Lothar Thiele}, title = {Test generation for clock-domain crossing faults in integrated circuits}, booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&} Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012}, pages = {406--411}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/DATE.2012.6176505}, doi = {10.1109/DATE.2012.6176505}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/KarimiCGP12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/todaes/WangG11, author = {Xiaofang (Maggie) Wang and Pallav Gupta}, title = {Resource-constrained multiprocessor synthesis for floating-point applications on FPGAs}, journal = {{ACM} Trans. Design Autom. Electr. Syst.}, volume = {16}, number = {4}, pages = {41:1--41:29}, year = {2011}, url = {https://doi.org/10.1145/2003695.2003701}, doi = {10.1145/2003695.2003701}, timestamp = {Sat, 09 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/todaes/WangG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ats/KarimiKCGP11, author = {Naghmeh Karimi and Zhiqiu Kong and Krishnendu Chakrabarty and Pallav Gupta and Srinivas Patil}, title = {Testing of Clock-Domain Crossing Faults in Multi-core System-on-Chip}, booktitle = {Proceedings of the 20th {IEEE} Asian Test Symposium, {ATS} 2011, New Delhi, India, November 20-23, 2011}, pages = {7--14}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/ATS.2011.68}, doi = {10.1109/ATS.2011.68}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/ats/KarimiKCGP11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ZhangHYG11, author = {Wei Zhang and Jiale Huang and Shengqi Yang and Pallav Gupta}, title = {Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface}, booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France, March 14-18, 2011}, pages = {1071--1076}, publisher = {{IEEE}}, year = {2011}, url = {https://doi.org/10.1109/DATE.2011.5763176}, doi = {10.1109/DATE.2011.5763176}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ZhangHYG11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GuptaZJ08, author = {Pallav Gupta and Rui Zhang and Niraj K. Jha}, title = {Automatic Test Generation for Combinational Threshold Logic Networks}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {16}, number = {8}, pages = {1035--1045}, year = {2008}, url = {https://doi.org/10.1109/TVLSI.2008.2000671}, doi = {10.1109/TVLSI.2008.2000671}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GuptaZJ08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhangGJ07, author = {Rui Zhang and Pallav Gupta and Niraj K. Jha}, title = {Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {26}, number = {7}, pages = {1233--1245}, year = {2007}, url = {https://doi.org/10.1109/TCAD.2006.888267}, doi = {10.1109/TCAD.2006.888267}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhangGJ07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/GuptaJL07, author = {Pallav Gupta and Niraj K. Jha and Loganathan Lingappan}, title = {A Test Generation Framework for Quantum Cellular Automata Circuits}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {15}, number = {1}, pages = {24--36}, year = {2007}, url = {https://doi.org/10.1109/TVLSI.2007.891081}, doi = {10.1109/TVLSI.2007.891081}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/GuptaJL07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/GuptaAJ06, author = {Pallav Gupta and Abhinav Agrawal and Niraj K. Jha}, title = {An Algorithm for Synthesis of Reversible Logic Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {25}, number = {11}, pages = {2317--2330}, year = {2006}, url = {https://doi.org/10.1109/TCAD.2006.871622}, doi = {10.1109/TCAD.2006.871622}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/GuptaAJ06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/GuptaJL06, author = {Pallav Gupta and Niraj K. Jha and Loganathan Lingappan}, editor = {Georges G. E. Gielen}, title = {Test generation for combinational quantum cellular automata {(QCA)} circuits}, booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe, {DATE} 2006, Munich, Germany, March 6-10, 2006}, pages = {311--316}, publisher = {European Design and Automation Association, Leuven, Belgium}, year = {2006}, url = {https://doi.org/10.1109/DATE.2006.244175}, doi = {10.1109/DATE.2006.244175}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/GuptaJL06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhangGZJ05, author = {Rui Zhang and Pallav Gupta and Lin Zhong and Niraj K. Jha}, title = {Threshold network synthesis and optimization and its application to nanotechnologies}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {24}, number = {1}, pages = {107--118}, year = {2005}, url = {https://doi.org/10.1109/TCAD.2004.839468}, doi = {10.1109/TCAD.2004.839468}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhangGZJ05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/GuptaRRJ05, author = {Pallav Gupta and Srivaths Ravi and Anand Raghunathan and Niraj K. Jha}, editor = {William H. Joyner Jr. and Grant Martin and Andrew B. Kahng}, title = {Efficient fingerprint-based user authentication for embedded systems}, booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005, San Diego, CA, USA, June 13-17, 2005}, pages = {244--247}, publisher = {{ACM}}, year = {2005}, url = {https://doi.org/10.1145/1065579.1065643}, doi = {10.1145/1065579.1065643}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/dac/GuptaRRJ05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/ZhangGJ05, author = {Rui Zhang and Pallav Gupta and Niraj K. Jha}, title = {Synthesis of Majority and Minority Networks and Its Applications to QCA, {TPL} and {SET} Based Nanotechnologies}, booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India}, pages = {229--234}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ICVD.2005.157}, doi = {10.1109/ICVD.2005.157}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/ZhangGJ05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/ZhangGZJ04, author = {Rui Zhang and Pallav Gupta and Lin Zhong and Niraj K. Jha}, title = {Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies}, booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2004), 16-20 February 2004, Paris, France}, pages = {904--909}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/DATE.2004.1269003}, doi = {10.1109/DATE.2004.1269003}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/ZhangGZJ04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/date/GuptaJ04, author = {Pallav Gupta and Niraj K. Jha}, title = {An Algorithm for Nano-Pipelining of Circuits and Architectures for a Nanotechnology}, booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition {(DATE} 2004), 16-20 February 2004, Paris, France}, pages = {974--979}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/DATE.2004.1269019}, doi = {10.1109/DATE.2004.1269019}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/date/GuptaJ04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/GuptaZJ04, author = {Pallav Gupta and Rui Zhang and Niraj K. Jha}, title = {An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks}, booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings}, pages = {540--543}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/ICCD.2004.1347974}, doi = {10.1109/ICCD.2004.1347974}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/GuptaZJ04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/GuptaZJ03, author = {Pallav Gupta and Lin Zhong and Niraj K. Jha}, title = {A High-level Interconnect Power Model for Design Space Exploration}, booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003, San Jose, CA, USA, November 9-13, 2003}, pages = {551--559}, publisher = {{IEEE} Computer Society / {ACM}}, year = {2003}, url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257865}, doi = {10.1109/ICCAD.2003.1257865}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/GuptaZJ03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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