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BibTeX records: Ali M. Farhangi
@inproceedings{DBLP:conf/ccece/EsmaeiliFAC12, author = {Seyed Ebrahim Esmaeili and Ali M. Farhangi and Asim J. Al{-}Khalili and Glenn E. R. Cowan}, title = {Clock tree structure with reduced wire length using the matched-delay skew compensation technique}, booktitle = {25th {IEEE} Canadian Conference on Electrical and Computer Engineering, {CCECE} 2012, Montreal, QC, Canada, April 29 - May 2, 2012}, pages = {1--4}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/CCECE.2012.6335054}, doi = {10.1109/CCECE.2012.6335054}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/ccece/EsmaeiliFAC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/iet-cdt/EsmaeiliFAC10, author = {Seyed Ebrahim Esmaeili and Ali M. Farhangi and Asim J. Al{-}Khalili and Glenn E. R. Cowan}, title = {Skew compensation in energy recovery clock distribution networks}, journal = {{IET} Comput. Digit. Tech.}, volume = {4}, number = {1}, pages = {56--72}, year = {2010}, url = {https://doi.org/10.1049/iet-cdt.2008.0155}, doi = {10.1049/IET-CDT.2008.0155}, timestamp = {Tue, 14 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/iet-cdt/EsmaeiliFAC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isvlsi/FarhangiAA10, author = {Ali M. Farhangi and Asim J. Al{-}Khalili and Dhamin Al{-}Khalili}, title = {Pattern-Driven Clock Tree Routing with Via Minimization}, booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2010, 5-7 July 2010, Lixouri Kefalonia, Greece}, pages = {216--221}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ISVLSI.2010.82}, doi = {10.1109/ISVLSI.2010.82}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isvlsi/FarhangiAA10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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