BibTeX records: Aristides Efthymiou

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@inproceedings{DBLP:conf/icaiic/PlissitiPSPPET24,
  author       = {Marina E. Plissiti and
                  Christoforos Papaioannou and
                  Yiorgos Sfikas and
                  Georgios Papatheodorou and
                  Simon{-}Ilias Poulis and
                  Aristides Efthymiou and
                  Yiorgos Tsiatouhas},
  title        = {Deep Learning Based Detection of Anti-Reflective Obstacles in {VLC}
                  Systems},
  booktitle    = {International Conference on Artificial Intelligence in Information
                  and Communication , {ICAIIC} 2024, Osaka, Japan, February 19-22, 2024},
  pages        = {401--406},
  publisher    = {{IEEE}},
  year         = {2024},
  url          = {https://doi.org/10.1109/ICAIIC60209.2024.10463371},
  doi          = {10.1109/ICAIIC60209.2024.10463371},
  timestamp    = {Tue, 02 Apr 2024 21:06:09 +0200},
  biburl       = {https://dblp.org/rec/conf/icaiic/PlissitiPSPPET24.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/blackseecom/PapaioannouPSPP22,
  author       = {Christoforos Papaioannou and
                  Marina E. Plissiti and
                  Yiorgos Sfikas and
                  Georgios Papatheodorou and
                  Simon{-}Ilias Poulis and
                  Aristides Efthymiou and
                  Yiorgos Tsiatouhas},
  title        = {Signal decoding in an {NLOS} {VLC} system with the presence of anti-reflective
                  obstacles},
  booktitle    = {10th {IEEE} International Black Sea Conference on Communications and
                  Networking, BlackSeaCom 2022, Sofia, Bulgaria, June 6-9, 2022},
  pages        = {303--309},
  publisher    = {{IEEE}},
  year         = {2022},
  url          = {https://doi.org/10.1109/BlackSeaCom54372.2022.9858232},
  doi          = {10.1109/BLACKSEACOM54372.2022.9858232},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/blackseecom/PapaioannouPSPP22.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/meditcom/PlissitiPSPPET21,
  author       = {Marina E. Plissiti and
                  Christoforos Papaioannou and
                  Yiorgos Sfikas and
                  Georgios Papatheodorou and
                  Simon{-}Ilias Poulis and
                  Aristides Efthymiou and
                  Yiorgos Tsiatouhas},
  title        = {An efficient adaptive thresholding scheme for signal decoding in {NLOS}
                  {VLC} systems},
  booktitle    = {{IEEE} International Mediterranean Conference on Communications and
                  Networking, MeditCom 2021, Athens, Greece, September 7-10, 2021},
  pages        = {378--382},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/MeditCom49071.2021.9647560},
  doi          = {10.1109/MEDITCOM49071.2021.9647560},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/meditcom/PlissitiPSPPET21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/glvlsi/Efthymiou13,
  author       = {Aristides Efthymiou},
  editor       = {Jos{\'{e}} Luis Ayala and
                  Alex K. Jones and
                  Patrick H. Madden and
                  Ayse K. Coskun},
  title        = {An error tolerant {CAM} with nand match-line organization},
  booktitle    = {Great Lakes Symposium on {VLSI} 2013 (part of ECRC), GLSVLSI'13, Paris,
                  France, May 2-4, 2013},
  pages        = {257--262},
  publisher    = {{ACM}},
  year         = {2013},
  url          = {https://doi.org/10.1145/2483028.2483105},
  doi          = {10.1145/2483028.2483105},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/glvlsi/Efthymiou13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/Efthymiou10,
  author       = {Aristides Efthymiou},
  title        = {Initialization-Based Test Pattern Generation for Asynchronous Circuits},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {18},
  number       = {4},
  pages        = {591--601},
  year         = {2010},
  url          = {https://doi.org/10.1109/TVLSI.2009.2013470},
  doi          = {10.1109/TVLSI.2009.2013470},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/Efthymiou10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/dsd/FergusonEAH10,
  author       = {Phillip David Ferguson and
                  Aristides Efthymiou and
                  Tughrul Arslan and
                  Danny Hume},
  editor       = {Sebasti{\'{a}}n L{\'{o}}pez},
  title        = {Optimising Self-Timed {FPGA} Circuits},
  booktitle    = {13th Euromicro Conference on Digital System Design, Architectures,
                  Methods and Tools, {DSD} 2010, 1-3 September 2010, Lille, France},
  pages        = {563--570},
  publisher    = {{IEEE} Computer Society},
  year         = {2010},
  url          = {https://doi.org/10.1109/DSD.2010.97},
  doi          = {10.1109/DSD.2010.97},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/dsd/FergusonEAH10.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ddecs/VasudevanE08,
  author       = {Dilip P. Vasudevan and
                  Aristides Efthymiou},
  editor       = {Bernd Straube and
                  Milos Drutarovsk{\'{y}} and
                  Michel Renovell and
                  Peter Gramata and
                  M{\'{a}}ria Fischerov{\'{a}}},
  title        = {A Partial Scan Based Test Generation for Asynchronous Circuits},
  booktitle    = {Proceedings of the 11th {IEEE} Workshop on Design {\&} Diagnostics
                  of Electronic Circuits {\&} Systems {(DDECS} 2008), Bratislava,
                  Slovakia, April 16-18, 2008},
  pages        = {186--189},
  publisher    = {{IEEE} Computer Society},
  year         = {2008},
  url          = {https://doi.org/10.1109/DDECS.2008.4538783},
  doi          = {10.1109/DDECS.2008.4538783},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/ddecs/VasudevanE08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/aina/HassanHTE07,
  author       = {Rahman Hassan and
                  Antony Harris and
                  Nigel P. Topham and
                  Aristides Efthymiou},
  title        = {Synthetic Trace-Driven Simulation of Cache Memory},
  booktitle    = {21st International Conference on Advanced Information Networking and
                  Applications {(AINA} 2007), Workshops Proceedings, Volume 1, May 21-23,
                  2007, Niagara Falls, Canada},
  pages        = {764--771},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/AINAW.2007.345},
  doi          = {10.1109/AINAW.2007.345},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/aina/HassanHTE07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ddecs/Efthymiou07,
  author       = {Aristides Efthymiou},
  editor       = {Patrick Girard and
                  Andrzej Krasniewski and
                  Elena Gramatov{\'{a}} and
                  Adam Pawlak and
                  Tomasz Garbolino},
  title        = {Redundancy and Test-Pattern Generation for Asynchronous Quasi-Delay-Insensitive
                  Combinational Circuits},
  booktitle    = {Proceedings of the 10th {IEEE} Workshop on Design {\&} Diagnostics
                  of Electronic Circuits {\&} Systems {(DDECS} 2007), Krak{\'{o}}w,
                  Poland, April 11-13, 2007},
  pages        = {377--382},
  publisher    = {{IEEE} Computer Society},
  year         = {2007},
  url          = {https://doi.org/10.1109/DDECS.2007.4295316},
  doi          = {10.1109/DDECS.2007.4295316},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/ddecs/Efthymiou07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/EfthymiouBE05,
  author       = {Aristides Efthymiou and
                  John Bainbridge and
                  Douglas A. Edwards},
  title        = {Test pattern generation and partial-scan methodology for an asynchronous
                  SoC interconnect},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {13},
  number       = {12},
  pages        = {1384--1393},
  year         = {2005},
  url          = {https://doi.org/10.1109/TVLSI.2005.862722},
  doi          = {10.1109/TVLSI.2005.862722},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/EfthymiouBE05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/asap/EfthymiouGP05,
  author       = {Aristides Efthymiou and
                  Jim D. Garside and
                  Ioannis Papaefstathiou},
  title        = {A Low-Power Processor Architecture Optimized forWireless Devices},
  booktitle    = {16th {IEEE} International Conference on Application-Specific Systems,
                  Architectures, and Processors {(ASAP} 2005), 23-25 July 2005, Samos,
                  Greece},
  pages        = {185--190},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ASAP.2005.7},
  doi          = {10.1109/ASAP.2005.7},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/asap/EfthymiouGP05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iolts/MatakiasTHAE05,
  author       = {Sotirios Matakias and
                  Y. Tsiatouhas and
                  Themistoklis Haniotakis and
                  Angela Arapoyanni and
                  Aristides Efthymiou},
  title        = {Fast, Parallel Two-Rail Code Checker with Enhanced Testability},
  booktitle    = {11th {IEEE} International On-Line Testing Symposium {(IOLTS} 2005),
                  6-8 July 2005, Saint Raphael, France},
  pages        = {149--156},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/IOLTS.2005.29},
  doi          = {10.1109/IOLTS.2005.29},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/iolts/MatakiasTHAE05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/tvlsi/EfthymiouG04,
  author       = {Aristides Efthymiou and
                  Jim D. Garside},
  title        = {A {CAM} with mixed serial-parallel comparison for use in low energy
                  caches},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {12},
  number       = {3},
  pages        = {325--329},
  year         = {2004},
  url          = {https://doi.org/10.1109/TVLSI.2004.824298},
  doi          = {10.1109/TVLSI.2004.824298},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tvlsi/EfthymiouG04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/EfthymiouSGB04,
  author       = {Aristides Efthymiou and
                  W. Suntiamorntut and
                  Jim D. Garside and
                  L. E. M. Brackenbury},
  title        = {An Asynchronous, Iterative Implementation of the Original Booth Multiplication
                  Algorithm},
  booktitle    = {10th International Symposium on Advanced Research in Asynchronous
                  Circuits and Systems {(ASYNC} 2004), 19-23 April 2004, Crete, Greece},
  pages        = {207--215},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/ASYNC.2004.1299304},
  doi          = {10.1109/ASYNC.2004.1299304},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/async/EfthymiouSGB04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/ats/EfthymiouBE04,
  author       = {Aristides Efthymiou and
                  John Bainbridge and
                  Douglas A. Edwards},
  title        = {Adding Testability to an Asynchronous Interconnect for {GALS} SoC},
  booktitle    = {13th Asian Test Symposium {(ATS} 2004), 15-17 November 2004, Kenting,
                  Taiwan},
  pages        = {20--23},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/ATS.2004.20},
  doi          = {10.1109/ATS.2004.20},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ats/EfthymiouBE04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/date/EfthymiouSE04,
  author       = {Aristides Efthymiou and
                  Christos P. Sotiriou and
                  Douglas A. Edwards},
  title        = {Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits},
  booktitle    = {2004 Design, Automation and Test in Europe Conference and Exposition
                  {(DATE} 2004), 16-20 February 2004, Paris, France},
  pages        = {672--673},
  publisher    = {{IEEE} Computer Society},
  year         = {2004},
  url          = {https://doi.org/10.1109/DATE.2004.1268924},
  doi          = {10.1109/DATE.2004.1268924},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/date/EfthymiouSE04.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/async/EfthymiouG03,
  author       = {Aristides Efthymiou and
                  Jim D. Garside},
  title        = {Adaptive Pipeline Structures fo Speculation Control},
  booktitle    = {9th International Symposium on Advanced Research in Asynchronous Circuits
                  and Systems {(ASYNC} 2003), 12-16 May 2003, Vancouver, BC, Canada},
  pages        = {46--55},
  publisher    = {{IEEE} Computer Society},
  year         = {2003},
  url          = {https://doi.org/10.1109/ASYNC.2003.1199165},
  doi          = {10.1109/ASYNC.2003.1199165},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/async/EfthymiouG03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/iccd/EfthymiouG02,
  author       = {Aristides Efthymiou and
                  Jim D. Garside},
  title        = {Adaptive Pipeline Depth Control for Processor Power-Management},
  booktitle    = {20th International Conference on Computer Design {(ICCD} 2002), {VLSI}
                  in Computers and Processors, 16-18 September 2002, Freiburg, Germany,
                  Proceedings},
  pages        = {454--457},
  publisher    = {{IEEE} Computer Society},
  year         = {2002},
  url          = {https://doi.org/10.1109/ICCD.2002.1106812},
  doi          = {10.1109/ICCD.2002.1106812},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/iccd/EfthymiouG02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/islped/EfthymiouG02,
  author       = {Aristides Efthymiou and
                  Jim D. Garside},
  editor       = {Vivek De and
                  Mary Jane Irwin and
                  Ingrid Verbauwhede and
                  Christian Piguet},
  title        = {An adaptive serial-parallel {CAM} architecture for low-power cache
                  blocks},
  booktitle    = {Proceedings of the 2002 International Symposium on Low Power Electronics
                  and Design, 2002, Monterey, California, USA, August 12-14, 2002},
  pages        = {136--141},
  publisher    = {{ACM}},
  year         = {2002},
  url          = {https://doi.org/10.1145/566408.566445},
  doi          = {10.1145/566408.566445},
  timestamp    = {Sat, 05 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/islped/EfthymiouG02.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/dt/FurberEGLLT01,
  author       = {Stephen B. Furber and
                  Aristides Efthymiou and
                  Jim D. Garside and
                  David W. Lloyd and
                  Mike J. G. Lewis and
                  Steve Temple},
  title        = {Power Management in the Amulet Microprocessors},
  journal      = {{IEEE} Des. Test Comput.},
  volume       = {18},
  number       = {2},
  pages        = {42--52},
  year         = {2001},
  url          = {https://doi.org/10.1109/54.914617},
  doi          = {10.1109/54.914617},
  timestamp    = {Sun, 17 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/dt/FurberEGLLT01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/sigcomm/KatevenisVE95,
  author       = {Manolis Katevenis and
                  Panagiota Vatsolaki and
                  Aristides Efthymiou},
  editor       = {Stuart Wecker and
                  David Oran},
  title        = {Pipelined Memory Shared Buffer for {VLSI} Switches},
  booktitle    = {Proceedings of the {ACM} {SIGCOMM} 1995 Conference on Applications,
                  Technologies, Architectures, and Protocols for Computer Communication,
                  Cambridge, MA, USA, August 28 - September 1, 1995},
  pages        = {39--48},
  publisher    = {{ACM}},
  year         = {1995},
  url          = {https://doi.org/10.1145/217382.217406},
  doi          = {10.1145/217382.217406},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/sigcomm/KatevenisVE95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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