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BibTeX records: Santanu Dutta
@inproceedings{DBLP:conf/vtc/ZhengD19, author = {Dunmin Zheng and Santanu Dutta}, title = {Adaptive Beamforming for Mobile Satellite Systems Based on User Location/Waveform}, booktitle = {90th {IEEE} Vehicular Technology Conference, {VTC} Fall 2019, Honolulu, HI, USA, September 22-25, 2019}, pages = {1--6}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.1109/VTCFall.2019.8891406}, doi = {10.1109/VTCFALL.2019.8891406}, timestamp = {Mon, 20 Dec 2021 11:29:04 +0100}, biburl = {https://dblp.org/rec/conf/vtc/ZhengD19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cssc/DuttaB18, author = {Santanu Dutta and Suparna Biswas}, title = {Nonparametric estimation of 100(1 - p){\%} expected shortfall: p {\(\rightarrow\)} 0 as sample size is increased}, journal = {Commun. Stat. Simul. Comput.}, volume = {47}, number = {2}, pages = {338--352}, year = {2018}, url = {https://doi.org/10.1080/03610918.2016.1152370}, doi = {10.1080/03610918.2016.1152370}, timestamp = {Mon, 01 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cssc/DuttaB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cssc/DuttaB17, author = {Santanu Dutta and Suparna Biswas}, title = {Extreme quantile estimation based on financial time series}, journal = {Commun. Stat. Simul. Comput.}, volume = {46}, number = {6}, pages = {4226--4243}, year = {2017}, url = {https://doi.org/10.1080/03610918.2015.1112908}, doi = {10.1080/03610918.2015.1112908}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cssc/DuttaB17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cssc/Dutta16, author = {Santanu Dutta}, title = {Cross-validation Revisited}, journal = {Commun. Stat. Simul. Comput.}, volume = {45}, number = {2}, pages = {472--490}, year = {2016}, url = {https://doi.org/10.1080/03610918.2013.862275}, doi = {10.1080/03610918.2013.862275}, timestamp = {Sun, 10 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cssc/Dutta16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cssc/Dutta15, author = {Santanu Dutta}, title = {Local Smoothing for Kernel Distribution Function Estimation}, journal = {Commun. Stat. Simul. Comput.}, volume = {44}, number = {4}, pages = {878--891}, year = {2015}, url = {https://doi.org/10.1080/03610918.2013.795591}, doi = {10.1080/03610918.2013.795591}, timestamp = {Sun, 10 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cssc/Dutta15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cssc/Dutta14, author = {Santanu Dutta}, title = {Local Smoothing Using the Bootstrap}, journal = {Commun. Stat. Simul. Comput.}, volume = {43}, number = {2}, pages = {378--389}, year = {2014}, url = {https://doi.org/10.1080/03610918.2012.703360}, doi = {10.1080/03610918.2012.703360}, timestamp = {Sun, 10 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cssc/Dutta14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ma/GhoshD13, author = {Subir Ghosh and Santanu Dutta}, title = {Robustness of designs for model discrimination}, journal = {J. Multivar. Anal.}, volume = {115}, pages = {193--203}, year = {2013}, url = {https://doi.org/10.1016/j.jmva.2012.10.009}, doi = {10.1016/J.JMVA.2012.10.009}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ma/GhoshD13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cm/AnsariDT09, author = {Arif Ansari and Santanu Dutta and Michael Tseytlin}, title = {S-WiMAX: adaptation of {IEEE} 802.16e for mobile satellite services}, journal = {{IEEE} Commun. Mag.}, volume = {47}, number = {6}, pages = {150--155}, year = {2009}, url = {https://doi.org/10.1109/MCOM.2009.5116812}, doi = {10.1109/MCOM.2009.5116812}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/cm/AnsariDT09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dac/RamanCOD07, author = {Balaji Raman and Samarjit Chakraborty and Wei Tsang Ooi and Santanu Dutta}, title = {Reducing Data-Memory Footprint of Multimedia Applications by Delay Redistribution}, booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007, San Diego, CA, USA, June 4-8, 2007}, pages = {738--743}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1145/1278480.1278664}, doi = {10.1145/1278480.1278664}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/dac/RamanCOD07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/secrypt/Dutta07, author = {Santanu Dutta}, editor = {Javier Hernando and Eduardo Fern{\'{a}}ndez{-}Medina and Manu Malek}, title = {Recent Trends in the Design of Video Signal Processing {IPS} and Multimedia SoCs}, booktitle = {{SECRYPT} 2007, Proceedings of the International Conference on Security and Cryptography, Barcelona, Spain, July 28-13, 2007, {SECRYPT} is part of {ICETE} - The International Joint Conference on e-Business and Telecommunications}, pages = {13}, publisher = {{INSTICC} Press}, year = {2007}, timestamp = {Fri, 04 Sep 2009 13:27:09 +0200}, biburl = {https://dblp.org/rec/conf/secrypt/Dutta07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/estimedia/Dutta05, author = {Santanu Dutta}, editor = {Miguel Miranda and Soonhoi Ha}, title = {Design of Multimillion-Gate Multimedia SoCs: Where do we stand?}, booktitle = {Proceedings of the 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, ESTIMedia 2005, September 22-23, 2005, New York Metropolitan Area, {USA}}, pages = {4}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/ESTMED.2005.1518056}, doi = {10.1109/ESTMED.2005.1518056}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/estimedia/Dutta05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sbcci/Dutta03, author = {Santanu Dutta}, title = {Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital {TV} Systems}, booktitle = {Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, {SBCCI} 2003, Sao Paulo, Brazil, September 8-11, 2003}, pages = {145}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/SBCCI.2003.1232820}, doi = {10.1109/SBCCI.2003.1232820}, timestamp = {Fri, 17 Jun 2022 15:49:04 +0200}, biburl = {https://dblp.org/rec/conf/sbcci/Dutta03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/DuttaJR01, author = {Santanu Dutta and Rune Jensen and Alf Rieckmann}, title = {Viper: {A} Multiprocessor {SOC} for Advanced Set-Top Box and Digital {TV} Systems}, journal = {{IEEE} Des. Test Comput.}, volume = {18}, number = {5}, pages = {21--31}, year = {2001}, url = {https://doi.org/10.1109/54.953269}, doi = {10.1109/54.953269}, timestamp = {Sun, 17 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/dt/DuttaJR01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/Dutta01, author = {Santanu Dutta}, title = {Architecture and design of {NX-2700:} a programmable single-chip {HDTV} all-format-decode-and-display processor}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {9}, number = {2}, pages = {313--328}, year = {2001}, url = {https://doi.org/10.1109/92.924054}, doi = {10.1109/92.924054}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/Dutta01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icecsys/Dutta01, author = {Santanu Dutta}, title = {Design verification of an 18-million-transistor digital television and media processor chip}, booktitle = {Proceedings of the 2001 8th {IEEE} International Conference on Electronics, Circuits and Systems, {ICECS} 2001, Malta, September 2-5, 2001}, pages = {1495--1499}, publisher = {{IEEE}}, year = {2001}, url = {https://doi.org/10.1109/ICECS.2001.957498}, doi = {10.1109/ICECS.2001.957498}, timestamp = {Mon, 09 Aug 2021 14:54:04 +0200}, biburl = {https://dblp.org/rec/conf/icecsys/Dutta01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/patmos/Dutta00, author = {Santanu Dutta}, editor = {Dimitrios Soudris and Peter Pirsch and Erich Barke}, title = {Architecture, Design, and Verification of an 18 Million Transistor Digital Television and Media Processor Chip}, booktitle = {Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, {PATMOS} 2000, G{\"{o}}ttingen, Germany, September 13-15, 2000, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1918}, pages = {225--232}, publisher = {Springer}, year = {2000}, url = {https://doi.org/10.1007/3-540-45373-3\_24}, doi = {10.1007/3-540-45373-3\_24}, timestamp = {Tue, 14 May 2019 10:00:54 +0200}, biburl = {https://dblp.org/rec/conf/patmos/Dutta00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/vlsid/DuttaSAM00, author = {Santanu Dutta and Deepak Singh and Essam Abu{-}Ghoush and Vijay Mehra}, title = {Architecture and Implementation of a High-Definition Video Co-Processor for Digital Television Applications}, booktitle = {13th International Conference on {VLSI} Design {(VLSI} Design 2000), 4-7 January 2000, Calcutta, India}, pages = {350--359}, publisher = {{IEEE} Computer Society}, year = {2000}, url = {https://doi.org/10.1109/ICVD.2000.812631}, doi = {10.1109/ICVD.2000.812631}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/vlsid/DuttaSAM00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcsv/DuttaMZSJVBPAKHLNBW99, author = {Santanu Dutta and Vijay Mehra and Weiwen Zhu and Deepak Singh and Marcel Janssens and Ramakrishna Vengalasetti and Boaz Ben{-}Nun and Pardha Pothana and Venkat Adusumilli and Nahid King and John Yen{-}Han Huang and Lie Ling and Chris Nelson and Jai Bannur and Sarah Wu}, title = {Architecture and design of a Talisman-compatible multimedia processor}, journal = {{IEEE} Trans. Circuits Syst. Video Technol.}, volume = {9}, number = {4}, pages = {565--579}, year = {1999}, url = {https://doi.org/10.1109/76.767123}, doi = {10.1109/76.767123}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcsv/DuttaMZSJVBPAKHLNBW99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/DuttaW99, author = {Santanu Dutta and Wayne H. Wolf}, title = {A circuit-driven design methodology for video signal-processing datapath elements}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {7}, number = {2}, pages = {229--240}, year = {1999}, url = {https://doi.org/10.1109/92.766750}, doi = {10.1109/92.766750}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/DuttaW99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcsv/DuttaWW98, author = {Santanu Dutta and Wayne H. Wolf and Andrew Wolfe}, title = {A methodology to evaluate memory architecture design tradeoffs for video signal processors}, journal = {{IEEE} Trans. Circuits Syst. Video Technol.}, volume = {8}, number = {1}, pages = {36--53}, year = {1998}, url = {https://doi.org/10.1109/76.660828}, doi = {10.1109/76.660828}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcsv/DuttaWW98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcsv/DuttaOWW98, author = {Santanu Dutta and Kevin J. O'Connor and Wayne H. Wolf and Andrew Wolfe}, title = {A design study of a 0.25-{\(\mu\)}m video signal processor}, journal = {{IEEE} Trans. Circuits Syst. Video Technol.}, volume = {8}, number = {4}, pages = {501--519}, year = {1998}, url = {https://doi.org/10.1109/76.709414}, doi = {10.1109/76.709414}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcsv/DuttaOWW98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/WolfeFDF97, author = {Andrew Wolfe and Jason Fritts and Santanu Dutta and Edil S. T. Fernandes}, title = {Datapath Design for a {VLIW} Video Signal Processor}, booktitle = {Proceedings of the 3rd {IEEE} Symposium on High-Performance Computer Architecture {(HPCA} '97), San Antonio, Texas, USA, February 1-5, 1997}, pages = {24--35}, publisher = {{IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/HPCA.1997.569593}, doi = {10.1109/HPCA.1997.569593}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/WolfeFDF97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcsv/DuttaW96, author = {Santanu Dutta and Wayne H. Wolf}, title = {A flexible parallel architecture adapted to block-matching motion-estimation algorithms}, journal = {{IEEE} Trans. Circuits Syst. Video Technol.}, volume = {6}, number = {1}, pages = {74--86}, year = {1996}, url = {https://doi.org/10.1109/76.486422}, doi = {10.1109/76.486422}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcsv/DuttaW96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/DuttaML95, author = {Santanu Dutta and Shivaling S. Mahant{-}Shetti and Stephen L. Lusky}, title = {A comprehensive delay model for {CMOS} inverters}, journal = {{IEEE} J. Solid State Circuits}, volume = {30}, number = {8}, pages = {864--871}, year = {1995}, url = {https://doi.org/10.1109/4.400428}, doi = {10.1109/4.400428}, timestamp = {Wed, 03 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/DuttaML95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcsv/DuttaW95, author = {Santanu Dutta and Wayne H. Wolf}, title = {Asymptotic limits of video signal processing architectures}, journal = {{IEEE} Trans. Circuits Syst. Video Technol.}, volume = {5}, number = {6}, pages = {545--561}, year = {1995}, url = {https://doi.org/10.1109/76.475897}, doi = {10.1109/76.475897}, timestamp = {Tue, 25 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcsv/DuttaW95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/DuttaWW95, author = {Santanu Dutta and Wayne H. Wolf and Andrew Wolfe}, title = {{VLSI} issues in memory-system design for video signal processors}, booktitle = {1995 International Conference on Computer Design {(ICCD} '95), {VLSI} in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings}, pages = {498--503}, publisher = {{IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/ICCD.1995.528914}, doi = {10.1109/ICCD.1995.528914}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/DuttaWW95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/DuttaW94, author = {Santanu Dutta and Wayne H. Wolf}, title = {Asymptotic Limits of Video Signal Processing Architectures}, booktitle = {Proceedings 1994 {IEEE} International Conference on Computer Design: {VLSI} in Computer {\&} Processors, {ICCD} '94, Cambridge, MA, USA, October 10-12, 1994}, pages = {622--625}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/ICCD.1994.331991}, doi = {10.1109/ICCD.1994.331991}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/DuttaW94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/DuttaNR94, author = {Santanu Dutta and Sudip Nag and Kaushik Roy}, title = {{ASAP:} {A} Transistor Sizing Tool for Speed Area and Power Optimization of Static {CMOS} Circuits}, booktitle = {1994 {IEEE} International Symposium on Circuits and Systems, {ISCAS} 1994, London, England, UK, May 30 - June 2, 1994}, pages = {61--64}, publisher = {{IEEE}}, year = {1994}, url = {https://doi.org/10.1109/ISCAS.1994.408755}, doi = {10.1109/ISCAS.1994.408755}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/DuttaNR94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccd/RoyND93, author = {Kaushik Roy and Sudip Nag and Santanu Dutta}, title = {Channel Architecture Optimization for Performance and Routability of Row-Based FPGAs}, booktitle = {Proceedings 1993 International Conference on Computer Design: {VLSI} in Computers {\&} Processors, {ICCD} '93, Cambridge, MA, USA, October 3-6, 1993}, pages = {220--223}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/ICCD.1993.393377}, doi = {10.1109/ICCD.1993.393377}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccd/RoyND93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/HolbergDP90, author = {Douglas R. Holberg and Santanu Dutta and Lawrence T. Pillage}, title = {{DC} Parameterized Piecewise-Function Transistor Models for Bipolar and {MOS} Logic Stage Delay Evaluation}, booktitle = {{IEEE/ACM} International Conference on Computer-Aided Design, {ICCAD} 1990, Santa Clara, CA, USA, November 11-15, 1990. Digest of Technical Papers}, pages = {546--549}, publisher = {{IEEE} Computer Society}, year = {1990}, url = {https://doi.org/10.1109/ICCAD.1990.129977}, doi = {10.1109/ICCAD.1990.129977}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/HolbergDP90.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iccad/ChenD89, author = {Hau{-}Yung Chen and Santanu Dutta}, title = {A timing model for static {CMOS} gates}, booktitle = {1989 {IEEE} International Conference on Computer-Aided Design, {ICCAD} 1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical Papers}, pages = {72--75}, publisher = {{IEEE} Computer Society}, year = {1989}, url = {https://doi.org/10.1109/ICCAD.1989.76907}, doi = {10.1109/ICCAD.1989.76907}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/iccad/ChenD89.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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