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BibTeX records: Paul Chow
@article{DBLP:journals/corr/abs-2402-12742, author = {Mohammad Ewais and Paul Chow}, title = {{DDC:} {A} Vision for a Disaggregated Datacenter}, journal = {CoRR}, volume = {abs/2402.12742}, year = {2024}, url = {https://doi.org/10.48550/arXiv.2402.12742}, doi = {10.48550/ARXIV.2402.12742}, eprinttype = {arXiv}, eprint = {2402.12742}, timestamp = {Thu, 21 Mar 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/corr/abs-2402-12742.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/access/EwaisC23, author = {Mohammad Ewais and Paul Chow}, title = {Disaggregated Memory in the Datacenter: {A} Survey}, journal = {{IEEE} Access}, volume = {11}, pages = {20688--20712}, year = {2023}, url = {https://doi.org/10.1109/ACCESS.2023.3250407}, doi = {10.1109/ACCESS.2023.3250407}, timestamp = {Tue, 28 Mar 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/access/EwaisC23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cloudcom/ShenC23, author = {Qiangfeng Shen and Paul Chow}, title = {A Lightweight Routing Layer Using a Reliable Link-Layer Protocol}, booktitle = {{IEEE} International Conference on Cloud Computing Technology and Science, CloudCom 2023, Naples, Italy, December 4-6, 2023}, pages = {82--90}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.1109/CloudCom59040.2023.00026}, doi = {10.1109/CLOUDCOM59040.2023.00026}, timestamp = {Thu, 11 Apr 2024 16:38:29 +0200}, biburl = {https://dblp.org/rec/conf/cloudcom/ShenC23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MazraeliGC23, author = {Mohammadmahdi Mazraeli and Yu Gao and Paul Chow}, editor = {Nele Mentens and Leonel Sousa and Pedro Trancoso and Nikela Papadopoulou and Ioannis Sourdis}, title = {Partitioning Large-Scale, Multi-FPGA Applications for the Data Center}, booktitle = {33rd International Conference on Field-Programmable Logic and Applications, {FPL} 2023, Gothenburg, Sweden, September 4-8, 2023}, pages = {253--258}, publisher = {{IEEE}}, year = {2023}, url = {https://doi.org/10.1109/FPL60245.2023.00043}, doi = {10.1109/FPL60245.2023.00043}, timestamp = {Fri, 17 Nov 2023 08:57:25 +0100}, biburl = {https://dblp.org/rec/conf/fpl/MazraeliGC23.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2309-08696, author = {Qianfeng Shen and Jun Zheng and Paul Chow}, title = {{RIFL:} {A} Reliable Link Layer Network Protocol for Data Center Communication}, journal = {CoRR}, volume = {abs/2309.08696}, year = {2023}, url = {https://doi.org/10.48550/arXiv.2309.08696}, doi = {10.48550/ARXIV.2309.08696}, eprinttype = {arXiv}, eprint = {2309.08696}, timestamp = {Fri, 22 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2309-08696.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2311-00911, author = {Qianfeng Shen and Paul Chow}, title = {A Lightweight Routing Layer Using a Reliable Link-Layer Protocol}, journal = {CoRR}, volume = {abs/2311.00911}, year = {2023}, url = {https://doi.org/10.48550/arXiv.2311.00911}, doi = {10.48550/ARXIV.2311.00911}, eprinttype = {arXiv}, eprint = {2311.00911}, timestamp = {Tue, 07 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/corr/abs-2311-00911.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jocnet/ShenZC22, author = {Qianfeng Shen and Jun Zheng and Paul Chow}, title = {{RIFL:} a reliable link layer network protocol for data center communication}, journal = {{JOCN}}, volume = {14}, number = {3}, pages = {111--126}, year = {2022}, url = {https://doi.org/10.1364/jocn.443448}, doi = {10.1364/JOCN.443448}, timestamp = {Sun, 16 Apr 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jocnet/ShenZC22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/TarafdarGHKLRTW22, author = {Naif Tarafdar and Giuseppe Di Guglielmo and Philip C. Harris and Jeffrey D. Krupa and Vladimir Loncar and Dylan S. Rankin and Nhan Tran and Zhenbin Wu and Qianfeng Shen and Paul Chow}, title = {\emph{AIgean}: An Open Framework for Deploying Machine Learning on Heterogeneous Clusters}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {15}, number = {3}, pages = {23:1--23:32}, year = {2022}, url = {https://doi.org/10.1145/3482854}, doi = {10.1145/3482854}, timestamp = {Mon, 25 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/TarafdarGHKLRTW22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/BobdaMCETVEKHLH22, author = {Christophe Bobda and Joel Mandebi Mbongue and Paul Chow and Mohammad Ewais and Naif Tarafdar and Juan Camilo Vega and Ken Eguro and Dirk Koch and Suranga Handagala and Miriam Leeser and Martin C. Herbordt and Hafsah Shahzad and H. Peter Hofstee and Burkhard Ringlein and Jakub Szefer and Ahmed Sanaullah and Russell Tessier}, title = {The Future of {FPGA} Acceleration in Datacenters and the Cloud}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {15}, number = {3}, pages = {34:1--34:42}, year = {2022}, url = {https://doi.org/10.1145/3506713}, doi = {10.1145/3506713}, timestamp = {Tue, 19 Dec 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/BobdaMCETVEKHLH22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/ShenVC22, author = {Qianfeng Clark Shen and Juan Camilo Vega and Paul Chow}, title = {Parallel {CRC} On An {FPGA} At Terabit Speeds}, booktitle = {International Conference on Field-Programmable Technology, {(IC)FPT} 2022, Hong Kong, December 5-9, 2022}, pages = {1--6}, publisher = {{IEEE}}, year = {2022}, url = {https://doi.org/10.1109/ICFPT56656.2022.9974233}, doi = {10.1109/ICFPT56656.2022.9974233}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/ShenVC22.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiCPJ21, author = {Jun Li and Paul Chow and Yuanxi Peng and Tian Jiang}, title = {{FPGA} Implementation of an Improved {OMP} for Compressive Sensing Reconstruction}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {29}, number = {2}, pages = {259--272}, year = {2021}, url = {https://doi.org/10.1109/TVLSI.2020.3030906}, doi = {10.1109/TVLSI.2020.3030906}, timestamp = {Mon, 13 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiCPJ21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/VegaELC21, author = {Juan Camilo Vega and Mohammad Ewais and Alberto Leon{-}Garcia and Paul Chow}, title = {{FFIVE:} An {FPGA} Framework for Interactive {VNF} Environments}, booktitle = {29th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2021, Orlando, FL, USA, May 9-12, 2021}, pages = {263}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/FCCM51124.2021.00050}, doi = {10.1109/FCCM51124.2021.00050}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/VegaELC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/RafiiCS21, author = {Arzhang Rafii and Paul Chow and Welson Sun}, title = {Pharos: a Performance Monitor for Multi-FPGA Systems}, booktitle = {29th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2021, Orlando, FL, USA, May 9-12, 2021}, pages = {271}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/FCCM51124.2021.00056}, doi = {10.1109/FCCM51124.2021.00056}, timestamp = {Mon, 07 Jun 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/RafiiCS21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/MerliniPC21, author = {Marco Antonio Merlini and Isamu Poy and Paul Chow}, editor = {Lesley Shannon and Michael Adler}, title = {Interactive Debugging at {IP} Block Interfaces in FPGAs}, booktitle = {{FPGA} '21: The 2021 {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021}, pages = {138--144}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3431920.3439305}, doi = {10.1145/3431920.3439305}, timestamp = {Wed, 24 Feb 2021 15:58:34 +0100}, biburl = {https://dblp.org/rec/conf/fpga/MerliniPC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ShenZC21, author = {Qianfeng Clark Shen and Jun Zheng and Paul Chow}, editor = {Lesley Shannon and Michael Adler}, title = {{RIFL:} {A} Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication}, booktitle = {{FPGA} '21: The 2021 {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021}, pages = {148}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3431920.3439467}, doi = {10.1145/3431920.3439467}, timestamp = {Wed, 24 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ShenZC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SharmaC21, author = {Varun Sharma and Paul Chow}, editor = {Lesley Shannon and Michael Adler}, title = {Exploring {PGAS} Communication for Heterogeneous Clusters with FPGAs}, booktitle = {{FPGA} '21: The 2021 {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28 - March 2, 2021}, pages = {225}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3431920.3439469}, doi = {10.1145/3431920.3439469}, timestamp = {Wed, 24 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/SharmaC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/RafiiSC21, author = {Arzhang Rafii and Welson Sun and Paul Chow}, title = {Pharos: a Multi-FPGA Performance Monitor}, booktitle = {31st International Conference on Field-Programmable Logic and Applications, {FPL} 2021, Dresden, Germany, August 30 - Sept. 3, 2021}, pages = {257--262}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/FPL53798.2021.00048}, doi = {10.1109/FPL53798.2021.00048}, timestamp = {Mon, 18 Oct 2021 17:08:51 +0200}, biburl = {https://dblp.org/rec/conf/fpl/RafiiSC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/nof/EwaisVLC21, author = {Mohammad Ewais and Juan Camilo Vega and Alberto Leon{-}Garcia and Paul Chow}, editor = {Carmen Mas Machuca and L{\'{u}}cia Martins and Susana Sargento and Tim Wauters and Lu{\'{\i}}sa Jorge and Nazih Salhab and Prosper Chemouil}, title = {A Framework Integrating FPGAs in {VNF} Networks}, booktitle = {12th International Conference on Network of the Future, NoF 2021, Coimbra, Portugal, October 6-8, 2021}, pages = {1--9}, publisher = {{IEEE}}, year = {2021}, url = {https://doi.org/10.1109/NoF52522.2021.9609941}, doi = {10.1109/NOF52522.2021.9609941}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/nof/EwaisVLC21.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/heart/2021, editor = {Christian Plessl and Paul Chow and Marco Platzner}, title = {{HEART} '21: 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, Virtual Event, Germany, 21-23 June, 2021}, publisher = {{ACM}}, year = {2021}, url = {https://doi.org/10.1145/3468044}, doi = {10.1145/3468044}, isbn = {978-1-4503-8549-7}, timestamp = {Tue, 03 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/heart/2021.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/abs-2104-12350, author = {Varun Sharma and Paul Chow}, title = {A {PGAS} Communication Library for Heterogeneous Clusters}, journal = {CoRR}, volume = {abs/2104.12350}, year = {2021}, url = {https://arxiv.org/abs/2104.12350}, eprinttype = {arXiv}, eprint = {2104.12350}, timestamp = {Mon, 03 May 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/abs-2104-12350.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/VegaMC20, author = {Juan Camilo Vega and Marco Antonio Merlini and Paul Chow}, title = {FFShark: {A} 100G {FPGA} Implementation of {BPF} Filtering for Wireshark}, booktitle = {28th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2020, Fayetteville, AR, USA, May 3-6, 2020}, pages = {47--55}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/FCCM48280.2020.00016}, doi = {10.1109/FCCM48280.2020.00016}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/VegaMC20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/LoC20, author = {Charles Lo and Paul Chow}, title = {Hierarchical Modelling of Generators in Design-Space Exploration}, booktitle = {28th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2020, Fayetteville, AR, USA, May 3-6, 2020}, pages = {186--194}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/FCCM48280.2020.00033}, doi = {10.1109/FCCM48280.2020.00033}, timestamp = {Thu, 25 Jun 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/LoC20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/VegaSC20, author = {Juan Camilo Vega and Qianfeng Clark Shen and Paul Chow}, title = {{SHIP:} Storage for Hybrid Interconnected Processors}, booktitle = {28th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2020, Fayetteville, AR, USA, May 3-6, 2020}, pages = {211}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/FCCM48280.2020.00043}, doi = {10.1109/FCCM48280.2020.00043}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/VegaSC20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/TarafdarGHKLRTW20, author = {Naif Tarafdar and Giuseppe Di Guglielmo and Philip C. Harris and Jeffrey D. Krupa and Vladimir Loncar and Dylan S. Rankin and Nhan Tran and Zhenbin Wu and Qianfeng Shen and Paul Chow}, title = {AIgean: An Open Framework for Machine Learning on Heterogeneous Clusters}, booktitle = {28th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2020, Fayetteville, AR, USA, May 3-6, 2020}, pages = {239}, publisher = {{IEEE}}, year = {2020}, url = {https://doi.org/10.1109/FCCM48280.2020.00072}, doi = {10.1109/FCCM48280.2020.00072}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/TarafdarGHKLRTW20.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/concurrency/GhasemiC19, author = {Ehsan Ghasemi and Paul Chow}, title = {Accelerating Apache Spark with FPGAs}, journal = {Concurr. Comput. Pract. Exp.}, volume = {31}, number = {2}, year = {2019}, url = {https://doi.org/10.1002/cpe.4222}, doi = {10.1002/CPE.4222}, timestamp = {Mon, 02 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/concurrency/GhasemiC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/SharmaTC19, author = {Varun Sharma and Naif Tarafdar and Paul Chow}, title = {Sonar: Writing Testbenches through Python}, booktitle = {27th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2019, San Diego, CA, USA, April 28 - May 1, 2019}, pages = {311}, publisher = {{IEEE}}, year = {2019}, url = {https://doi.org/10.1109/FCCM.2019.00052}, doi = {10.1109/FCCM.2019.00052}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/fccm/SharmaTC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/RozhkoC19, author = {Daniel Rozhko and Paul Chow}, editor = {Kia Bazargan and Stephen Neuendorffer}, title = {The Network Management Unit {(NMU):} Securing Network Access for Direct-Connected FPGAs}, booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019}, pages = {232--241}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3289602.3293903}, doi = {10.1145/3289602.3293903}, timestamp = {Tue, 05 Mar 2019 07:04:43 +0100}, biburl = {https://dblp.org/rec/conf/fpga/RozhkoC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/EskandariTLC19, author = {Nariman Eskandari and Naif Tarafdar and Daniel Ly{-}Ma and Paul Chow}, editor = {Kia Bazargan and Stephen Neuendorffer}, title = {A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the Data Center}, booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019}, pages = {262--271}, publisher = {{ACM}}, year = {2019}, url = {https://doi.org/10.1145/3289602.3293909}, doi = {10.1145/3289602.3293909}, timestamp = {Tue, 05 Mar 2019 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/EskandariTLC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/im/VegaSLC19, author = {Juan Camilo Vega and Qianfeng Shen and Alberto Leon{-}Garcia and Paul Chow}, editor = {Joe Betser and Carol J. Fung and Alex Clemm and J{\'{e}}r{\^{o}}me Fran{\c{c}}ois and Shingo Ata}, title = {Introducing ReCPRI: {A} Field Re-configurable Protocol for Backhaul Communication in a Radio Access Network}, booktitle = {{IFIP/IEEE} International Symposium on Integrated Network Management, {IM} 2019, Washington, DC, USA, April 09-11, 2019}, pages = {329--336}, publisher = {{IFIP}}, year = {2019}, url = {http://dl.ifip.org/db/conf/im/im2019/189399.pdf}, timestamp = {Tue, 10 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/im/VegaSLC19.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/dt/TarafdarELC18, author = {Naif Tarafdar and Nariman Eskandari and Thomas Lin and Paul Chow}, title = {Designing for FPGAs in the Cloud}, journal = {{IEEE} Des. Test}, volume = {35}, number = {1}, pages = {23--29}, year = {2018}, url = {https://doi.org/10.1109/MDAT.2017.2748393}, doi = {10.1109/MDAT.2017.2748393}, timestamp = {Fri, 13 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/dt/TarafdarELC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/TarafdarESLC18, author = {Naif Tarafdar and Nariman Eskandari and Varun Sharma and Charles Lo and Paul Chow}, title = {Galapagos: {A} Full Stack Approach to {FPGA} Integration in the Cloud}, journal = {{IEEE} Micro}, volume = {38}, number = {6}, pages = {18--24}, year = {2018}, url = {https://doi.org/10.1109/MM.2018.2877290}, doi = {10.1109/MM.2018.2877290}, timestamp = {Sat, 19 Oct 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/TarafdarESLC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/YassineARBC18, author = {Abdul{-}Amir Yassine and Yasmin Afsharnejad and Omar Ragheb and Vaughn Betz and Paul Chow}, title = {A High-Level Synthesis Case Study on Light Propagation Simulation in Turbid Media}, booktitle = {26th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2018, Boulder, CO, USA, April 29 - May 1, 2018}, pages = {216}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/FCCM.2018.00050}, doi = {10.1109/FCCM.2018.00050}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/YassineARBC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LoC18, author = {Charles Lo and Paul Chow}, title = {Multi-fidelity Optimization for High-Level Synthesis Directives}, booktitle = {28th International Conference on Field Programmable Logic and Applications, {FPL} 2018, Dublin, Ireland, August 27-31, 2018}, pages = {272--279}, publisher = {{IEEE} Computer Society}, year = {2018}, url = {https://doi.org/10.1109/FPL.2018.00054}, doi = {10.1109/FPL.2018.00054}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/LoC18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/heart/AfsharnejadYRCB18, author = {Yasmin Afsharnejad and Abdul{-}Amir Yassine and Omar Ragheb and Paul Chow and Vaughn Betz}, title = {HLS-based {FPGA} Acceleration of Light Propagation Simulation in Turbid Media}, booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto, ON, Canada, June 20-22, 2018}, pages = {11:1--11:6}, publisher = {{ACM}}, year = {2018}, url = {https://doi.org/10.1145/3241793.3241804}, doi = {10.1145/3241793.3241804}, timestamp = {Wed, 21 Nov 2018 12:44:16 +0100}, biburl = {https://dblp.org/rec/conf/heart/AfsharnejadYRCB18.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/apnoms/LinTPCL17, author = {Thomas Lin and Naif Tarafdar and Byungchul Park and Paul Chow and Alberto Leon{-}Garcia}, title = {Enabling network function virtualization over heterogeneous resources}, booktitle = {19th Asia-Pacific Network Operations and Management Symposium, {APNOMS} 2017, Seoul, Korea (South), September 27-29, 2017}, pages = {58--63}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/APNOMS.2017.8094179}, doi = {10.1109/APNOMS.2017.8094179}, timestamp = {Wed, 16 Oct 2019 14:14:56 +0200}, biburl = {https://dblp.org/rec/conf/apnoms/LinTPCL17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asplos/Chow17, author = {Paul Chow}, title = {Building the Reconfigurable Cloud Ecosystem}, booktitle = {Proceedings of the first Workshop on Emerging Technologies for software-defined and reconfigurable hardware-accelerated Cloud Datacenters, ETCD@ASPLOS 2017, Xi'an, China, April 8, 2017}, pages = {10:1}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3129457.3129501}, doi = {10.1145/3129457.3129501}, timestamp = {Tue, 06 Nov 2018 11:07:42 +0100}, biburl = {https://dblp.org/rec/conf/asplos/Chow17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/RozhkoELCJ17, author = {Daniel Rozhko and Geoffrey Elliott and Daniel Ly{-}Ma and Paul Chow and Hans{-}Arno Jacobsen}, editor = {Jonathan W. Greene and Jason Helge Anderson}, title = {Packet Matching on FPGAs Using {HMC} Memory: Towards One Million Rules}, booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017}, pages = {201--206}, publisher = {{ACM}}, year = {2017}, url = {http://dl.acm.org/citation.cfm?id=3021752}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/RozhkoELCJ17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/TarafdarLFBLC17, author = {Naif Tarafdar and Thomas Lin and Eric Fukuda and Hadi Bannazadeh and Alberto Leon{-}Garcia and Paul Chow}, editor = {Jonathan W. Greene and Jason Helge Anderson}, title = {Enabling Flexible Network {FPGA} Clusters in a Heterogeneous Cloud Data Center}, booktitle = {Proceedings of the 2017 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} 2017, Monterey, CA, USA, February 22-24, 2017}, pages = {237--246}, publisher = {{ACM}}, year = {2017}, url = {http://dl.acm.org/citation.cfm?id=3021742}, timestamp = {Fri, 03 Feb 2017 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/TarafdarLFBLC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/TarafdarLELLC17, author = {Naif Tarafdar and Thomas Lin and Nariman Eskandari and David Lion and Alberto Leon{-}Garcia and Paul Chow}, editor = {Marco D. Santambrogio and Diana G{\"{o}}hringer and Dirk Stroobandt and Nele Mentens and Jari Nurmi}, title = {Heterogeneous virtualized network function framework for the data center}, booktitle = {27th International Conference on Field Programmable Logic and Applications, {FPL} 2017, Ghent, Belgium, September 4-8, 2017}, pages = {1--8}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.23919/FPL.2017.8056790}, doi = {10.23919/FPL.2017.8056790}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/TarafdarLELLC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/LiuDJ0C17, author = {Zhiqiang Liu and Yong Dou and Jingfei Jiang and Qiang Wang and Paul Chow}, title = {An FPGA-based processor for training convolutional neural networks}, booktitle = {International Conference on Field Programmable Technology, {FPT} 2017, Melbourne, Australia, December 11-13, 2017}, pages = {207--210}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/FPT.2017.8280142}, doi = {10.1109/FPT.2017.8280142}, timestamp = {Sat, 30 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/LiuDJ0C17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/DiCeccoSC17, author = {Roberto DiCecco and Lin Sun and Paul Chow}, title = {FPGA-based training of convolutional neural networks with a reduced precision floating-point library}, booktitle = {International Conference on Field Programmable Technology, {FPT} 2017, Melbourne, Australia, December 11-13, 2017}, pages = {239--242}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/FPT.2017.8280150}, doi = {10.1109/FPT.2017.8280150}, timestamp = {Mon, 17 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpt/DiCeccoSC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iwocl/MirianC17, author = {Vincent Mirian and Paul Chow}, editor = {Simon McIntosh{-}Smith and Ben Bergen}, title = {Enabling FPGAs as a True Device in the OpenCL Standard: Bridging the Gap for FPGAs}, booktitle = {Proceedings of the 5th International Workshop on OpenCL, {IWOCL} 2017, Toronto, Canada, May 16-18, 2017}, pages = {5:1--5:12}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3078155.3078176}, doi = {10.1145/3078155.3078176}, timestamp = {Mon, 21 Dec 2020 16:56:10 +0100}, biburl = {https://dblp.org/rec/conf/iwocl/MirianC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/memsys/CampoC17, author = {Fernando Martin del Campo and Paul Chow}, title = {Task replication and control for highly parallel in-memory stores}, booktitle = {Proceedings of the International Symposium on Memory Systems, {MEMSYS} 2017, Alexandria, VA, USA, October 02 - 05, 2017}, pages = {312--326}, publisher = {{ACM}}, year = {2017}, url = {https://doi.org/10.1145/3132402.3132428}, doi = {10.1145/3132402.3132428}, timestamp = {Fri, 13 Nov 2020 09:24:44 +0100}, biburl = {https://dblp.org/rec/conf/memsys/CampoC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/BoutrosGAC17, author = {Andrew Boutros and Brett Grady and Mustafa Abbas and Paul Chow}, title = {Build fast, trade fast: FPGA-based high-frequency trading using high-level synthesis}, booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2017, Cancun, Mexico, December 4-6, 2017}, pages = {1--6}, publisher = {{IEEE}}, year = {2017}, url = {https://doi.org/10.1109/RECONFIG.2017.8279781}, doi = {10.1109/RECONFIG.2017.8279781}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/reconfig/BoutrosGAC17.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ZhangCL16, author = {Jianfeng Zhang and Paul Chow and Hengzhu Liu}, title = {CORDIC-Based Enhanced Systolic Array Architecture for {QR} Decomposition}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {9}, number = {2}, pages = {9:1--9:22}, year = {2016}, url = {https://doi.org/10.1145/2827700}, doi = {10.1145/2827700}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ZhangCL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/GhasemiC16, author = {Ehsan Ghasemi and Paul Chow}, title = {Accelerating Apache Spark Big Data Analysis with FPGAs}, booktitle = {24th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2016, Washington, DC, USA, May 1-3, 2016}, pages = {94}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/FCCM.2016.33}, doi = {10.1109/FCCM.2016.33}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/GhasemiC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/GhasemiC16, author = {Ehsan Ghasemi and Paul Chow}, editor = {Deming Chen and Jonathan W. Greene}, title = {A Scalable Heterogeneous Dataflow Architecture For Big Data Analytics Using FPGAs (Abstract Only)}, booktitle = {Proceedings of the 2016 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 21-23, 2016}, pages = {274}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2847263.2847294}, doi = {10.1145/2847263.2847294}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/GhasemiC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LoC16, author = {Charles Lo and Paul Chow}, editor = {Paolo Ienne and Walid A. Najjar and Jason Helge Anderson and Philip Brisk and Walter Stechele}, title = {Model-based optimization of High Level Synthesis directives}, booktitle = {26th International Conference on Field Programmable Logic and Applications, {FPL} 2016, Lausanne, Switzerland, August 29 - September 2, 2016}, pages = {1--10}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/FPL.2016.7577358}, doi = {10.1109/FPL.2016.7577358}, timestamp = {Fri, 17 Jan 2020 17:11:15 +0100}, biburl = {https://dblp.org/rec/conf/fpl/LoC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/DiCeccoLVCTA16, author = {Roberto DiCecco and Griffin Lacey and Jasmina Vasiljevic and Paul Chow and Graham W. Taylor and Shawki Areibi}, editor = {Yuchen Song and Shaojun Wang and Brent Nelson and Junbao Li and Yu Peng}, title = {Caffeinated FPGAs: {FPGA} framework For Convolutional Neural Networks}, booktitle = {2016 International Conference on Field-Programmable Technology, {FPT} 2016, Xi'an, China, December 7-9, 2016}, pages = {265--268}, publisher = {{IEEE}}, year = {2016}, url = {https://doi.org/10.1109/FPT.2016.7929549}, doi = {10.1109/FPT.2016.7929549}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/DiCeccoLVCTA16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/MirianC16, author = {Vincent Mirian and Paul Chow}, editor = {Ayse K. Coskun and Martin Margala and Laleh Behjat and Jie Han}, title = {Extracting Designs of Secure IPs Using {FPGA} {CAD} Tools}, booktitle = {Proceedings of the 26th edition on Great Lakes Symposium on VLSI, {GLVLSI} 2016, Boston, MA, USA, May 18-20, 2016}, pages = {293--298}, publisher = {{ACM}}, year = {2016}, url = {https://doi.org/10.1145/2902961.2903033}, doi = {10.1145/2902961.2903033}, timestamp = {Wed, 10 Mar 2021 14:55:38 +0100}, biburl = {https://dblp.org/rec/conf/glvlsi/MirianC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/uic/GhasemiC16, author = {Ehsan Ghasemi and Paul Chow}, title = {Accelerating Apache Spark Big Data Analysis with FPGAs}, booktitle = {2016 Intl {IEEE} Conferences on Ubiquitous Intelligence {\&} Computing, Advanced and Trusted Computing, Scalable Computing and Communications, Cloud and Big Data Computing, Internet of People, and Smart World Congress (UIC/ATC/ScalCom/CBDCom/IoP/SmartWorld), Toulouse, France, July 18-21, 2016}, pages = {737--744}, publisher = {{IEEE} Computer Society}, year = {2016}, url = {https://doi.org/10.1109/UIC-ATC-ScalCom-CBDCom-IoP-SmartWorld.2016.0119}, doi = {10.1109/UIC-ATC-SCALCOM-CBDCOM-IOP-SMARTWORLD.2016.0119}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/uic/GhasemiC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/DiCeccoLVCTA16, author = {Roberto DiCecco and Griffin Lacey and Jasmina Vasiljevic and Paul Chow and Graham W. Taylor and Shawki Areibi}, title = {Caffeinated FPGAs: {FPGA} Framework For Convolutional Neural Networks}, journal = {CoRR}, volume = {abs/1609.09671}, year = {2016}, url = {http://arxiv.org/abs/1609.09671}, eprinttype = {arXiv}, eprint = {1609.09671}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/DiCeccoLVCTA16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ZhangCL15, author = {Jianfeng Zhang and Paul Chow and Hengzhu Liu}, title = {An Enhanced Adaptive Recoding Rotation {CORDIC}}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {9}, number = {1}, pages = {4:1--4:25}, year = {2015}, url = {https://doi.org/10.1145/2812813}, doi = {10.1145/2812813}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ZhangCL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/BymaTXBLC15, author = {Stuart Byma and Naif Tarafdar and Talia Xu and Hadi Bannazadeh and Alberto Leon{-}Garcia and Paul Chow}, editor = {George A. Constantinides and Deming Chen}, title = {Expanding OpenFlow Capabilities with Virtualized Reconfigurable Hardware}, booktitle = {Proceedings of the 2015 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA, February 22-24, 2015}, pages = {94--97}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2684746.2689086}, doi = {10.1145/2684746.2689086}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/BymaTXBLC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/VasiljevicWSFMS15, author = {Jasmina Vasiljevic and Ralph Wittig and Paul Schumacher and Jeff Fifield and Fernando Martinez{-}Vallina and Henry Styles and Paul Chow}, title = {OpenCL library of stream memory components targeting FPGAs}, booktitle = {2015 International Conference on Field Programmable Technology, {FPT} 2015, Queenstown, New Zealand, December 7-9, 2015}, pages = {104--111}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/FPT.2015.7393134}, doi = {10.1109/FPT.2015.7393134}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/VasiljevicWSFMS15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/MirianC15, author = {Vincent Mirian and Paul Chow}, title = {Exploring pipe implementations using an OpenCL framework for FPGAs}, booktitle = {2015 International Conference on Field Programmable Technology, {FPT} 2015, Queenstown, New Zealand, December 7-9, 2015}, pages = {112--119}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/FPT.2015.7393135}, doi = {10.1109/FPT.2015.7393135}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/MirianC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/ZhangCL15, author = {Jianfeng Zhang and Paul Chow and Hengzhu Liu}, title = {{FPGA} implementation of low-power and high-PSNR {DCT/IDCT} architecture based on adaptive recoding {CORDIC}}, booktitle = {2015 International Conference on Field Programmable Technology, {FPT} 2015, Queenstown, New Zealand, December 7-9, 2015}, pages = {128--135}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/FPT.2015.7393139}, doi = {10.1109/FPT.2015.7393139}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/ZhangCL15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/memsys/CampoC15, author = {Fernando Martin del Campo and Paul Chow}, editor = {Bruce L. Jacob}, title = {Architecture Exploration for Data Intensive Applications}, booktitle = {Proceedings of the 2015 International Symposium on Memory Systems, {MEMSYS} 2015, Washington DC, DC, USA, October 5-8, 2015}, pages = {135--145}, publisher = {{ACM}}, year = {2015}, url = {https://doi.org/10.1145/2818950.2818970}, doi = {10.1145/2818950.2818970}, timestamp = {Fri, 13 Nov 2020 09:24:44 +0100}, biburl = {https://dblp.org/rec/conf/memsys/CampoC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/MirianC15, author = {Vincent Mirian and Paul Chow}, editor = {Michael H{\"{u}}bner and Maya B. Gokhale and Ren{\'{e}} Cumplido}, title = {Evaluating shared virtual memory in an OpenCL framework for embedded systems on FPGAs}, booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015}, pages = {1--8}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ReConFig.2015.7393303}, doi = {10.1109/RECONFIG.2015.7393303}, timestamp = {Wed, 28 Apr 2021 16:06:54 +0200}, biburl = {https://dblp.org/rec/conf/reconfig/MirianC15.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/MirianC15a, author = {Vincent Mirian and Paul Chow}, editor = {Michael H{\"{u}}bner and Maya B. Gokhale and Ren{\'{e}} Cumplido}, title = {{UT-OCL:} an OpenCL framework for embedded systems using xilinx FPGAs}, booktitle = {International Conference on ReConFigurable Computing and FPGAs, ReConFig 2015, Riviera Maya, Mexico, December 7-9, 2015}, pages = {1--6}, publisher = {{IEEE}}, year = {2015}, url = {https://doi.org/10.1109/ReConFig.2015.7393366}, doi = {10.1109/RECONFIG.2015.7393366}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/reconfig/MirianC15a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/PengSMZC14, author = {Yuanxi Peng and Manuel Salda{\~{n}}a and Christopher A. Madill and Xiaofeng Zou and Paul Chow}, title = {Benefits of Adding Hardware Support for Broadcast and Reduce Operations in MPSoC Applications}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {7}, number = {3}, pages = {17:1--17:23}, year = {2014}, url = {https://doi.org/10.1145/2629470}, doi = {10.1145/2629470}, timestamp = {Mon, 13 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/trets/PengSMZC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LiCJZW14, author = {Yuan Li and Paul Chow and Jiang Jiang and Minxuan Zhang and Shaojun Wei}, title = {Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the {WELL} Method}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {22}, number = {5}, pages = {1054--1059}, year = {2014}, url = {https://doi.org/10.1109/TVLSI.2013.2262103}, doi = {10.1109/TVLSI.2013.2262103}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LiCJZW14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/BymaSBLC14, author = {Stuart Byma and J. Gregory Steffan and Hadi Bannazadeh and Alberto Leon{-}Garcia and Paul Chow}, title = {FPGAs in the Cloud: Booting Virtualized Hardware Accelerators with OpenStack}, booktitle = {22nd {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2014, Boston, MA, USA, May 11-13, 2014}, pages = {109--116}, publisher = {{IEEE} Computer Society}, year = {2014}, url = {https://doi.org/10.1109/FCCM.2014.42}, doi = {10.1109/FCCM.2014.42}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/BymaSBLC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/VasiljevicC14, author = {Jasmina Vasiljevic and Paul Chow}, editor = {Vaughn Betz and George A. Constantinides}, title = {MPack: global memory optimization for stream applications in high-level synthesis}, booktitle = {The 2014 {ACM/SIGDA} International Symposium on Field-Programmable Gate Arrays, {FPGA} '14, Monterey, CA, {USA} - February 26 - 28, 2014}, pages = {233--236}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2554688.2554761}, doi = {10.1145/2554688.2554761}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/VasiljevicC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/MirianC14, author = {Vincent Mirian and Paul Chow}, title = {Using an OpenCL framework to evaluate interconnect implementations on FPGAs}, booktitle = {24th International Conference on Field Programmable Logic and Applications, {FPL} 2014, Munich, Germany, 2-4 September, 2014}, pages = {1--4}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/FPL.2014.6927440}, doi = {10.1109/FPL.2014.6927440}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/MirianC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/VasiljevicC14, author = {Jasmina Vasiljevic and Paul Chow}, title = {Using buffer-to-BRAM mapping approaches to trade-off throughput vs. memory use}, booktitle = {24th International Conference on Field Programmable Logic and Applications, {FPL} 2014, Munich, Germany, 2-4 September, 2014}, pages = {1--8}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/FPL.2014.6927469}, doi = {10.1109/FPL.2014.6927469}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/VasiljevicC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/ZhangCL14, author = {Jianfeng Zhang and Paul Chow and Hengzhu Liu}, editor = {Jialin Chen and Wenbo Yin and Yuichiro Shibata and Lingli Wang and Hayden Kwok{-}Hay So and Yuchun Ma}, title = {An efficient {FPGA} implementation of {QR} decomposition using a novel systolic array architecture based on enhanced vectoring {CORDIC}}, booktitle = {2014 International Conference on Field-Programmable Technology, {FPT} 2014, Shanghai, China, December 10-12, 2014}, pages = {123--130}, publisher = {{IEEE}}, year = {2014}, url = {https://doi.org/10.1109/FPT.2014.7082764}, doi = {10.1109/FPT.2014.7082764}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/ZhangCL14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/pgas/WillenbergC14, author = {Ruediger Willenberg and Paul Chow}, editor = {Allen D. Malony and Jeff R. Hammond}, title = {A Heterogeneous GASNet Implementation for FPGA-accelerated Computing}, booktitle = {Proceedings of the 8th International Conference on Partitioned Global Address Space Programming Models, {PGAS} 2014, Eugene, OR, USA, October 6-10, 2014}, pages = {2:1--2:9}, publisher = {{ACM}}, year = {2014}, url = {https://doi.org/10.1145/2676870.2676885}, doi = {10.1145/2676870.2676885}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/pgas/WillenbergC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/tridentcom/BymaBLSC14, author = {Stuart Byma and Hadi Bannazadeh and Alberto Leon{-}Garcia and J. Gregory Steffan and Paul Chow}, editor = {Victor C. M. Leung and Min Chen and Jiafu Wan and Yin Zhang}, title = {Virtualized Reconfigurable Hardware Resources in the {SAVI} Testbed}, booktitle = {Testbeds and Research Infrastructure: Development of Networks and Communities - 9th International {ICST} Conference, TridentCom 2014, Guangzhou, China, May 5-7, 2014, Revised Selected Papers}, series = {Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering}, volume = {137}, pages = {54--64}, publisher = {Springer}, year = {2014}, url = {https://doi.org/10.1007/978-3-319-13326-3\_6}, doi = {10.1007/978-3-319-13326-3\_6}, timestamp = {Sat, 05 Sep 2020 18:08:54 +0200}, biburl = {https://dblp.org/rec/conf/tridentcom/BymaBLSC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/corr/WillenbergC14, author = {Ruediger Willenberg and Paul Chow}, title = {A Software Parallel Programming Approach to FPGA-Accelerated Computing}, journal = {CoRR}, volume = {abs/1408.4959}, year = {2014}, url = {http://arxiv.org/abs/1408.4959}, eprinttype = {arXiv}, eprint = {1408.4959}, timestamp = {Mon, 13 Aug 2018 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/corr/WillenbergC14.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/WillenbergC13, author = {Ruediger Willenberg and Paul Chow}, editor = {Brad L. Hutchings and Vaughn Betz}, title = {A remote memory access infrastructure for global address space programming models in FPGAs}, booktitle = {The 2013 {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, {FPGA} '13, Monterey, CA, USA, February 11-13, 2013}, pages = {211--220}, publisher = {{ACM}}, year = {2013}, url = {https://doi.org/10.1145/2435264.2435301}, doi = {10.1145/2435264.2435301}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/WillenbergC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/BymaSC13, author = {Stuart Byma and J. Gregory Steffan and Paul Chow}, title = {NetThreads-10G: Software packet processing on NetFPGA-10G in a virtualized networking environment demonstration abstract}, booktitle = {23rd International Conference on Field programmable Logic and Applications, {FPL} 2013, Porto, Portugal, September 2-4, 2013}, pages = {1}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPL.2013.6645624}, doi = {10.1109/FPL.2013.6645624}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/BymaSC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/WillenbergC13, author = {Ruediger Willenberg and Paul Chow}, title = {Simulation-based {HW/SW} co-debugging for field-programmable systems-on-chip}, booktitle = {23rd International Conference on Field programmable Logic and Applications, {FPL} 2013, Porto, Portugal, September 2-4, 2013}, pages = {1--8}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPL.2013.6645542}, doi = {10.1109/FPL.2013.6645542}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/WillenbergC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/WillenbergC13a, author = {Ruediger Willenberg and Paul Chow}, title = {SimXMD: Simulation-based {HW/SW} co-debugging}, booktitle = {23rd International Conference on Field programmable Logic and Applications, {FPL} 2013, Porto, Portugal, September 2-4, 2013}, pages = {1}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPL.2013.6645632}, doi = {10.1109/FPL.2013.6645632}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/WillenbergC13a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/Chow13, author = {Paul Chow}, title = {Why Put FPGAs in your {CPU} socket?}, booktitle = {2013 International Conference on Field-Programmable Technology, {FPT} 2013, Kyoto, Japan, December 9-11, 2013}, pages = {3}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPT.2013.6718320}, doi = {10.1109/FPT.2013.6718320}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/Chow13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/LinC13, author = {Zhongduo Lin and Paul Chow}, title = {ZCluster: {A} Zynq-based Hadoop cluster}, booktitle = {2013 International Conference on Field-Programmable Technology, {FPT} 2013, Kyoto, Japan, December 9-11, 2013}, pages = {450--453}, publisher = {{IEEE}}, year = {2013}, url = {https://doi.org/10.1109/FPT.2013.6718411}, doi = {10.1109/FPT.2013.6718411}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/LinC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ijrc/SaldanaPLC12, author = {Manuel Salda{\~{n}}a and Arun Patel and Hao Jun Liu and Paul Chow}, title = {Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms}, journal = {Int. J. Reconfigurable Comput.}, volume = {2012}, pages = {127302:1--127302:10}, year = {2012}, url = {https://doi.org/10.1155/2012/127302}, doi = {10.1155/2012/127302}, timestamp = {Thu, 02 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ijrc/SaldanaPLC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/MirianC12, author = {Vincent Mirian and Paul Chow}, editor = {Katherine Compton and Brad L. Hutchings}, title = {FCache: a system for cache coherent processing on FPGAs}, booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA, February 22-24, 2012}, pages = {233--236}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2145694.2145733}, doi = {10.1145/2145694.2145733}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/MirianC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ChinC12, author = {S. Alexander Chin and Paul Chow}, editor = {Katherine Compton and Brad L. Hutchings}, title = {OpenCL memory infrastructure for FPGAs (abstract only)}, booktitle = {Proceedings of the {ACM/SIGDA} 20th International Symposium on Field Programmable Gate Arrays, {FPGA} 2012, Monterey, California, USA, February 22-24, 2012}, pages = {269--270}, publisher = {{ACM}}, year = {2012}, url = {https://doi.org/10.1145/2145694.2145756}, doi = {10.1145/2145694.2145756}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ChinC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LinLC12, author = {Zhongduo Lin and Charles Lo and Paul Chow}, editor = {Dirk Koch and Satnam Singh and Jim T{\o}rresen}, title = {K-means implementation on {FPGA} for high-dimensional data using triangle inequality}, booktitle = {22nd International Conference on Field Programmable Logic and Applications (FPL), Oslo, Norway, August 29-31, 2012}, pages = {437--442}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/FPL.2012.6339141}, doi = {10.1109/FPL.2012.6339141}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/LinLC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/MirianC12, author = {Vincent Mirian and Paul Chow}, title = {Managing mutex variables in a cache-coherent shared-memory system for FPGAs}, booktitle = {2012 International Conference on Field-Programmable Technology, {FPT} 2012, Seoul, Korea (South), December 10-12, 2012}, pages = {43--46}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/FPT.2012.6412109}, doi = {10.1109/FPT.2012.6412109}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/MirianC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/LoC12, author = {Charles Lo and Paul Chow}, title = {A high-performance architecture for training Viola-Jones object detectors}, booktitle = {2012 International Conference on Field-Programmable Technology, {FPT} 2012, Seoul, Korea (South), December 10-12, 2012}, pages = {174--181}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/FPT.2012.6412131}, doi = {10.1109/FPT.2012.6412131}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/LoC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/LiCJZW12, author = {Yuan Li and Paul Chow and Jiang Jiang and Minxuan Zhang and Shaojun Wei}, title = {Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method}, booktitle = {2012 International Conference on Field-Programmable Technology, {FPT} 2012, Seoul, Korea (South), December 10-12, 2012}, pages = {190--197}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/FPT.2012.6412133}, doi = {10.1109/FPT.2012.6412133}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/LiCJZW12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/WillenbergC12, author = {Ruediger Willenberg and Paul Chow}, title = {SimXMD: Integrated debugging of {C} code and hardware components}, booktitle = {2012 International Conference on Field-Programmable Technology, {FPT} 2012, Seoul, Korea (South), December 10-12, 2012}, pages = {309--312}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/FPT.2012.6412154}, doi = {10.1109/FPT.2012.6412154}, timestamp = {Wed, 24 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpt/WillenbergC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/MirianC12, author = {Vincent Mirian and Paul Chow}, title = {An implementation of a directory protocol for a cache coherent system on FPGAs}, booktitle = {2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, Cancun, Mexico, December 5-7, 2012}, pages = {1--6}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/ReConFig.2012.6416731}, doi = {10.1109/RECONFIG.2012.6416731}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/reconfig/MirianC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/KaganovLC11, author = {Alexander Kaganov and Asif Lakhany and Paul Chow}, title = {{FPGA} Acceleration of MultiFactor {CDO} Pricing}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {4}, number = {2}, pages = {20:1--20:17}, year = {2011}, url = {https://doi.org/10.1145/1968502.1968511}, doi = {10.1145/1968502.1968511}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/KaganovLC11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/ShannonC11, author = {Lesley Shannon and Paul Chow}, title = {Leveraging reconfigurability in the hardware/software codesign process}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {4}, number = {3}, pages = {28:1--28:27}, year = {2011}, url = {https://doi.org/10.1145/2000832.2000840}, doi = {10.1145/2000832.2000840}, timestamp = {Fri, 24 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/ShannonC11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/LoC11, author = {Charles Lo and Paul Chow}, editor = {John Wawrzynek and Katherine Compton}, title = {Building a multi-FPGA virtualized restricted boltzmann machine architecture using embedded {MPI}}, booktitle = {Proceedings of the {ACM/SIGDA} 19th International Symposium on Field Programmable Gate Arrays, {FPGA} 2011, Monterey, California, USA, February 27, March 1, 2011}, pages = {189--198}, publisher = {{ACM}}, year = {2011}, url = {https://doi.org/10.1145/1950413.1950452}, doi = {10.1145/1950413.1950452}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/LoC11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LiCJZ11, author = {Yuan Li and Paul Chow and Jiang Jiang and Minxuan Zhang}, title = {Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the {WELL} Method}, booktitle = {International Conference on Field Programmable Logic and Applications, {FPL} 2011, September 5-7, Chania, Crete, Greece}, pages = {110--115}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/FPL.2011.29}, doi = {10.1109/FPL.2011.29}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/LiCJZ11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/PengSC11, author = {Yuanxi Peng and Manuel Salda{\~{n}}a and Paul Chow}, title = {Hardware Support for Broadcast and Reduce in MPSoC}, booktitle = {International Conference on Field Programmable Logic and Applications, {FPL} 2011, September 5-7, Chania, Crete, Greece}, pages = {144--150}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://doi.org/10.1109/FPL.2011.34}, doi = {10.1109/FPL.2011.34}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/PengSC11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/fccm/2011, editor = {Paul Chow and Michael J. Wirthlin}, title = {{IEEE} 19th Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2011, Salt Lake City, Utah, USA, 1-3 May 2011}, publisher = {{IEEE} Computer Society}, year = {2011}, url = {https://ieeexplore.ieee.org/xpl/conhome/5771180/proceeding}, isbn = {978-0-7695-4301-7}, timestamp = {Wed, 16 Oct 2019 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/2011.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tnn/LyC10, author = {Daniel Le Ly and Paul Chow}, title = {High-Performance Reconfigurable Hardware Architecture for Restricted Boltzmann Machines}, journal = {{IEEE} Trans. Neural Networks}, volume = {21}, number = {11}, pages = {1780--1792}, year = {2010}, url = {https://doi.org/10.1109/TNN.2010.2073481}, doi = {10.1109/TNN.2010.2073481}, timestamp = {Wed, 14 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tnn/LyC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/trets/SaldanaPMNWCWSP10, author = {Manuel Salda{\~{n}}a and Arun Patel and Christopher A. Madill and Daniel Nunes and Danyao Wang and Paul Chow and Ralph Wittig and Henry Styles and Andrew Putnam}, title = {{MPI} as a Programming Model for High-Performance Reconfigurable Computers}, journal = {{ACM} Trans. Reconfigurable Technol. Syst.}, volume = {3}, number = {4}, pages = {22:1--22:29}, year = {2010}, url = {https://doi.org/10.1145/1862648.1862652}, doi = {10.1145/1862648.1862652}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/trets/SaldanaPMNWCWSP10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/HouseSC10, author = {Andrew W. H. House and Manuel Salda{\~{n}}a and Paul Chow}, editor = {Ron Sass and Russell Tessier}, title = {Integrating High-Level Synthesis into {MPI}}, booktitle = {18th {IEEE} Annual International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2010, Charlotte, North Carolina, USA, 2-4 May 2010}, pages = {175--178}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/FCCM.2010.34}, doi = {10.1109/FCCM.2010.34}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/HouseSC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/GuptaC10, author = {Dharmendra P. Gupta and Paul Chow}, editor = {Peter Y. K. Cheung and John Wawrzynek}, title = {Acceleration of an analytical approach to collateralized debt obligation pricing}, booktitle = {Proceedings of the {ACM/SIGDA} 18th International Symposium on Field Programmable Gate Arrays, {FPGA} 2010, Monterey, California, USA, February 21-23, 2010}, pages = {103--106}, publisher = {{ACM}}, year = {2010}, url = {https://doi.org/10.1145/1723112.1723130}, doi = {10.1145/1723112.1723130}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/GuptaC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/SaldanaPLC10, author = {Manuel Salda{\~{n}}a and Arun Patel and Hao Jun Liu and Paul Chow}, editor = {Viktor K. Prasanna and J{\"{u}}rgen Becker and Ren{\'{e}} Cumplido}, title = {Using Partial Reconfiguration in an Embedded Message-Passing System}, booktitle = {ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 13-15 December 2010, Proceedings}, pages = {418--423}, publisher = {{IEEE} Computer Society}, year = {2010}, url = {https://doi.org/10.1109/ReConFig.2010.37}, doi = {10.1109/RECONFIG.2010.37}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/reconfig/SaldanaPLC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/tridentcom/BannazadehLRTKMDC10, author = {Hadi Bannazadeh and Alberto Leon{-}Garcia and Keith Redmond and Gordon Tam and Arbab Khan and Mingliang Ma and Saleh Dani and Paul Chow}, editor = {Thomas Magedanz and Anastasius Gavras and Huu{-}Thanh Nguyen and Jeffrey S. Chase}, title = {Virtualized Application Networking Infrastructure}, booktitle = {Testbeds and Research Infrastructures. Development of Networks and Communities - 6th International {ICST} Conference, TridentCom 2010, Berlin, Germany, May 18-20, 2010, Revised Selected Papers}, series = {Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering}, volume = {46}, pages = {363--382}, publisher = {Springer}, year = {2010}, url = {https://doi.org/10.1007/978-3-642-17851-1\_29}, doi = {10.1007/978-3-642-17851-1\_29}, timestamp = {Thu, 09 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/tridentcom/BannazadehLRTKMDC10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ijrc/SaldanaRC09, author = {Manuel Salda{\~{n}}a and Emanuel Ramalho and Paul Chow}, title = {A Message-Passing Hardware/Software Cosimulation Environment for Reconfigurable Computing Systems}, journal = {Int. J. Reconfigurable Comput.}, volume = {2009}, pages = {376232:1--376232:9}, year = {2009}, url = {https://doi.org/10.1155/2009/376232}, doi = {10.1155/2009/376232}, timestamp = {Thu, 02 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ijrc/SaldanaRC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/LuuRLCLR09, author = {Jason Luu and Keith Redmond and William Lo and Paul Chow and Lothar Lilge and Jonathan Rose}, editor = {Kenneth L. Pocek and Duncan A. Buell}, title = {FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy}, booktitle = {{FCCM} 2009, 17th {IEEE} Symposium on Field Programmable Custom Computing Machines, Napa, California, USA, 5-7 April 2009, Proceedings}, pages = {157--164}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/FCCM.2009.24}, doi = {10.1109/FCCM.2009.24}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/LuuRLCLR09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/LyC09, author = {Daniel Le Ly and Paul Chow}, editor = {Paul Chow and Peter Y. K. Cheung}, title = {A high-performance {FPGA} architecture for restricted boltzmann machines}, booktitle = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA, February 22-24, 2009}, pages = {73--82}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1508128.1508140}, doi = {10.1145/1508128.1508140}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/LyC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/LyC09, author = {Daniel Le Ly and Paul Chow}, editor = {Martin Danek and Jiri Kadlec and Brent E. Nelson}, title = {A multi-FPGA architecture for stochastic Restricted Boltzmann Machines}, booktitle = {19th International Conference on Field Programmable Logic and Applications, {FPL} 2009, August 31 - September 2, 2009, Prague, Czech Republic}, pages = {168--173}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/FPL.2009.5272516}, doi = {10.1109/FPL.2009.5272516}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/LyC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/LySC09, author = {Daniel Le Ly and Manuel Salda{\~{n}}a and Paul Chow}, editor = {Neil W. Bergmann and Oliver Diessel and Lesley Shannon}, title = {The challenges of using an embedded {MPI} for hardware-based processing nodes}, booktitle = {Proceedings of the 2009 International Conference on Field-Programmable Technology, {FPT} 2009, Sydney, Australia, December 9-11, 2009}, pages = {120--127}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/FPT.2009.5377688}, doi = {10.1109/FPT.2009.5377688}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/LySC09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hotchips/ChowSPM09, author = {Paul Chow and Manuel Salda{\~{n}}a and Arun Patel and Christopher A. Madill}, title = {Programming the Nallatech Xeon + multi-FPGA heterogeneous platform}, booktitle = {2009 {IEEE} Hot Chips 21 Symposium (HCS), Stanford, CA, USA, August 23-25, 2009}, pages = {1--16}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.ieeecomputersociety.org/10.1109/HOTCHIPS.2009.7478369}, doi = {10.1109/HOTCHIPS.2009.7478369}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hotchips/ChowSPM09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/JiangMTCX09, author = {Jiang Jiang and Vincent Mirian and Kam Pui Tang and Paul Chow and Zuocheng Xing}, editor = {Viktor K. Prasanna and Lionel Torres and Ren{\'{e}} Cumplido}, title = {Matrix Multiplication Based on Scalable Macro-Pipelined {FPGA} Accelerator Architecture}, booktitle = {ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, Cancun, Quintana Roo, Mexico, 9-11 December 2009, Proceedings}, pages = {48--53}, publisher = {{IEEE} Computer Society}, year = {2009}, url = {https://doi.org/10.1109/ReConFig.2009.30}, doi = {10.1109/RECONFIG.2009.30}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/reconfig/JiangMTCX09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/fpga/2009, editor = {Paul Chow and Peter Y. K. Cheung}, title = {Proceedings of the {ACM/SIGDA} 17th International Symposium on Field Programmable Gate Arrays, {FPGA} 2009, Monterey, California, USA, February 22-24, 2009}, publisher = {{ACM}}, year = {2009}, url = {https://doi.org/10.1145/1508128}, doi = {10.1145/1508128}, isbn = {978-1-60558-410-2}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/2009.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tecs/AamodtC08, author = {Tor M. Aamodt and Paul Chow}, title = {Compile-time and instruction-set methods for improving floating- to fixed-point conversion accuracy}, journal = {{ACM} Trans. Embed. Comput. Syst.}, volume = {7}, number = {3}, pages = {26:1--26:27}, year = {2008}, url = {https://doi.org/10.1145/1347375.1347379}, doi = {10.1145/1347375.1347379}, timestamp = {Tue, 08 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tecs/AamodtC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/HouseC08, author = {Andrew W. H. House and Paul Chow}, editor = {Kenneth L. Pocek and Duncan A. Buell}, title = {Investigation of Programming Models for Emerging FPGA-Based High Performance Computing Systems}, booktitle = {16th {IEEE} International Symposium on Field-Programmable Custom Computing Machines, {FCCM} 2008, 14-15 April 2008, Stanford, Palo Alto, California, {USA}}, pages = {291--292}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/FCCM.2008.38}, doi = {10.1109/FCCM.2008.38}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/HouseC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/KaganovCL08, author = {Alexander Kaganov and Paul Chow and Asif Lakhany}, title = {{FPGA} acceleration of Monte-Carlo based credit derivative pricing}, booktitle = {{FPL} 2008, International Conference on Field Programmable Logic and Applications, Heidelberg, Germany, 8-10 September 2008}, pages = {329--334}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPL.2008.4629953}, doi = {10.1109/FPL.2008.4629953}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/KaganovCL08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/NunesSC08, author = {Daniel Nunes and Manuel Salda{\~{n}}a and Paul Chow}, editor = {Tarek A. El{-}Ghazawi and Yao{-}Wen Chang and Juinn{-}Dar Huang and Proshanta Saha}, title = {A profiler for a heterogeneous multi-core multi-FPGA system}, booktitle = {2008 International Conference on Field-Programmable Technology, {FPT} 2008, Taipei, Taiwan, December 7-10, 2008}, pages = {113--120}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/FPT.2008.4762373}, doi = {10.1109/FPT.2008.4762373}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/fpt/NunesSC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/SaldanaRC08, author = {Manuel Salda{\~{n}}a and Emanuel Ramalho and Paul Chow}, title = {A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using {TMD-MPI}}, booktitle = {ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 3-5 December 2008, Cancun, Mexico, Proceedings}, pages = {265--270}, publisher = {{IEEE} Computer Society}, year = {2008}, url = {https://doi.org/10.1109/ReConFig.2008.10}, doi = {10.1109/RECONFIG.2008.10}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/reconfig/SaldanaRC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sc/SaldanaPMNWSPWC08, author = {Manuel Salda{\~{n}}a and Arun Patel and Christopher A. Madill and Daniel Nunes and Danyao Wang and Henry Styles and Andrew Putnam and Ralph Wittig and Paul Chow}, title = {{MPI} as an abstraction for software-hardware interaction for HPRCs}, booktitle = {2008 Second International Workshop on High-Performance Reconfigurable Computing Technology and Applications, HPRCTA@SC 2008, Austin, TX, USA, November 17, 2008}, pages = {1--10}, publisher = {{IEEE}}, year = {2008}, url = {https://doi.org/10.1109/HPRCTA.2008.4745682}, doi = {10.1109/HPRCTA.2008.4745682}, timestamp = {Sun, 12 Feb 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/sc/SaldanaPMNWSPWC08.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@proceedings{DBLP:conf/fpga/2008, editor = {Mike Hutton and Paul Chow}, title = {Proceedings of the {ACM/SIGDA} 16th International Symposium on Field Programmable Gate Arrays, {FPGA} 2008, Monterey, California, USA, February 24-26, 2008}, publisher = {{ACM}}, year = {2008}, url = {https://doi.org/10.1145/1344671}, doi = {10.1145/1344671}, isbn = {978-1-59593-934-0}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/2008.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ShannonC07, author = {Lesley Shannon and Paul Chow}, title = {{SIMPPL:} An Adaptable SoC Framework Using a Programmable Controller {IP} Interface to Facilitate Design Reuse}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {15}, number = {4}, pages = {377--390}, year = {2007}, url = {https://doi.org/10.1109/TVLSI.2007.893645}, doi = {10.1109/TVLSI.2007.893645}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/ShannonC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/SaldanaSYBCC07, author = {Manuel Salda{\~{n}}a and Lesley Shannon and Jia Shuo Yue and Sikang Bian and John Craig and Paul Chow}, title = {Routability of Network Topologies in FPGAs}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {15}, number = {8}, pages = {948--951}, year = {2007}, url = {https://doi.org/10.1109/TVLSI.2007.900746}, doi = {10.1109/TVLSI.2007.900746}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/SaldanaSYBCC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cicc/ParikhGC07, author = {Samir Parikh and P. Glenn Gulak and Paul Chow}, title = {A {CMOS} Image Sensor for {DNA} Microarrays}, booktitle = {Proceedings of the {IEEE} 2007 Custom Integrated Circuits Conference, {CICC} 2007, DoubleTree Hotel, San Jose, California, USA, September 16-19, 2007}, pages = {821--824}, publisher = {{IEEE}}, year = {2007}, url = {https://doi.org/10.1109/CICC.2007.4405854}, doi = {10.1109/CICC.2007.4405854}, timestamp = {Wed, 16 Oct 2019 14:14:52 +0200}, biburl = {https://dblp.org/rec/conf/cicc/ParikhGC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ersa/LeeC07, author = {Sam Lee and Paul Chow}, editor = {Toomas P. Plaks}, title = {An {FPGA} Implementation of Reciprocal Sums for {SPME}}, booktitle = {Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems {\&} Algorithms, {ERSA} 2007, Las Vegas, Nevada, USA, June 25-28, 2007}, pages = {159--165}, publisher = {{CSREA} Press}, year = {2007}, timestamp = {Fri, 14 Dec 2007 20:45:54 +0100}, biburl = {https://dblp.org/rec/conf/ersa/LeeC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ChowH07, author = {Paul Chow and Mike Hutton}, editor = {Andr{\'{e}} DeHon and Mike Hutton}, title = {Integrating FPGAs in high-performance computing: introduction}, booktitle = {Proceedings of the {ACM/SIGDA} 15th International Symposium on Field Programmable Gate Arrays, {FPGA} 2007, Monterey, California, USA, February 18-20, 2007}, pages = {131}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1216919.1216940}, doi = {10.1145/1216919.1216940}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ChowH07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/glvlsi/ChenC07, author = {Chichyang Chen and Paul Chow}, editor = {Hai Zhou and Enrico Macii and Zhiyuan Yan and Yehia Massoud}, title = {Design of a versatile and cost-effective hybrid floating-point/LNS arithmetic processor}, booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007, Stresa, Lago Maggiore, Italy, March 11-13, 2007}, pages = {540--545}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1228784.1228912}, doi = {10.1145/1228784.1228912}, timestamp = {Wed, 16 Aug 2023 21:16:32 +0200}, biburl = {https://dblp.org/rec/conf/glvlsi/ChenC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ics/AamodtC07, author = {Tor M. Aamodt and Paul Chow}, editor = {Burton J. Smith}, title = {Optimization of data prefetch helper threads with path-expression based statistical modeling}, booktitle = {Proceedings of the 21th Annual International Conference on Supercomputing, {ICS} 2007, Seattle, Washington, USA, June 17-21, 2007}, pages = {210--221}, publisher = {{ACM}}, year = {2007}, url = {https://doi.org/10.1145/1274971.1275001}, doi = {10.1145/1274971.1275001}, timestamp = {Tue, 06 Nov 2018 11:07:02 +0100}, biburl = {https://dblp.org/rec/conf/ics/AamodtC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/PatelMSCPC06, author = {Arun Patel and Christopher A. Madill and Manuel Salda{\~{n}}a and Chris Comis and R{\'{e}}gis Pom{\`{e}}s and Paul Chow}, title = {A Scalable FPGA-based Multiprocessor}, booktitle = {14th {IEEE} Symposium on Field-Programmable Custom Computing Machines {(FCCM} 2006), 24-26 April 2006, Napa, CA, USA, Proceedings}, pages = {111--120}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/FCCM.2006.17}, doi = {10.1109/FCCM.2006.17}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/PatelMSCPC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/SaldanaSC06, author = {Manuel Salda{\~{n}}a and Lesley Shannon and Paul Chow}, editor = {Steven J. E. Wilton and Andr{\'{e}} DeHon}, title = {The routability of multiprocessor network topologies in FPGAs}, booktitle = {Proceedings of the {ACM/SIGDA} 14th International Symposium on Field Programmable Gate Arrays, {FPGA} 2006, Monterey, California, USA, February 22-24, 2006}, pages = {232}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1117201.1117253}, doi = {10.1145/1117201.1117253}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/SaldanaSC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/SaldanaC06, author = {Manuel Salda{\~{n}}a and Paul Chow}, title = {{TMD-MPI:} An {MPI} Implementation for Multiple Processors Across Multiple FPGAs}, booktitle = {Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006}, pages = {1--6}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/FPL.2006.311233}, doi = {10.1109/FPL.2006.311233}, timestamp = {Wed, 16 Oct 2019 14:14:53 +0200}, biburl = {https://dblp.org/rec/conf/fpl/SaldanaC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ShannonFPPSC06, author = {Lesley Shannon and Blair Fort and Samir Parikh and Arun Patel and Manuel Salda{\~{n}}a and Paul Chow}, title = {A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification}, booktitle = {Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006}, pages = {1--6}, publisher = {{IEEE}}, year = {2006}, url = {https://doi.org/10.1109/FPL.2006.311227}, doi = {10.1109/FPL.2006.311227}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fpl/ShannonFPPSC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/reconfig/SaldanaNRC06, author = {Manuel Salda{\~{n}}a and Daniel Nunes and Emanuel Ramalho and Paul Chow}, editor = {Ren{\'{e}} Cumplido{-}Parra and C{\'{e}}sar Torres{-}Huitzil and Andr{\'{e}}s D. Garc{\'{\i}}a}, title = {Configuration and Programming of Heterogeneous Multiprocessors on a Multi-FPGA System Using {TMD-MPI}}, booktitle = {2006 {IEEE} International Conference on Reconfigurable Computing and FPGA's, ReConFig 2006, San Luis Potosi, Mexico, September 20-22, 2006}, pages = {260--279}, publisher = {{IEEE} Computer Society}, year = {2006}, url = {https://doi.org/10.1109/RECONF.2006.307779}, doi = {10.1109/RECONF.2006.307779}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/reconfig/SaldanaNRC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/slip/SaldanaSC06, author = {Manuel Salda{\~{n}}a and Lesley Shannon and Paul Chow}, editor = {Mike Hutton and Joni Dambre}, title = {The routability of multiprocessor network topologies in FPGAs}, booktitle = {The Eigth International Workshop on System-Level Interconnect Prediction {(SLIP} 2006), Munich, Germany, March 4-5, 2006, Proceedings}, pages = {49--56}, publisher = {{ACM}}, year = {2006}, url = {https://doi.org/10.1145/1117278.1117290}, doi = {10.1145/1117278.1117290}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/slip/SaldanaSC06.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/ShannonC05, author = {Lesley Shannon and Paul Chow}, title = {Simplifying the Integration of Processing Elements in Computing Systems Using a Programmable Controller}, booktitle = {13th {IEEE} Symposium on Field-Programmable Custom Computing Machines {(FCCM} 2005), 17-20 April 2005, Napa, CA, USA, Proceedings}, pages = {63--72}, publisher = {{IEEE} Computer Society}, year = {2005}, url = {https://doi.org/10.1109/FCCM.2005.59}, doi = {10.1109/FCCM.2005.59}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/ShannonC05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpl/ShannonC05, author = {Lesley Shannon and Paul Chow}, editor = {Tero Rissa and Steven J. E. Wilton and Philip Heng Wai Leong}, title = {Leveraging Reconfigurability in the Design Process}, booktitle = {Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005}, pages = {731--732}, publisher = {{IEEE}}, year = {2005}, url = {https://doi.org/10.1109/FPL.2005.1515830}, doi = {10.1109/FPL.2005.1515830}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpl/ShannonC05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/ShannonFPPSC05, author = {Lesley Shannon and Blair Fort and Samir Parikh and Arun Patel and Manuel Salda{\~{n}}a and Paul Chow}, editor = {Gordon J. Brebner and Samarjit Chakraborty and Weng{-}Fai Wong}, title = {Designing an {FPGA} SoC Using a Standardized {IP} Block Interface}, booktitle = {Proceedings of the 2005 {IEEE} International Conference on Field-Programmable Technology, {FPT} 2005, 11-14 December 2005, Singapore}, pages = {341--342}, publisher = {{IEEE}}, year = {2005}, timestamp = {Tue, 19 Jun 2018 20:15:46 +0200}, biburl = {https://dblp.org/rec/conf/fpt/ShannonFPPSC05.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/AziziKEDC04, author = {Navid Azizi and Ian Kuon and Aaron Egier and Ahmad Darabiha and Paul Chow}, title = {Reconfigurable Molecular Dynamics Simulator}, booktitle = {12th {IEEE} Symposium on Field-Programmable Custom Computing Machines {(FCCM} 2004), 20-23 April 2004, Napa, CA, USA, Proceedings}, pages = {197--206}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/FCCM.2004.48}, doi = {10.1109/FCCM.2004.48}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/AziziKEDC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ShannonC04, author = {Lesley Shannon and Paul Chow}, editor = {Russell Tessier and Herman Schmit}, title = {Using reconfigurability to achieve real-time profiling for hardware/software codesign}, booktitle = {Proceedings of the {ACM/SIGDA} 12th International Symposium on Field Programmable Gate Arrays, {FPGA} 2004, Monterey, California, USA, February 22-24, 2004}, pages = {190--199}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/968280.968308}, doi = {10.1145/968280.968308}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ShannonC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/KuonADEC04, author = {Ian Kuon and Navid Azizi and Ahmad Darabiha and Aaron Egier and Paul Chow}, editor = {Russell Tessier and Herman Schmit}, title = {FPGA-based supercomputing: an implementation for molecular dynamics}, booktitle = {Proceedings of the {ACM/SIGDA} 12th International Symposium on Field Programmable Gate Arrays, {FPGA} 2004, Monterey, California, USA, February 22-24, 2004}, pages = {253}, publisher = {{ACM}}, year = {2004}, url = {https://doi.org/10.1145/968280.968340}, doi = {10.1145/968280.968340}, timestamp = {Tue, 06 Nov 2018 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fpga/KuonADEC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpt/ShannonC04, author = {Lesley Shannon and Paul Chow}, editor = {Oliver Diessel and John Williams}, title = {Maximizing system performance: using reconfigurability to monitor system communications}, booktitle = {Proceedings of the 2004 {IEEE} International Conference on Field-Programmable Technology, Brisbane, Australia, December 6-8, 2004}, pages = {231--238}, publisher = {{IEEE}}, year = {2004}, url = {https://doi.org/10.1109/FPT.2004.1393273}, doi = {10.1109/FPT.2004.1393273}, timestamp = {Fri, 22 Nov 2019 15:44:53 +0100}, biburl = {https://dblp.org/rec/conf/fpt/ShannonC04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/AamodtCHWS04, author = {Tor M. Aamodt and Paul Chow and Per Hammarlund and Hong Wang and John Paul Shen}, title = {Hardware Support for Prescient Instruction Prefetch}, booktitle = {10th International Conference on High-Performance Computer Architecture {(HPCA-10} 2004), 14-18 February 2004, Madrid, Spain}, pages = {84--95}, publisher = {{IEEE} Computer Society}, year = {2004}, url = {https://doi.org/10.1109/HPCA.2004.10028}, doi = {10.1109/HPCA.2004.10028}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/AamodtCHWS04.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/ShannonC03, author = {Lesley Shannon and Paul Chow}, title = {Standardizing the Performance Assessment of Reconfigurable Processor Architectures}, booktitle = {11th {IEEE} Symposium on Field-Programmable Custom Computing Machines {(FCCM} 2003), 8-11 April 2003, Napa, CA, USA, Proceedings}, pages = {282--283}, publisher = {{IEEE} Computer Society}, year = {2003}, url = {https://doi.org/10.1109/FPGA.2003.1227271}, doi = {10.1109/FPGA.2003.1227271}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/fccm/ShannonC03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/sigmetrics/AamodtMCGHWS03, author = {Tor M. Aamodt and Pedro Marcuello and Paul Chow and Antonio Gonz{\'{a}}lez and Per Hammarlund and Hong Wang and John Paul Shen}, editor = {Bill Cheng and Satish K. Tripathi and Jennifer Rexford and William H. Sanders}, title = {A framework for modeling and optimization of prescient instruction prefetch}, booktitle = {Proceedings of the International Conference on Measurements and Modeling of Computer Systems, {SIGMETRICS} 2003, June 9-14, 2003, San Diego, CA, {USA}}, pages = {13--24}, publisher = {{ACM}}, year = {2003}, url = {https://doi.org/10.1145/781027.781030}, doi = {10.1145/781027.781030}, timestamp = {Thu, 23 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/sigmetrics/AamodtMCGHWS03.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/CarrilloC01, author = {Jorge E. Carrillo and Paul Chow}, editor = {Scott Hauck and Martine D. F. Schlag and Russell Tessier}, title = {The effect of reconfigurable units in superscalar processors}, booktitle = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001}, pages = {141--150}, publisher = {{ACM}}, year = {2001}, url = {https://doi.org/10.1145/360276.360328}, doi = {10.1145/360276.360328}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/CarrilloC01.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/micro/ZhangBHCL00, author = {L. Louis Zhang and Brent Beacham and Massoud R. Hashemi and Paul Chow and Alberto Leon{-}Garcia}, title = {A Scheduler {ASIC} for a Programmable Packet Switch}, journal = {{IEEE} Micro}, volume = {20}, number = {1}, pages = {42--48}, year = {2000}, url = {https://doi.org/10.1109/40.820052}, doi = {10.1109/40.820052}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/micro/ZhangBHCL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cases/AamodtC00, author = {Tor M. Aamodt and Paul Chow}, title = {Embedded {ISA} support for enhanced floating-point to fixed-point {ANSI-C} compilation}, booktitle = {Proceedings of the 2000 International Conference on Compilers, Architectures and Synthesis for Embedded Systems, {CASES} 2000, San Jose, California, USA, November 7-18, 2000}, pages = {128--137}, publisher = {{ACM}}, year = {2000}, url = {https://doi.org/10.1145/354880.354899}, doi = {10.1145/354880.354899}, timestamp = {Tue, 06 Nov 2018 11:07:42 +0100}, biburl = {https://dblp.org/rec/conf/cases/AamodtC00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ijpp/FarkasCJV99, author = {Keith I. Farkas and Paul Chow and Norman P. Jouppi and Zvonko G. Vranesic}, title = {The Multicluster Architecture: Reducing Processor Cycle Time Through Partitioning}, journal = {Int. J. Parallel Program.}, volume = {27}, number = {5}, pages = {327--356}, year = {1999}, url = {https://doi.org/10.1023/A:1018782806674}, doi = {10.1023/A:1018782806674}, timestamp = {Wed, 01 Apr 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/ijpp/FarkasCJV99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChowSRCPR99, author = {Paul Chow and Soon Ong Seo and Jonathan Rose and Kevin Chung and Gerard P{\'{a}}ez{-}Monz{\'{o}}n and Immanuel Rahardja}, title = {The design of an SRAM-based field-programmable gate array. I. Architecture}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {7}, number = {2}, pages = {191--197}, year = {1999}, url = {https://doi.org/10.1109/92.766746}, doi = {10.1109/92.766746}, timestamp = {Mon, 11 May 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/ChowSRCPR99a, author = {Paul Chow and Soon Ong Seo and Jonathan Rose and Kevin Chung and Gerard P{\'{a}}ez{-}Monz{\'{o}}n and Immanuel Rahardja}, title = {The design of a SRAM-based field-programmable gate array-Part {II:} Circuit design and layout}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {7}, number = {3}, pages = {321--330}, year = {1999}, url = {https://doi.org/10.1109/92.784093}, doi = {10.1109/92.784093}, timestamp = {Wed, 14 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tvlsi/ChowSRCPR99a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/ches/HamerC99, author = {Ivan Hamer and Paul Chow}, editor = {{\c{C}}etin Kaya Ko{\c{c}} and Christof Paar}, title = {{DES} Cracking on the Transmogrifier 2a}, booktitle = {Cryptographic Hardware and Embedded Systems, First International Workshop, CHES'99, Worcester, MA, USA, August 12-13, 1999, Proceedings}, series = {Lecture Notes in Computer Science}, volume = {1717}, pages = {13--24}, publisher = {Springer}, year = {1999}, url = {https://doi.org/10.1007/3-540-48059-5\_3}, doi = {10.1007/3-540-48059-5\_3}, timestamp = {Tue, 14 May 2019 10:00:47 +0200}, biburl = {https://dblp.org/rec/conf/ches/HamerC99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/JacobC99, author = {Jeffrey A. Jacob and Paul Chow}, editor = {Sinan Kaptanoglu and Steve Trimberger}, title = {Memory Interfacing and Instruction Specification for Reconfigurable Processors}, booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA, February 21-23, 1999}, pages = {145--154}, publisher = {{ACM}}, year = {1999}, url = {https://doi.org/10.1145/296399.296446}, doi = {10.1145/296399.296446}, timestamp = {Tue, 06 Nov 2018 16:58:22 +0100}, biburl = {https://dblp.org/rec/conf/fpga/JacobC99.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tvlsi/LewisGIRC98, author = {David M. Lewis and David R. Galloway and Marcus van Ierssel and Jonathan Rose and Paul Chow}, title = {The Transmogrifier-2: a 1 million gate rapid-prototyping system}, journal = {{IEEE} Trans. Very Large Scale Integr. Syst.}, volume = {6}, number = {2}, pages = {188--198}, year = {1998}, url = {https://doi.org/10.1109/92.678867}, doi = {10.1109/92.678867}, timestamp = {Wed, 11 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tvlsi/LewisGIRC98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/LewisGIRC97, author = {David M. Lewis and David R. Galloway and Marcus van Ierssel and Jonathan Rose and Paul Chow}, editor = {Carl Ebeling}, title = {The Transmogrifier-2: {A} 1 Million Gate Rapid Prototyping System}, booktitle = {Proceedings of the 1997 {ACM/SIGDA} Fifth International Symposium on Field Programmable Gate Arrays, {FPGA} 1997, Monterey, CA, USA, February 9-11, 1997}, pages = {53--61}, publisher = {{ACM}}, year = {1997}, url = {https://doi.org/10.1145/258305.258312}, doi = {10.1145/258305.258312}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/LewisGIRC97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/FarkasCJV97, author = {Keith I. Farkas and Paul Chow and Norman P. Jouppi and Zvonko G. Vranesic}, editor = {Andrew R. Pleszkun and Trevor N. Mudge}, title = {Memory-System Design Considerations for Dynamically-Scheduled Processors}, booktitle = {Proceedings of the 24th International Symposium on Computer Architecture, Denver, Colorado, USA, June 2-4, 1997}, pages = {133--143}, publisher = {{ACM}}, year = {1997}, url = {https://doi.org/10.1145/264107.264156}, doi = {10.1145/264107.264156}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/isca/FarkasCJV97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/micro/FarkasCJV97, author = {Keith I. Farkas and Paul Chow and Norman P. Jouppi and Zvonko G. Vranesic}, editor = {Mark Smotherman and Tom Conte}, title = {The Multicluster Architecture: Reducing Cycle Time Through Partitioning}, booktitle = {Proceedings of the Thirtieth Annual {IEEE/ACM} International Symposium on Microarchitecture, {MICRO} 30, Research Triangle Park, North Carolina, USA, December 1-3, 1997}, pages = {149--159}, publisher = {{ACM/IEEE} Computer Society}, year = {1997}, url = {https://doi.org/10.1109/MICRO.1997.645806}, doi = {10.1109/MICRO.1997.645806}, timestamp = {Tue, 31 May 2022 14:39:58 +0200}, biburl = {https://dblp.org/rec/conf/micro/FarkasCJV97.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/asplos/SaghirCL96, author = {Mazen A. R. Saghir and Paul Chow and Corinna G. Lee}, editor = {Bill Dally and Susan J. Eggers}, title = {Exploiting Dual Data-Memory Banks in Digital Signal Processors}, booktitle = {{ASPLOS-VII} Proceedings - Seventh International Conference on Architectural Support for Programming Languages and Operating Systems, Cambridge, Massachusetts, USA, October 1-5, 1996}, pages = {234--243}, publisher = {{ACM} Press}, year = {1996}, url = {https://doi.org/10.1145/237090.237193}, doi = {10.1145/237090.237193}, timestamp = {Wed, 07 Jul 2021 13:23:09 +0200}, biburl = {https://dblp.org/rec/conf/asplos/SaghirCL96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/YehFC96, author = {David Yeh and Gennady Feygin and Paul Chow}, title = {{RACER:} a reconfigurable constraint-length 14 Viterbi decoder}, booktitle = {4th {IEEE} Symposium on FPGAs for Custom Computing Machines {(FCCM} '96), Napa Valley, CA, USA, April 17-19, 1996}, pages = {60--69}, publisher = {{IEEE}}, year = {1996}, url = {https://doi.org/10.1109/FPGA.1996.564746}, doi = {10.1109/FPGA.1996.564746}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/fccm/YehFC96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fccm/WittigC96, author = {Ralph Wittig and Paul Chow}, title = {OneChip: an {FPGA} processor with reconfigurable logic}, booktitle = {4th {IEEE} Symposium on FPGAs for Custom Computing Machines {(FCCM} '96), Napa Valley, CA, USA, April 17-19, 1996}, pages = {126--135}, publisher = {{IEEE}}, year = {1996}, url = {https://doi.org/10.1109/FPGA.1996.564773}, doi = {10.1109/FPGA.1996.564773}, timestamp = {Sun, 21 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/fccm/WittigC96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/FarkasJC96, author = {Keith I. Farkas and Norman P. Jouppi and Paul Chow}, title = {Register File Design Considerations in Dynamically Scheduled Processors}, booktitle = {Proceedings of the Second International Symposium on High-Performance Computer Architecture, San Jose, CA, USA, February 3-7, 1996}, pages = {40--51}, publisher = {{IEEE} Computer Society}, year = {1996}, url = {https://doi.org/10.1109/HPCA.1996.501172}, doi = {10.1109/HPCA.1996.501172}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/FarkasJC96.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/fpga/ChowGC95, author = {Paul Chow and P. Glenn Gulak}, editor = {Pak K. Chan and Jonathan Rose}, title = {A Field-Programmable Mixed-Analog-Digital Array}, booktitle = {Proceedings of the Third International {ACM} Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995}, pages = {104--109}, publisher = {{ACM}}, year = {1995}, url = {https://doi.org/10.1145/201310.201327}, doi = {10.1145/201310.201327}, timestamp = {Tue, 06 Nov 2018 16:58:23 +0100}, biburl = {https://dblp.org/rec/conf/fpga/ChowGC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/hpca/FarkasJC95, author = {Keith I. Farkas and Norman P. Jouppi and Paul Chow}, title = {How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors?}, booktitle = {Proceedings of the 1st {IEEE} Symposium on High-Performance Computer Architecture {(HPCA} 1995), Raleigh, North Carolina, USA, January 22-25, 1995}, pages = {78--89}, publisher = {{IEEE} Computer Society}, year = {1995}, url = {https://doi.org/10.1109/HPCA.1995.386553}, doi = {10.1109/HPCA.1995.386553}, timestamp = {Fri, 24 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/hpca/FarkasJC95.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/ipm/FeyginGC94, author = {Gennady Feygin and P. Glenn Gulak and Paul Chow}, title = {Minimizing Excess Code Length and {VLSI} Complexity in the Multiplication Free Approximation of Arithmetic Coding}, journal = {Inf. Process. Manag.}, volume = {30}, number = {6}, pages = {805--816}, year = {1994}, url = {https://doi.org/10.1016/0306-4573(94)90008-6}, doi = {10.1016/0306-4573(94)90008-6}, timestamp = {Fri, 21 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/ipm/FeyginGC94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dcc/FeyginGC94, author = {Gennady Feygin and P. Glenn Gulak and Paul Chow}, editor = {James A. Storer and Martin Cohn}, title = {Architectural Advances in the {VLSI} Implementation of Arithmetic Coding for Binary Image Compression}, booktitle = {Proceedings of the {IEEE} Data Compression Conference, {DCC} 1994, Snowbird, Utah, USA, March 29-31, 1994}, pages = {254--263}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/DCC.1994.305933}, doi = {10.1109/DCC.1994.305933}, timestamp = {Wed, 16 Oct 2019 14:14:57 +0200}, biburl = {https://dblp.org/rec/conf/dcc/FeyginGC94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icassp/SaghirCL94, author = {Mazen A. R. Saghir and Paul Chow and Corinna G. Lee}, title = {Application-driven design of {DSP} architectures and compilers}, booktitle = {Proceedings of {ICASSP} '94: {IEEE} International Conference on Acoustics, Speech and Signal Processing, Adelaide, South Australia, Australia, April 19-22, 1994}, pages = {437--440}, publisher = {{IEEE} Computer Society}, year = {1994}, url = {https://doi.org/10.1109/ICASSP.1994.389627}, doi = {10.1109/ICASSP.1994.389627}, timestamp = {Thu, 23 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/conf/icassp/SaghirCL94.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tsp/FeyginGC93, author = {Gennady Feygin and Patrick Glenn Gulak and Paul Chow}, title = {A multiprocessor architecture for Viterbi decoders with linear speedup}, journal = {{IEEE} Trans. Signal Process.}, volume = {41}, number = {9}, pages = {2907--2917}, year = {1993}, url = {https://doi.org/10.1109/78.236512}, doi = {10.1109/78.236512}, timestamp = {Tue, 10 Mar 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tsp/FeyginGC93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/dcc/FeyginGC93, author = {Gennady Feygin and P. Glenn Gulak and Paul Chow}, editor = {James A. Storer and Martin Cohn}, title = {Minimizing Error and {VLSI} Complexity in the Multiplication-Free Approximation of Arithmetic Coding}, booktitle = {Proceedings of the {IEEE} Data Compression Conference, {DCC} 1993, Snowbird, Utah, USA, March 30 - April 1, 1993}, pages = {118--127}, publisher = {{IEEE} Computer Society}, year = {1993}, url = {https://doi.org/10.1109/DCC.1993.253138}, doi = {10.1109/DCC.1993.253138}, timestamp = {Wed, 16 Oct 2019 14:14:57 +0200}, biburl = {https://dblp.org/rec/conf/dcc/FeyginGC93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/iscas/FeyginCGCGHSSSW93, author = {Gennady Feygin and Paul Chow and P. Glenn Gulak and John Chappel and Grant Goodes and Oswin Hall and Ahmad Sayes and Satwant Singh and Michael B. Smith and Steven J. E. Wilton}, title = {A {VLSI} Implementation of a Cascade Viterbi Decoder with Traceback}, booktitle = {1993 {IEEE} International Symposium on Circuits and Systems, {ISCAS} 1993, Chicago, Illinois, USA, May 3-6, 1993}, pages = {1945--1948}, publisher = {{IEEE}}, year = {1993}, timestamp = {Wed, 16 Oct 2019 14:14:49 +0200}, biburl = {https://dblp.org/rec/conf/iscas/FeyginCGCGHSSSW93.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icassp/FeyginGC91, author = {Gennady Feygin and Patrick Glenn Gulak and Paul Chow}, title = {Generalized cascade Viterbi decoder-a locally connected multiprocessor with linear speed-up}, booktitle = {1991 International Conference on Acoustics, Speech, and Signal Processing, {ICASSP} '91, Toronto, Ontario, Canada, May 14-17, 1991}, pages = {1097--1100}, publisher = {{IEEE} Computer Society}, year = {1991}, url = {https://doi.org/10.1109/ICASSP.1991.150554}, doi = {10.1109/ICASSP.1991.150554}, timestamp = {Mon, 09 Aug 2021 14:54:02 +0200}, biburl = {https://dblp.org/rec/conf/icassp/FeyginGC91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/icassp/TakefmanC91, author = {Michael Takefman and Paul Chow}, title = {A streamlined {DSP} microprocessor architecture}, booktitle = {1991 International Conference on Acoustics, Speech, and Signal Processing, {ICASSP} '91, Toronto, Ontario, Canada, May 14-17, 1991}, pages = {1257--1260}, publisher = {{IEEE} Computer Society}, year = {1991}, url = {https://doi.org/10.1109/ICASSP.1991.150624}, doi = {10.1109/ICASSP.1991.150624}, timestamp = {Thu, 09 Jul 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/conf/icassp/TakefmanC91.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/isca/ChowH87, author = {Paul Chow and Mark Horowitz}, editor = {Daniel C. St. Clair}, title = {Architectural Tradeoffs in the Design of {MIPS-X}}, booktitle = {Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, PA, USA, June 1987}, pages = {300--308}, year = {1987}, url = {https://doi.org/10.1145/30350.30384}, doi = {10.1145/30350.30384}, timestamp = {Fri, 09 Jul 2021 15:51:20 +0200}, biburl = {https://dblp.org/rec/conf/isca/ChowH87.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tc/ChowVY83, author = {Paul Chow and Zvonko G. Vranesic and Jui Lin Yen}, title = {A Pipelined Distributed Arithmetic {PFFT} Processor}, journal = {{IEEE} Trans. Computers}, volume = {32}, number = {12}, pages = {1128--1136}, year = {1983}, url = {https://doi.org/10.1109/TC.1983.1676173}, doi = {10.1109/TC.1983.1676173}, timestamp = {Sat, 20 May 2017 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tc/ChowVY83.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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