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ORCIDBibTeX records: Kiyoung Choi
@inproceedings{DBLP:conf/aimech/LeeCKYKNO23,
author = {Deokjin Lee and
Kiyoung Choi and
Junyoung Kim and
Wonbum Yun and
Taehoon Kim and
Kanghyun Nam and
Sehoon Oh},
title = {ExSLeR: Development of a Robotic Arm for Human Skill Learning},
booktitle = {{IEEE/ASME} International Conference on Advanced Intelligent Mechatronics,
{AIM} 2023, Seattle, WA, USA, June 28-30, 2023},
pages = {209--214},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/AIM46323.2023.10196166},
doi = {10.1109/AIM46323.2023.10196166},
timestamp = {Mon, 14 Aug 2023 15:14:40 +0200},
biburl = {https://dblp.org/rec/conf/aimech/LeeCKYKNO23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2306-15577,
author = {Junwhan Ahn and
Sungpack Hong and
Sungjoo Yoo and
Onur Mutlu and
Kiyoung Choi},
title = {Retrospective: {A} Scalable Processing-in-Memory Accelerator for Parallel
Graph Processing},
journal = {CoRR},
volume = {abs/2306.15577},
year = {2023},
url = {https://doi.org/10.48550/arXiv.2306.15577},
doi = {10.48550/ARXIV.2306.15577},
eprinttype = {arXiv},
eprint = {2306.15577},
timestamp = {Fri, 30 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2306-15577.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/KimPLKLC22,
author = {Namhyung Kim and
Hanmin Park and
Dongwoo Lee and
Sungbum Kang and
Jinho Lee and
Kiyoung Choi},
title = {ComPreEND: Computation Pruning through Predictive Early Negative Detection
for ReLU in a Deep Neural Network Accelerator},
journal = {{IEEE} Trans. Computers},
volume = {71},
number = {7},
pages = {1537--1550},
year = {2022},
url = {https://doi.org/10.1109/TC.2021.3092205},
doi = {10.1109/TC.2021.3092205},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/KimPLKLC22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iecon/LeeCYO22,
author = {Deokjin Lee and
Kiyoung Choi and
Wonbum Yun and
Sehoon Oh},
title = {Human-Robot Interaction Force based Power Assistive Algorithm of Upper
Limb Exoskeleton Robots Driven by a Series Elastic Actuator},
booktitle = {{IECON} 2022 - 48th Annual Conference of the {IEEE} Industrial Electronics
Society, Brussels, Belgium, October 17-20, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/IECON49645.2022.9968363},
doi = {10.1109/IECON49645.2022.9968363},
timestamp = {Wed, 04 Jan 2023 16:48:30 +0100},
biburl = {https://dblp.org/rec/conf/iecon/LeeCYO22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/KimPKCLRLCL21,
author = {Heesu Kim and
Hanmin Park and
Taehyun Kim and
Kwanheum Cho and
Eojin Lee and
Soojung Ryu and
Hyuk{-}Jae Lee and
Kiyoung Choi and
Jinho Lee},
title = {GradPIM: {A} Practical Processing-in-DRAM Architecture for Gradient
Descent},
booktitle = {{IEEE} International Symposium on High-Performance Computer Architecture,
{HPCA} 2021, Seoul, South Korea, February 27 - March 3, 2021},
pages = {249--262},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/HPCA51647.2021.00030},
doi = {10.1109/HPCA51647.2021.00030},
timestamp = {Tue, 27 Apr 2021 14:46:03 +0200},
biburl = {https://dblp.org/rec/conf/hpca/KimPKCLRLCL21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2102-07511,
author = {Heesu Kim and
Hanmin Park and
Taehyun Kim and
Kwanheum Cho and
Eojin Lee and
Soojung Ryu and
Hyuk{-}Jae Lee and
Kiyoung Choi and
Jinho Lee},
title = {GradPIM: {A} Practical Processing-in-DRAM Architecture for Gradient
Descent},
journal = {CoRR},
volume = {abs/2102.07511},
year = {2021},
url = {https://arxiv.org/abs/2102.07511},
eprinttype = {arXiv},
eprint = {2102.07511},
timestamp = {Thu, 18 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2102-07511.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcas/KimKAHGCP20,
author = {Heesu Kim and
Jongho Kim and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Andreas Gerstlauer and
Kiyoung Choi and
Hanmin Park},
title = {Aging Compensation With Dynamic Computation Approximation},
journal = {{IEEE} Trans. Circuits Syst. {I} Fundam. Theory Appl.},
volume = {67-I},
number = {4},
pages = {1319--1332},
year = {2020},
url = {https://doi.org/10.1109/TCSI.2020.2969462},
doi = {10.1109/TCSI.2020.2969462},
timestamp = {Fri, 22 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcas/KimKAHGCP20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aaai/YuKC19,
author = {Joonsang Yu and
Sungbum Kang and
Kiyoung Choi},
title = {Network Recasting: {A} Universal Method for Network Architecture Transformation},
booktitle = {The Thirty-Third {AAAI} Conference on Artificial Intelligence, {AAAI}
2019, The Thirty-First Innovative Applications of Artificial Intelligence
Conference, {IAAI} 2019, The Ninth {AAAI} Symposium on Educational
Advances in Artificial Intelligence, {EAAI} 2019, Honolulu, Hawaii,
USA, January 27 - February 1, 2019},
pages = {5701--5708},
publisher = {{AAAI} Press},
year = {2019},
url = {https://doi.org/10.1609/aaai.v33i01.33015701},
doi = {10.1609/AAAI.V33I01.33015701},
timestamp = {Mon, 04 Sep 2023 12:29:24 +0200},
biburl = {https://dblp.org/rec/conf/aaai/YuKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ParkC19,
author = {Hanmin Park and
Kiyoung Choi},
editor = {Toshiyuki Shibuya},
title = {Cell division: weight bit-width reduction technique for convolutional
neural network hardware accelerators},
booktitle = {Proceedings of the 24th Asia and South Pacific Design Automation Conference,
{ASPDAC} 2019, Tokyo, Japan, January 21-24, 2019},
pages = {286--291},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3287624.3287721},
doi = {10.1145/3287624.3287721},
timestamp = {Sun, 20 Jan 2019 16:08:16 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ParkC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LeePKYJC19,
author = {Gunhee Lee and
Hanmin Park and
Namhyung Kim and
Joonsang Yu and
Sujeong Jo and
Kiyoung Choi},
title = {Acceleration of {DNN} Backward Propagation by Selective Computation
of Gradients},
booktitle = {Proceedings of the 56th Annual Design Automation Conference 2019,
{DAC} 2019, Las Vegas, NV, USA, June 02-06, 2019},
pages = {85},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3316781.3317755},
doi = {10.1145/3316781.3317755},
timestamp = {Sun, 08 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/dac/LeePKYJC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KimKAHGC19,
author = {Jongho Kim and
Heesu Kim and
Hussam Amrouch and
J{\"{o}}rg Henkel and
Andreas Gerstlauer and
Kiyoung Choi},
title = {Aging Gracefully with Approximation},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2019,
Sapporo, Japan, May 26-29, 2019},
pages = {1--5},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISCAS.2019.8702120},
doi = {10.1109/ISCAS.2019.8702120},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KimKAHGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimLKKHC19,
author = {Jaehyun Kim and
Chaeun Lee and
Jihun Kim and
Yumin Kim and
Cheol Seong Hwang and
Kiyoung Choi},
title = {{VCAM:} Variation Compensation through Activation Matching for Analog
Binarized Neural Networks},
booktitle = {2019 {IEEE/ACM} International Symposium on Low Power Electronics and
Design, {ISLPED} 2019, Lausanne, Switzerland, July 29-31, 2019},
pages = {1--6},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISLPED.2019.8824902},
doi = {10.1109/ISLPED.2019.8824902},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/KimLKKHC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/LeeKC19,
author = {Chaeun Lee and
Jaehyun Kim and
Kiyoung Choi},
title = {An RRAM-based Analog Neuron Design for the Weighted Spiking Neural
network},
booktitle = {2019 International SoC Design Conference, {ISOCC} 2019, Jeju, Korea
(South), October 6-9, 2019},
pages = {259--260},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ISOCC47750.2019.9078507},
doi = {10.1109/ISOCC47750.2019.9078507},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/LeeKC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1907-07872,
author = {Euntae Choi and
Kyungmi Lee and
Kiyoung Choi},
title = {Autoencoder-Based Incremental Class Learning without Retraining on
Old Data},
journal = {CoRR},
volume = {abs/1907.07872},
year = {2019},
url = {http://arxiv.org/abs/1907.07872},
eprinttype = {arXiv},
eprint = {1907.07872},
timestamp = {Tue, 23 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1907-07872.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijon/KimKHLC18,
author = {Jaehyun Kim and
Heesu Kim and
Subin Huh and
Jinho Lee and
Kiyoung Choi},
title = {Deep neural networks with weighted spikes},
journal = {Neurocomputing},
volume = {311},
pages = {373--386},
year = {2018},
url = {https://doi.org/10.1016/j.neucom.2018.05.087},
doi = {10.1016/J.NEUCOM.2018.05.087},
timestamp = {Sat, 11 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijon/KimKHLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/KimACSYR18,
author = {Namhyung Kim and
Junwhan Ahn and
Kiyoung Choi and
Daniel S{\'{a}}nchez and
Donghoon Yoo and
Soojung Ryu},
title = {Benzene: An Energy-Efficient Distributed Hybrid Cache Architecture
for Manycore Systems},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {15},
number = {1},
pages = {10:1--10:23},
year = {2018},
url = {https://doi.org/10.1145/3177963},
doi = {10.1145/3177963},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/KimACSYR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhakatayevKCL18,
author = {Aidyn Zhakatayev and
Kyounghoon Kim and
Kiyoung Choi and
Jongeun Lee},
title = {An Efficient and Accurate Stochastic Number Generator Using Even-Distribution
Coding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3056--3066},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789732},
doi = {10.1109/TCAD.2018.2789732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhakatayevKCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimCKKDC18,
author = {Jongho Kim and
Kiyoung Choi and
Yonghwan Kim and
Wook Kim and
Kyung Tae Do and
Jung{-}Hwan Choi},
title = {Delay Monitoring System With Multiple Generic Monitors for Wide Voltage
Range Operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {26},
number = {1},
pages = {37--49},
year = {2018},
url = {https://doi.org/10.1109/TVLSI.2017.2757511},
doi = {10.1109/TVLSI.2017.2757511},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimCKKDC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/apsipa/KimCC18,
author = {Heesu Kim and
Euntae Choi and
Kiyoung Choi},
title = {Speaker Verification based on Deep Neural Network for Text-Constrained
Short Commands},
booktitle = {Asia-Pacific Signal and Information Processing Association Annual
Summit and Conference, {APSIPA} {ASC} 2018, Honolulu, HI, USA, November
12-15, 2018},
pages = {1766--1770},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.23919/APSIPA.2018.8659767},
doi = {10.23919/APSIPA.2018.8659767},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/apsipa/KimCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/HarrisMKBKMCKEH18,
author = {Barend Harris and
Mansureh S. Moghaddam and
Duseok Kang and
Inpyo Bae and
Euiseok Kim and
Hyemi Min and
Hansu Cho and
Sukjin Kim and
Bernhard Egger and
Soonhoi Ha and
Kiyoung Choi},
editor = {Youngsoo Shin},
title = {Architectures and algorithms for user customization of CNNs},
booktitle = {23rd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2018, Jeju, Korea (South), January 22-25, 2018},
pages = {540--547},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ASPDAC.2018.8297379},
doi = {10.1109/ASPDAC.2018.8297379},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/HarrisMKBKMCKEH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/JoPLC18,
author = {Sujeong Jo and
Hanmin Park and
Gunhee Lee and
Kiyoung Choi},
title = {Training Neural Networks with Low Precision Dynamic Fixed-Point},
booktitle = {36th {IEEE} International Conference on Computer Design, {ICCD} 2018,
Orlando, FL, USA, October 7-10, 2018},
pages = {405--408},
publisher = {{IEEE} Computer Society},
year = {2018},
url = {https://doi.org/10.1109/ICCD.2018.00067},
doi = {10.1109/ICCD.2018.00067},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/JoPLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ics/LeeKC18,
author = {Dongwoo Lee and
Sungbum Kang and
Kiyoung Choi},
title = {ComPEND: Computation Pruning through Early Negative Detection for
ReLU in a Deep Neural Network Accelerator},
booktitle = {Proceedings of the 32nd International Conference on Supercomputing,
{ICS} 2018, Beijing, China, June 12-15, 2018},
pages = {139--148},
publisher = {{ACM}},
year = {2018},
url = {https://doi.org/10.1145/3205289.3205295},
doi = {10.1145/3205289.3205295},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/ics/LeeKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KangYC18,
author = {Sungbum Kang and
Joonsang Yu and
Kiyoung Choi},
title = {Tapered-Ratio Compression for Residual Network},
booktitle = {International SoC Design Conference, {ISOCC} 2018, Daegu, South Korea,
November 12-15, 2018},
pages = {72--73},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISOCC.2018.8649890},
doi = {10.1109/ISOCC.2018.8649890},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/KangYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/MoradianJC18,
author = {Hossein Moradian and
Sujeong Jo and
Kiyoung Choi},
title = {Reconfigurable Multi-Input Adder Design for Deep Neural Network Accelerators},
booktitle = {International SoC Design Conference, {ISOCC} 2018, Daegu, South Korea,
November 12-15, 2018},
pages = {212--213},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISOCC.2018.8649943},
doi = {10.1109/ISOCC.2018.8649943},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/MoradianJC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimLC18a,
author = {Jaehyun Kim and
Chaeun Lee and
Kiyoung Choi},
title = {Energy Efficient Analog Synapse/Neuron Circuit for Binarized Neural
Networks},
booktitle = {International SoC Design Conference, {ISOCC} 2018, Daegu, South Korea,
November 12-15, 2018},
pages = {271--272},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ISOCC.2018.8649929},
doi = {10.1109/ISOCC.2018.8649929},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/KimLC18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-1809-05262,
author = {Joonsang Yu and
Sungbum Kang and
Kiyoung Choi},
title = {Network Recasting: {A} Universal Method for Network Architecture Transformation},
journal = {CoRR},
volume = {abs/1809.05262},
year = {2018},
url = {http://arxiv.org/abs/1809.05262},
eprinttype = {arXiv},
eprint = {1809.05262},
timestamp = {Fri, 05 Oct 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-1809-05262.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/MoghaddamBC17,
author = {Mansureh Shahraki Moghaddam and
M. Balakrishnan and
Kiyoung Choi},
title = {Optimal mapping of program overlays onto many-core platforms with
limited memory capacity},
journal = {Des. Autom. Embed. Syst.},
volume = {21},
number = {3-4},
pages = {173--194},
year = {2017},
url = {https://doi.org/10.1007/s10617-017-9193-9},
doi = {10.1007/S10617-017-9193-9},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/MoghaddamBC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ieicet/SongC17,
author = {Hyunjik Song and
Kiyoung Choi},
title = {Autonomic Diffusive Load Balancing on Many-Core Architecture Using
Simulated Annealing},
journal = {{IEICE} Trans. Fundam. Electron. Commun. Comput. Sci.},
volume = {100-A},
number = {8},
pages = {1640--1649},
year = {2017},
url = {https://doi.org/10.1587/transfun.E100.A.1640},
doi = {10.1587/TRANSFUN.E100.A.1640},
timestamp = {Sat, 11 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ieicet/SongC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pvldb/LeeKYCHNNJ17,
author = {Jinho Lee and
Heesu Kim and
Sungjoo Yoo and
Kiyoung Choi and
H. Peter Hofstee and
Gi{-}Joon Nam and
Mark Nutter and
Damir A. Jamsek},
title = {ExtraV: Boosting Graph Processing Near Storage with a Coherent Accelerator},
journal = {Proc. {VLDB} Endow.},
volume = {10},
number = {12},
pages = {1706--1717},
year = {2017},
url = {http://www.vldb.org/pvldb/vol10/p1706-lee.pdf},
doi = {10.14778/3137765.3137776},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/pvldb/LeeKYCHNNJ17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/LeeLRC17,
author = {Dongwoo Lee and
Sang{-}Heon Lee and
Soojung Ryu and
Kiyoung Choi},
title = {Dirty-Block Tracking in a Direct-Mapped {DRAM} Cache with Self-Balancing
Dispatch},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {14},
number = {2},
pages = {11:1--11:25},
year = {2017},
url = {https://doi.org/10.1145/3068460},
doi = {10.1145/3068460},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/taco/LeeLRC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeCAC17,
author = {Jinho Lee and
Jongwook Chung and
Jung Ho Ahn and
Kiyoung Choi},
title = {Excavating the Hidden Parallelism Inside {DRAM} Architectures With
Buffered Compares},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {25},
number = {6},
pages = {1793--1806},
year = {2017},
url = {https://doi.org/10.1109/TVLSI.2017.2655722},
doi = {10.1109/TVLSI.2017.2655722},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeCAC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SimNLC17,
author = {Hyeon Uk Sim and
Dong Nguyen and
Jongeun Lee and
Kiyoung Choi},
title = {Scalable stochastic-computing accelerator for convolutional neural
networks},
booktitle = {22nd Asia and South Pacific Design Automation Conference, {ASP-DAC}
2017, Chiba, Japan, January 16-19, 2017},
pages = {696--701},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ASPDAC.2017.7858405},
doi = {10.1109/ASPDAC.2017.7858405},
timestamp = {Tue, 24 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SimNLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/MoghaddamHKBKMC17,
author = {Mansureh S. Moghaddam and
Barend Harris and
Duseok Kang and
Inpyo Bae and
Euiseok Kim and
Hyemi Min and
Hansu Cho and
Sukjin Kim and
Bernhard Egger and
Soonhoi Ha and
Kiyoung Choi},
title = {Incremental training of CNNs for user customization: work-in-progress},
booktitle = {Proceedings of the 2017 International Conference on Compilers, Architectures
and Synthesis for Embedded Systems, {CASES} 2017, Seoul, Republic
of Korea, October 15-20, 2017},
pages = {9:1--9:2},
publisher = {{ACM}},
year = {2017},
url = {https://doi.org/10.1145/3125501.3125519},
doi = {10.1145/3125501.3125519},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/cases/MoghaddamHKBKMC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cgo/EggerLKMCLKHC17,
author = {Bernhard Egger and
Hochan Lee and
Duseok Kang and
Mansureh S. Moghaddam and
Youngchul Cho and
Yeonbok Lee and
Sukjin Kim and
Soonhoi Ha and
Kiyoung Choi},
editor = {Vijay Janapa Reddi and
Aaron Smith and
Lingjia Tang},
title = {A space- and energy-efficient code Compression/Decompression technique
for coarse-grained reconfigurable architectures},
booktitle = {Proceedings of the 2017 International Symposium on Code Generation
and Optimization, {CGO} 2017, Austin, TX, USA, February 4-8, 2017},
pages = {197--209},
publisher = {{ACM}},
year = {2017},
url = {http://dl.acm.org/citation.cfm?id=3049854},
timestamp = {Mon, 06 Feb 2017 08:11:47 +0100},
biburl = {https://dblp.org/rec/conf/cgo/EggerLKMCLKHC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RahmanOLC17,
author = {Atul Rahman and
Sangyun Oh and
Jongeun Lee and
Kiyoung Choi},
editor = {David Atienza and
Giorgio Di Natale},
title = {Design space exploration of {FPGA} accelerators for convolutional
neural networks},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2017, Lausanne, Switzerland, March 27-31, 2017},
pages = {1147--1152},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.23919/DATE.2017.7927162},
doi = {10.23919/DATE.2017.7927162},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/RahmanOLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/KimMMSLC17,
author = {Daewoo Kim and
Mansureh S. Moghaddam and
Hossein Moradian and
Hyeon Uk Sim and
Jongeun Lee and
Kiyoung Choi},
title = {{FPGA} implementation of convolutional neural network based on stochastic
computing},
booktitle = {International Conference on Field Programmable Technology, {FPT} 2017,
Melbourne, Australia, December 11-13, 2017},
pages = {287--290},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/FPT.2017.8280162},
doi = {10.1109/FPT.2017.8280162},
timestamp = {Mon, 17 Feb 2020 13:32:07 +0100},
biburl = {https://dblp.org/rec/conf/fpt/KimMMSLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/YuKLC17,
author = {Joonsang Yu and
Kyounghoon Kim and
Jongeun Lee and
Kiyoung Choi},
title = {Accurate and Efficient Stochastic Computing Hardware for Convolutional
Neural Networks},
booktitle = {2017 {IEEE} International Conference on Computer Design, {ICCD} 2017,
Boston, MA, USA, November 5-8, 2017},
pages = {105--112},
publisher = {{IEEE} Computer Society},
year = {2017},
url = {https://doi.org/10.1109/ICCD.2017.24},
doi = {10.1109/ICCD.2017.24},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/YuKLC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/HuhYC17,
author = {Subin Huh and
Joonsang Yu and
Kiyoung Choi},
title = {A new stochastic mutiplier for deep neural networks},
booktitle = {International SoC Design Conference, {ISOCC} 2017, Seoul, South Korea,
November 5-8, 2017},
pages = {46--47},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/ISOCC.2017.8368820},
doi = {10.1109/ISOCC.2017.8368820},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/HuhYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimC17,
author = {Kyounghoon Kim and
Kiyoung Choi},
title = {Synthesis of multi-variate stochastic computing circuits},
booktitle = {2017 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2017, Abu Dhabi, United Arab Emirates, October 23-25, 2017},
pages = {1--6},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-SoC.2017.8203493},
doi = {10.1109/VLSI-SOC.2017.8203493},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/KimYC17,
author = {Heesu Kim and
Joonsang Yu and
Kiyoung Choi},
title = {Hybrid spiking-stochastic Deep Neural Network},
booktitle = {2017 International Symposium on {VLSI} Design, Automation and Test,
{VLSI-DAT} 2017, Hsinchu, Taiwan, April 24-27, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/VLSI-DAT.2017.7939642},
doi = {10.1109/VLSI-DAT.2017.7939642},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/KimYC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:reference/hwswco/MoghaddamCC17,
author = {Mansureh Shahraki Moghaddam and
Jae{-}Min Cho and
Kiyoung Choi},
editor = {Soonhoi Ha and
J{\"{u}}rgen Teich},
title = {Reconfigurable Architectures},
booktitle = {Handbook of Hardware/Software Codesign},
pages = {335--376},
publisher = {Springer},
year = {2017},
url = {https://doi.org/10.1007/978-94-017-7267-9\_12},
doi = {10.1007/978-94-017-7267-9\_12},
timestamp = {Tue, 06 Aug 2019 10:05:03 +0200},
biburl = {https://dblp.org/rec/reference/hwswco/MoghaddamCC17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/iet-cdt/ParkC16,
author = {Hanmin Park and
Kiyoung Choi},
title = {Adaptively weighted round-robin arbitration for equality of service
in a many-core network-on-chip},
journal = {{IET} Comput. Digit. Tech.},
volume = {10},
number = {1},
pages = {37--44},
year = {2016},
url = {https://doi.org/10.1049/iet-cdt.2015.0049},
doi = {10.1049/IET-CDT.2015.0049},
timestamp = {Tue, 14 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/iet-cdt/ParkC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/KimC16,
author = {Namhyung Kim and
Kiyoung Choi},
title = {Exploration of trade-offs in the design of volatile {STT-RAM} cache},
journal = {J. Syst. Archit.},
volume = {71},
pages = {23--31},
year = {2016},
url = {https://doi.org/10.1016/j.sysarc.2016.06.005},
doi = {10.1016/J.SYSARC.2016.06.005},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jsa/KimC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/pr/KimLCC16,
author = {Kyounghoon Kim and
Helin Lin and
Jin Young Choi and
Kiyoung Choi},
title = {A design framework for hierarchical ensemble of multiple feature extractors
and multiple classifiers},
journal = {Pattern Recognit.},
volume = {52},
pages = {1--16},
year = {2016},
url = {https://doi.org/10.1016/j.patcog.2015.11.006},
doi = {10.1016/J.PATCOG.2015.11.006},
timestamp = {Mon, 24 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/pr/KimLCC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/AhnYC16,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {{AIM:} Energy-Efficient Aggregation Inside the Memory Hierarchy},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {13},
number = {4},
pages = {34:1--34:24},
year = {2016},
url = {https://doi.org/10.1145/2994149},
doi = {10.1145/2994149},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/AhnYC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AhnYC16,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {Prediction Hybrid Cache: An Energy-Efficient {STT-RAM} Cache Architecture},
journal = {{IEEE} Trans. Computers},
volume = {65},
number = {3},
pages = {940--951},
year = {2016},
url = {https://doi.org/10.1109/TC.2015.2435772},
doi = {10.1109/TC.2015.2435772},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/AhnYC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhnYC16,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level
Prefetching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {24},
number = {2},
pages = {453--464},
year = {2016},
url = {https://doi.org/10.1109/TVLSI.2015.2420315},
doi = {10.1109/TVLSI.2015.2420315},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhnYC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimLC16,
author = {Kyounghoon Kim and
Jongeun Lee and
Kiyoung Choi},
title = {An energy-efficient random number generator for stochastic circuits},
booktitle = {21st Asia and South Pacific Design Automation Conference, {ASP-DAC}
2016, Macao, Macao, January 25-28, 2016},
pages = {256--261},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ASPDAC.2016.7428020},
doi = {10.1109/ASPDAC.2016.7428020},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimKYSLC16,
author = {Kyounghoon Kim and
Jungki Kim and
Joonsang Yu and
Jungwoo Seo and
Jongeun Lee and
Kiyoung Choi},
title = {Dynamic energy-accuracy trade-off using stochastic computing in deep
neural networks},
booktitle = {Proceedings of the 53rd Annual Design Automation Conference, {DAC}
2016, Austin, TX, USA, June 5-9, 2016},
pages = {124:1--124:6},
publisher = {{ACM}},
year = {2016},
url = {https://doi.org/10.1145/2897937.2898011},
doi = {10.1145/2897937.2898011},
timestamp = {Tue, 06 Nov 2018 16:58:19 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimKYSLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KimLCKKDC16,
author = {Jongho Kim and
Gunhee Lee and
Kiyoung Choi and
Yonghwan Kim and
Wook Kim and
Kyung Tae Do and
Jung Yun Choi},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Adaptive delay monitoring for wide voltage-range operation},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {511--516},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459363/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/KimLCKKDC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/LeeAC16,
author = {Jinho Lee and
Jung Ho Ahn and
Kiyoung Choi},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Buffered compares: Excavating the hidden parallelism inside {DRAM}
architectures with lightweight logic},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1243--1248},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459501/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/LeeAC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RahmanLC16,
author = {Atul Rahman and
Jongeun Lee and
Kiyoung Choi},
editor = {Luca Fanucci and
J{\"{u}}rgen Teich},
title = {Efficient {FPGA} acceleration of Convolutional Neural Networks using
logical-3D compute array},
booktitle = {2016 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2016, Dresden, Germany, March 14-18, 2016},
pages = {1393--1398},
publisher = {{IEEE}},
year = {2016},
url = {https://ieeexplore.ieee.org/document/7459526/},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/RahmanLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/SeoYLC16,
author = {Jungwoo Seo and
Joonsang Yu and
Jongeun Lee and
Kiyoung Choi},
title = {A new approach to binarizing neural networks},
booktitle = {International SoC Design Conference, {ISOCC} 2016, Jeju, South Korea,
October 23-26, 2016},
pages = {77--78},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ISOCC.2016.7799741},
doi = {10.1109/ISOCC.2016.7799741},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isocc/SeoYLC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimCLR16,
author = {Jaehyun Kim and
Kiyoung Choi and
Sang{-}Heon Lee and
Soojung Ryu},
title = {Dynamic clock synchronization scheme between voltage domains in multi-core
architecture},
booktitle = {2016 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2016, Tallinn, Estonia, September 26-28, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/VLSI-SoC.2016.7753536},
doi = {10.1109/VLSI-SOC.2016.7753536},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimCLR16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsi/2015socs,
editor = {Youngsoo Shin and
Chi{-}Ying Tsui and
Jae{-}Joon Kim and
Kiyoung Choi and
Ricardo Reis},
title = {VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd {IFIP}
{WG} 10.5/IEEE International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected
Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {483},
publisher = {Springer},
year = {2016},
url = {https://doi.org/10.1007/978-3-319-46097-0},
doi = {10.1007/978-3-319-46097-0},
isbn = {978-3-319-46096-3},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/2015socs.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jetc/LeeKC15,
author = {Jinho Lee and
Kyungsu Kang and
Kiyoung Choi},
title = {{REDELF:} An Energy-Efficient Deadlock-Free Routing for 3D NoCs with
Partial Vertical Connections},
journal = {{ACM} J. Emerg. Technol. Comput. Syst.},
volume = {12},
number = {3},
pages = {26:1--26:22},
year = {2015},
url = {https://doi.org/10.1145/2751560},
doi = {10.1145/2751560},
timestamp = {Mon, 08 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jetc/LeeKC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tmscs/ChenCZ15,
author = {Yiran Chen and
Kiyoung Choi and
Weisheng Zhao},
title = {Guest Editorial for Special Issue on Emerging Memory Technologies
- Modeling, Design, and Applications for Multi-Scale Computing},
journal = {{IEEE} Trans. Multi Scale Comput. Syst.},
volume = {1},
number = {3},
pages = {125--126},
year = {2015},
url = {https://doi.org/10.1109/TMSCS.2015.2505118},
doi = {10.1109/TMSCS.2015.2505118},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tmscs/ChenCZ15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeACK15,
author = {Jinho Lee and
Junwhan Ahn and
Kiyoung Choi and
Kyungsu Kang},
title = {{THOR:} Orchestrated thermal management of cores and networks in 3D
many-core architectures},
booktitle = {The 20th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2015, Chiba, Japan, January 19-22, 2015},
pages = {773--778},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ASPDAC.2015.7059104},
doi = {10.1109/ASPDAC.2015.7059104},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeACK15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AhnHYMC15,
author = {Junwhan Ahn and
Sungpack Hong and
Sungjoo Yoo and
Onur Mutlu and
Kiyoung Choi},
editor = {Deborah T. Marr and
David H. Albonesi},
title = {A scalable processing-in-memory accelerator for parallel graph processing},
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer
Architecture, Portland, OR, USA, June 13-17, 2015},
pages = {105--117},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2749469.2750386},
doi = {10.1145/2749469.2750386},
timestamp = {Fri, 09 Jul 2021 15:51:20 +0200},
biburl = {https://dblp.org/rec/conf/isca/AhnHYMC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isca/AhnYMC15,
author = {Junwhan Ahn and
Sungjoo Yoo and
Onur Mutlu and
Kiyoung Choi},
editor = {Deborah T. Marr and
David H. Albonesi},
title = {PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory
architecture},
booktitle = {Proceedings of the 42nd Annual International Symposium on Computer
Architecture, Portland, OR, USA, June 13-17, 2015},
pages = {336--348},
publisher = {{ACM}},
year = {2015},
url = {https://doi.org/10.1145/2749469.2750385},
doi = {10.1145/2749469.2750385},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isca/AhnYMC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Nicolas-Nicolaz15,
author = {Pierre Nicolas{-}Nicolaz and
Kiyoung Choi},
title = {Dynamic error tracking and supply voltage adjustment for low power},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {74--79},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314395},
doi = {10.1109/VLSI-SOC.2015.7314395},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Nicolas-Nicolaz15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/KimASC15,
author = {Namhyung Kim and
Junwhan Ahn and
Woong Seo and
Kiyoung Choi},
title = {Energy-efficient exclusive last-level hybrid caches consisting of
{SRAM} and {STT-RAM}},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {183--188},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314413},
doi = {10.1109/VLSI-SOC.2015.7314413},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/KimASC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChangC15,
author = {Naehyuck Chang and
Kiyoung Choi},
title = {Message from the general chairs},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {VIII},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314376},
doi = {10.1109/VLSI-SOC.2015.7314376},
timestamp = {Wed, 24 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ChangC15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/JoLHC14,
author = {Manhwee Jo and
Dongwook Lee and
Kyuseung Han and
Kiyoung Choi},
title = {Design of a coarse-grained reconfigurable architecture with floating-point
support and comparative study},
journal = {Integr.},
volume = {47},
number = {2},
pages = {232--241},
year = {2014},
url = {https://doi.org/10.1016/j.vlsi.2013.08.003},
doi = {10.1016/J.VLSI.2013.08.003},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/JoLHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tdsc/HanLC14,
author = {Kyuseung Han and
Ganghee Lee and
Kiyoung Choi},
title = {Software-Level Approaches for Tolerating Transient Faults in a Coarse-GrainedReconfigurable
Architecture},
journal = {{IEEE} Trans. Dependable Secur. Comput.},
volume = {11},
number = {4},
pages = {392--398},
year = {2014},
url = {https://doi.org/10.1109/TDSC.2013.54},
doi = {10.1109/TDSC.2013.54},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tdsc/HanLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeSPC14,
author = {Jongeun Lee and
Seongseok Seo and
Jong Kyung Paek and
Kiyoung Choi},
title = {Configurable range memory for effective data reuse on programmable
accelerators},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {13:1--13:22},
year = {2014},
url = {https://doi.org/10.1145/2566662},
doi = {10.1145/2566662},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeeSPC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeC14,
author = {Seokhyun Lee and
Kiyoung Choi},
title = {Critical-path-aware high-level synthesis with distributed controller
for fast timing closure},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {19},
number = {2},
pages = {16:1--16:29},
year = {2014},
url = {https://doi.org/10.1145/2566670},
doi = {10.1145/2566670},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeeC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AndersonC14,
author = {Jason Helge Anderson and
Kiyoung Choi},
title = {Introduction to the Special Issue on the 11\({}^{\mbox{th}}\) International
Conference on Field-Programmable Technology (FPT'12)},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {7},
number = {3},
pages = {18:1--18:2},
year = {2014},
url = {https://doi.org/10.1145/2655712},
doi = {10.1145/2655712},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AndersonC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AhnC14,
author = {Junwhan Ahn and
Kiyoung Choi},
title = {{LASIC:} Loop-Aware Sleepy Instruction Caches Based on {STT-RAM} Technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {22},
number = {5},
pages = {1197--1201},
year = {2014},
url = {https://doi.org/10.1109/TVLSI.2013.2265278},
doi = {10.1109/TVLSI.2013.2265278},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AhnC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/RyooHC14,
author = {Jihyun Ryoo and
Kyuseung Han and
Kiyoung Choi},
title = {Leveraging parallelism in the presence of control flow on CGRAs},
booktitle = {19th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2014, Singapore, January 20-23, 2014},
pages = {285--291},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ASPDAC.2014.6742904},
doi = {10.1109/ASPDAC.2014.6742904},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/RyooHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AhnYC14,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {139:1--139:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2593128},
doi = {10.1145/2593069.2593128},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/AhnYC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hpca/AhnYC14,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {{DASCA:} Dead Write Prediction Assisted {STT-RAM} Cache Architecture},
booktitle = {20th {IEEE} International Symposium on High Performance Computer Architecture,
{HPCA} 2014, Orlando, FL, USA, February 15-19, 2014},
pages = {25--36},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/HPCA.2014.6835944},
doi = {10.1109/HPCA.2014.6835944},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hpca/AhnYC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ivs/LinKC14,
author = {Helin Lin and
Kyounghoon Kim and
Kiyoung Choi},
title = {Concept-aware ensemble system for pedestrian detection},
booktitle = {2014 {IEEE} Intelligent Vehicles Symposium Proceedings, Dearborn,
MI, USA, June 8-11, 2014},
pages = {140--145},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IVS.2014.6856521},
doi = {10.1109/IVS.2014.6856521},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ivs/LinKC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/HanLC14,
author = {Sungju Han and
Jinho Lee and
Kiyoung Choi},
editor = {Farhad Mehdipour and
Giorgos Dimitrakopoulos},
title = {Tree-Mesh Heterogeneous Topology for Low-Latency NoC},
booktitle = {Proceedings of the 2014 International Workshop on Network on Chip
Architectures, NoCArc '14, Cambridge, United Kingdom, December 13-14,
2014},
pages = {19--24},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2685342.2685346},
doi = {10.1145/2685342.2685346},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/HanLC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeC14,
author = {Dongwoo Lee and
Kiyoung Choi},
editor = {Lorena Garcia},
title = {Energy-efficient partitioning of hybrid caches in multi-core architecture},
booktitle = {22nd International Conference on Very Large Scale Integration, VLSI-SoC,
Playa del Carmen, Mexico, October 6-8, 2014},
pages = {1--6},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-SoC.2014.7004174},
doi = {10.1109/VLSI-SOC.2014.7004174},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LeeC14a,
author = {Dongwoo Lee and
Kiyoung Choi},
editor = {Luc Claesen and
Mar{\'{\i}}a Teresa Sanz{-}Pascual and
Ricardo Reis and
Arturo Sarmiento{-}Reyes},
title = {Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture},
booktitle = {VLSI-SoC: Internet of Things Foundations - 22nd {IFIP} {WG} 10.5/IEEE
International Conference on Very Large Scale Integration, VLSI-SoC
2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised and Extended
Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {464},
pages = {58--74},
publisher = {Springer},
year = {2014},
url = {https://doi.org/10.1007/978-3-319-25279-7\_4},
doi = {10.1007/978-3-319-25279-7\_4},
timestamp = {Tue, 22 Oct 2019 15:21:19 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LeeC14a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChoC14,
author = {Jae Min Cho and
Kiyoung Choi},
title = {An {FPGA} implementation of high-throughput key-value store using
Bloom filter},
booktitle = {Technical Papers of 2014 International Symposium on {VLSI} Design,
Automation and Test, {VLSI-DAT} 2014, Hsinchu, Taiwan, April 28-30,
2014},
pages = {1--4},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/VLSI-DAT.2014.6834868},
doi = {10.1109/VLSI-DAT.2014.6834868},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChoC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/ChoiJLJ13,
author = {Kiyoung Choi and
Sung{-}Up Jo and
Hwamin Lee and
Changsung Jeong},
title = {CPU-based speed acceleration techniques for shear warp volume rendering},
journal = {Multim. Tools Appl.},
volume = {64},
number = {2},
pages = {309--329},
year = {2013},
url = {https://doi.org/10.1007/s11042-012-1010-7},
doi = {10.1007/S11042-012-1010-7},
timestamp = {Fri, 22 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/ChoiJLJ13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/taco/HanAC13,
author = {Kyuseung Han and
Junwhan Ahn and
Kiyoung Choi},
title = {Power-Efficient Predication Techniques for Acceleration of Control
Flow Execution on {CGRA}},
journal = {{ACM} Trans. Archit. Code Optim.},
volume = {10},
number = {2},
pages = {8:1--8:25},
year = {2013},
url = {https://doi.org/10.1145/2459316.2459319},
doi = {10.1145/2459316.2459319},
timestamp = {Wed, 17 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/taco/HanAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhnC13,
author = {Junwhan Ahn and
Kiyoung Choi},
title = {Isomorphism-Aware Identification of Custom Instructions With {I/O}
Serialization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {1},
pages = {34--46},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2012.2214033},
doi = {10.1109/TCAD.2012.2214033},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhnC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCCRAC13,
author = {Jinho Lee and
Moo{-}Kyoung Chung and
Yeon{-}Gon Cho and
Soojung Ryu and
Jung Ho Ahn and
Kiyoung Choi},
title = {Mapping and Scheduling of Tasks and Communications on Many-Core SoC
Under Local Memory Constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {32},
number = {11},
pages = {1748--1761},
year = {2013},
url = {https://doi.org/10.1109/TCAD.2013.2266405},
doi = {10.1109/TCAD.2013.2266405},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LeeCCRAC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeLKC13,
author = {Jinho Lee and
Dongwook Lee and
Sunwook Kim and
Kiyoung Choi},
title = {Deflection routing in 3D network-on-chip with limited vertical bandwidth},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {18},
number = {4},
pages = {50:1--50:22},
year = {2013},
url = {https://doi.org/10.1145/2505011},
doi = {10.1145/2505011},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LeeLKC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeLKC13,
author = {Jinho Lee and
Dongwook Lee and
Sunwook Kim and
Kiyoung Choi},
title = {Deflection routing in 3D Network-on-Chip with {TSV} serialization},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {29--34},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509554},
doi = {10.1109/ASPDAC.2013.6509554},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeLKC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AhnYC13,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
title = {Selectively protecting error-correcting code for area-efficient and
reliable {STT-RAM} caches},
booktitle = {18th Asia and South Pacific Design Automation Conference, {ASP-DAC}
2013, Yokohama, Japan, January 22-25, 2013},
pages = {285--290},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ASPDAC.2013.6509610},
doi = {10.1109/ASPDAC.2013.6509610},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AhnYC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HanCL13,
author = {Kyuseung Han and
Kiyoung Choi and
Jongeun Lee},
editor = {Enrico Macii},
title = {Compiling control-intensive loops for CGRAs with state-based full
predication},
booktitle = {Design, Automation and Test in Europe, {DATE} 13, Grenoble, France,
March 18-22, 2013},
pages = {1579--1582},
publisher = {{EDA} Consortium San Jose, CA, {USA} / {ACM} {DL}},
year = {2013},
url = {https://doi.org/10.7873/DATE.2013.321},
doi = {10.7873/DATE.2013.321},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/HanCL13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/AhnYC13,
author = {Junwhan Ahn and
Sungjoo Yoo and
Kiyoung Choi},
editor = {Pai H. Chou and
Ru Huang and
Yuan Xie and
Tanay Karnik},
title = {Write intensity prediction for energy-efficient non-volatile caches},
booktitle = {International Symposium on Low Power Electronics and Design (ISLPED),
Beijing, China, September 4-6, 2013},
pages = {223--228},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/ISLPED.2013.6629298},
doi = {10.1109/ISLPED.2013.6629298},
timestamp = {Wed, 16 Oct 2019 14:14:56 +0200},
biburl = {https://dblp.org/rec/conf/islped/AhnYC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/LeeLC13,
author = {Gunhee Lee and
Jinho Lee and
Kiyoung Choi},
editor = {Maurizio Palesi and
Terrence S. T. Mak and
Masoud Daneshtalab},
title = {Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth},
booktitle = {Network on Chip Architectures, NoCArc '13, in conjunction with the
46th Annual {IEEE/ACM} International Symposium on Microarchitecture,
MICRO-46, Davis, CA, USA, December 7, 2013},
pages = {23--26},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2536522.2536534},
doi = {10.1145/2536522.2536534},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/LeeLC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mue/JoHC13,
author = {Manhwee Jo and
Kyuseung Han and
Kiyoung Choi},
editor = {James J. Park and
Joseph Kee{-}Yin Ng and
Hwa{-}Young Jeong and
Agustinus Borgy Waluyo},
title = {Enhancing Utilization of Integer Functional Units for High-Throughput
Floating Point Operations on Coarse-Grained Reconfigurable Architecture},
booktitle = {Multimedia and Ubiquitous Engineering, {MUE} 2013, May 9-11, 2013,
Seoul, Korea},
series = {Lecture Notes in Electrical Engineering},
volume = {240},
pages = {1161--1167},
publisher = {Springer},
year = {2013},
url = {https://doi.org/10.1007/978-94-007-6738-6\_143},
doi = {10.1007/978-94-007-6738-6\_143},
timestamp = {Sun, 04 Jun 2017 10:10:13 +0200},
biburl = {https://dblp.org/rec/conf/mue/JoHC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nocs/LeeC13,
author = {Jinho Lee and
Kiyoung Choi},
title = {A deadlock-free routing algorithm requiring no virtual channel on
3D-NoCs with partial vertical connections},
booktitle = {2013 Seventh {IEEE/ACM} International Symposium on Networks-on-Chip
(NoCS), Tempe, AZ, USA, April 21-24, 2013},
pages = {1--2},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/NoCS.2013.6558407},
doi = {10.1109/NOCS.2013.6558407},
timestamp = {Wed, 16 Oct 2019 14:14:48 +0200},
biburl = {https://dblp.org/rec/conf/nocs/LeeC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/ChoiKL12,
author = {Kiyoung Choi and
John Kim and
Gabriel H. Loh},
title = {Guest Editorial New Interconnect Technologies in On-Chip Communication},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {2},
number = {2},
pages = {121--123},
year = {2012},
url = {https://doi.org/10.1109/JETCAS.2012.2196890},
doi = {10.1109/JETCAS.2012.2196890},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/ChoiKL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/KimCL12,
author = {John Kim and
Kiyoung Choi and
Gabriel H. Loh},
title = {Exploiting New Interconnect Technologies in On-Chip Communication},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {2},
number = {2},
pages = {124--136},
year = {2012},
url = {https://doi.org/10.1109/JETCAS.2012.2201031},
doi = {10.1109/JETCAS.2012.2201031},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esticas/KimCL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jece/ChenCCXZ12,
author = {Deming Chen and
Kiyoung Choi and
Philippe Coussy and
Yuan Xie and
Zhiru Zhang},
title = {{ESL} Design Methodology},
journal = {J. Electr. Comput. Eng.},
volume = {2012},
pages = {358281:1--358281:2},
year = {2012},
url = {https://doi.org/10.1155/2012/358281},
doi = {10.1155/2012/358281},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jece/ChenCCXZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/YooYC12,
author = {Jun{-}hee Yoo and
Sungjoo Yoo and
Kiyoung Choi},
title = {Active Memory Processor for Network-on-Chip-Based Architecture},
journal = {{IEEE} Trans. Computers},
volume = {61},
number = {5},
pages = {622--635},
year = {2012},
url = {https://doi.org/10.1109/TC.2011.66},
doi = {10.1109/TC.2011.66},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/YooYC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/LeeC12,
author = {Jinho Lee and
Kiyoung Choi},
title = {Memory-aware mapping and scheduling of tasks and communications on
many-core SoC},
booktitle = {Proceedings of the 17th Asia and South Pacific Design Automation Conference,
{ASP-DAC} 2012, Sydney, Australia, January 30 - February 2, 2012},
pages = {419--424},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ASPDAC.2012.6164985},
doi = {10.1109/ASPDAC.2012.6164985},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/LeeC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HanPC12,
author = {Kyuseung Han and
Seongsik Park and
Kiyoung Choi},
editor = {Wolfgang Rosenstiel and
Lothar Thiele},
title = {State-based full predication for low power coarse-grained reconfigurable
architecture},
booktitle = {2012 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2012, Dresden, Germany, March 12-16, 2012},
pages = {1367--1372},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/DATE.2012.6176704},
doi = {10.1109/DATE.2012.6176704},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/HanPC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AhnC12,
author = {Junwhan Ahn and
Kiyoung Choi},
title = {Lower-bits cache for low power {STT-RAM} caches},
booktitle = {2012 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
2012, Seoul, Korea (South), May 20-23, 2012},
pages = {480--483},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISCAS.2012.6272069},
doi = {10.1109/ISCAS.2012.6272069},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AhnC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/LeeAC12,
author = {Dongwoo Lee and
Junwhan Ahn and
Kiyoung Choi},
title = {A Memetic Quantum-Inspired Evolutionary Algorithm for circuit bipartitioning
problem},
booktitle = {International SoC Design Conference, {ISOCC} 2012, Jeju Island, South
Korea, November 4-7, 2012},
pages = {159--162},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISOCC.2012.6407064},
doi = {10.1109/ISOCC.2012.6407064},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/LeeAC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/issoc/WuALC12,
author = {Di Wu and
Junwhan Ahn and
Imyong Lee and
Kiyoung Choi},
title = {Resource-shared custom instruction generation under performance/area
constraints},
booktitle = {2012 International Symposium on System on Chip, ISSoC 2012, Tampere,
Finland, October 10-12, 2012},
pages = {1--6},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/ISSoC.2012.6376353},
doi = {10.1109/ISSOC.2012.6376353},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/issoc/WuALC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/micro/ParkC12,
author = {Hanmin Park and
Kiyoung Choi},
editor = {Maurizio Palesi and
Terrence S. T. Mak},
title = {Position-based weighted round-robin arbitration for equality of service
in many-core network-on-chips},
booktitle = {Fifth International Workshop on Network on Chip Architectures, NoCArc
'12, Vancouver, BC, Canada, December 1, 2012},
pages = {51--56},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2401716.2401728},
doi = {10.1145/2401716.2401728},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/micro/ParkC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ZhuLC12,
author = {Mingyang Zhu and
Jinho Lee and
Kiyoung Choi},
editor = {Srinivas Katkoori and
Matthew R. Guthaus and
Ayse K. Coskun and
Andreas Burg and
Ricardo Reis},
title = {An adaptive routing algorithm for 3D mesh NoC with limited vertical
bandwidth},
booktitle = {20th {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2012, Santa Cruz, CA, USA, October 7-10, 2012},
pages = {18--23},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-SoC.2012.6378999},
doi = {10.1109/VLSI-SOC.2012.6378999},
timestamp = {Tue, 06 Sep 2022 16:02:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ZhuLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ipsj/Choi11,
author = {Kiyoung Choi},
title = {Coarse-Grained Reconfigurable Array: Architecture and Application
Mapping},
journal = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
volume = {4},
pages = {31--46},
year = {2011},
url = {https://doi.org/10.2197/ipsjtsldm.4.31},
doi = {10.2197/IPSJTSLDM.4.31},
timestamp = {Tue, 29 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ipsj/Choi11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCD11,
author = {Ganghee Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {5},
pages = {637--650},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2010.2098571},
doi = {10.1109/TCAD.2010.2098571},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/AhnLC11,
author = {Junwhan Ahn and
Imyong Lee and
Kiyoung Choi},
title = {A polynomial-time custom instruction identification algorithm based
on dynamic programming},
booktitle = {Proceedings of the 16th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2011, Yokohama, Japan, January 25-27, 2011},
pages = {573--578},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ASPDAC.2011.5722255},
doi = {10.1109/ASPDAC.2011.5722255},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/AhnLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/AhnC11,
author = {Junwhan Ahn and
Kiyoung Choi},
editor = {Robert P. Dick and
Jan Madsen},
title = {An efficient algorithm for isomorphism-aware custom instruction identification
for extensible processors},
booktitle = {Proceedings of the 9th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2011, part of ESWeek '11
Seventh Embedded Systems Week, Taipei, Taiwan, 9-14 October, 2011},
pages = {345--354},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2039370.2039424},
doi = {10.1145/2039370.2039424},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/AhnC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icac/SongC11,
author = {Hyunjik Song and
Kiyoung Choi},
editor = {Hartmut Schmeck and
Wolfgang Rosenstiel and
Tarek F. Abdelzaher and
Joseph L. Hellerstein},
title = {Simulated annealing-based diffusive load balancing on many-core SoC},
booktitle = {Proceedings of the 8th International Conference on Autonomic Computing,
{ICAC} 2011, Karlsruhe, Germany, June 14-18, 2011},
pages = {187--188},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/1998582.1998621},
doi = {10.1145/1998582.1998621},
timestamp = {Tue, 06 Nov 2018 11:06:50 +0100},
biburl = {https://dblp.org/rec/conf/icac/SongC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeC11,
author = {Seokhyun Lee and
Kiyoung Choi},
editor = {Joel R. Phillips and
Alan J. Hu and
Helmut Graeb},
title = {High-level synthesis with distributed controller for fast timing closure},
booktitle = {2011 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2011, San Jose, California, USA, November 7-10, 2011},
pages = {193--199},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCAD.2011.6105325},
doi = {10.1109/ICCAD.2011.6105325},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LeeC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/PaekLC11,
author = {Jong Kyung Paek and
Jong{-}eun Lee and
Kiyoung Choi},
title = {{CRM:} Configurable Range Memory for Fast Reconfigurable Computing},
booktitle = {25th {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2011, Anchorage, Alaska, USA, 16-20 May 2011 - Workshop Proceedings},
pages = {158--165},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/IPDPS.2011.137},
doi = {10.1109/IPDPS.2011.137},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/PaekLC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/LeeZCAS11,
author = {Jinho Lee and
Mingyang Zhu and
Kiyoung Choi and
Jung Ho Ahn and
Rohit Sharma},
title = {3D network-on-chip with wireless links through inductive coupling},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {353--356},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138783},
doi = {10.1109/ISOCC.2011.6138783},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isocc/LeeZCAS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isocc/KimHC11,
author = {Yangsu Kim and
Kyuseung Han and
Kiyoung Choi},
title = {A host-accelerator communication architecture design for efficient
binary acceleration},
booktitle = {International SoC Design Conference, {ISOCC} 2011, Jeju, South Korea,
November 17-18, 2011},
pages = {361--364},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/ISOCC.2011.6138785},
doi = {10.1109/ISOCC.2011.6138785},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isocc/KimHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/nems/ParkCLSK11,
author = {Jae Hong Park and
Kiyoung Choi and
Dong{-}Yeon Lee and
Jaesool Shim and
Tae Song Kim},
title = {Resonant properties of piezoelectric cantilever transducers fabricated
on the SiC membrane},
booktitle = {6th {IEEE} International Conference on Nano/Micro Engineered and Molecular
Systems, {NEMS} 2011, Kaohsiung, Taiwan, February 20-23, 2011},
pages = {61--63},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/NEMS.2011.6017295},
doi = {10.1109/NEMS.2011.6017295},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/nems/ParkCLSK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/LeeALSYC10,
author = {Ganghee Lee and
Yongjin Ahn and
Seokhyun Lee and
Jeongki Son and
Kiwook Yoon and
Kiyoung Choi},
title = {Communication architecture design for reconfigurable multimedia SoC
platform},
journal = {Des. Autom. Embed. Syst.},
volume = {14},
number = {1},
pages = {1--20},
year = {2010},
url = {https://doi.org/10.1007/s10617-009-9048-0},
doi = {10.1007/S10617-009-9048-0},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/LeeALSYC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PaekCL10,
author = {Jong Kyung Paek and
Kiyoung Choi and
Jong{-}eun Lee},
title = {Binary acceleration using coarse-grained reconfigurable architecture},
journal = {{SIGARCH} Comput. Archit. News},
volume = {38},
number = {4},
pages = {33--39},
year = {2010},
url = {https://doi.org/10.1145/1926367.1926374},
doi = {10.1145/1926367.1926374},
timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/sigarch/PaekCL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimMC10,
author = {Yoonjin Kim and
Rabi N. Mahapatra and
Kiyoung Choi},
title = {Design Space Exploration for Efficient Resource Utilization in Coarse-Grained
Reconfigurable Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {18},
number = {10},
pages = {1471--1482},
year = {2010},
url = {https://doi.org/10.1109/TVLSI.2009.2025280},
doi = {10.1109/TVLSI.2009.2025280},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimMC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ahs/LeeC10,
author = {Ganghee Lee and
Kiyoung Choi},
editor = {Tughrul Arslan and
Didier Keymeulen and
David Merodio and
Khaled Benkrid and
Ahmet T. Erdogan and
Umeshkumar D. Patel},
title = {Thermal-aware fault-tolerant system design with coarse-grained reconfigurable
array architecture},
booktitle = {2010 {NASA/ESA} Conference on Adaptive Hardware and Systems, {AHS}
2010, Anaheim, California, USA, June 15-18, 2010},
pages = {265--272},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/AHS.2010.5546249},
doi = {10.1109/AHS.2010.5546249},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ahs/LeeC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/LeeLCD10,
author = {Ganghee Lee and
Seokhyun Lee and
Kiyoung Choi and
Nikil D. Dutt},
editor = {Phaophak Sirisuk and
Fearghal Morgan and
Tarek A. El{-}Ghazawi and
Hideharu Amano},
title = {Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained
Reconfigurable Architecture},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 6th
International Symposium, {ARC} 2010, Bangkok, Thailand, March 17-19,
2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5992},
pages = {231--243},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-12133-3\_22},
doi = {10.1007/978-3-642-12133-3\_22},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/arc/LeeLCD10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/arc/ChangC10,
author = {Kyungwook Chang and
Kiyoung Choi},
editor = {Phaophak Sirisuk and
Fearghal Morgan and
Tarek A. El{-}Ghazawi and
Hideharu Amano},
title = {Memory-Centric Communication Architecture for Reconfigurable Computing},
booktitle = {Reconfigurable Computing: Architectures, Tools and Applications, 6th
International Symposium, {ARC} 2010, Bangkok, Thailand, March 17-19,
2010. Proceedings},
series = {Lecture Notes in Computer Science},
volume = {5992},
pages = {400--405},
publisher = {Springer},
year = {2010},
url = {https://doi.org/10.1007/978-3-642-12133-3\_40},
doi = {10.1007/978-3-642-12133-3\_40},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/arc/ChangC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpt/HanPC10,
author = {Kyuseung Han and
Jong Kyung Paek and
Kiyoung Choi},
editor = {Jinian Bian and
Qiang Zhou and
Peter Athanas and
Yajun Ha and
Kang Zhao},
title = {Acceleration of control flow on {CGRA} using advanced predicated execution},
booktitle = {Proceedings of the International Conference on Field-Programmable
Technology, {FPT} 2010, 8-10 December 2010, Tsinghua University, Beijing,
China},
pages = {429--432},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/FPT.2010.5681452},
doi = {10.1109/FPT.2010.5681452},
timestamp = {Thu, 01 Feb 2018 14:20:39 +0100},
biburl = {https://dblp.org/rec/conf/fpt/HanPC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ipps/LeeCC10,
author = {Ganghee Lee and
Kyungwook Chang and
Kiyoung Choi},
title = {Automatic mapping of control-intensive kernels onto coarse-grained
reconfigurable array architecture with speculative execution},
booktitle = {24th {IEEE} International Symposium on Parallel and Distributed Processing,
{IPDPS} 2010, Atlanta, Georgia, USA, 19-23 April 2010 - Workshop Proceedings},
pages = {1--4},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/IPDPSW.2010.5470746},
doi = {10.1109/IPDPSW.2010.5470746},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ipps/LeeCC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimMPC09,
author = {Yoonjin Kim and
Rabi N. Mahapatra and
Ilhyun Park and
Kiyoung Choi},
title = {Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable
Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {5},
pages = {593--603},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2006039},
doi = {10.1109/TVLSI.2008.2006039},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimMPC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YooYC09,
author = {Jun{-}hee Yoo and
Sungjoo Yoo and
Kiyoung Choi},
title = {Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {8},
pages = {1034--1047},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2009.2017442},
doi = {10.1109/TVLSI.2009.2017442},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YooYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChoC09,
author = {Youngchul Cho and
Kiyoung Choi},
editor = {Kazutoshi Wakabayashi},
title = {Code decomposition and recomposition for enhancing embedded software
performance},
booktitle = {Proceedings of the 14th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2009, Yokohama, Japan, January 19-22, 2009},
pages = {624--629},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/ASPDAC.2009.4796550},
doi = {10.1109/ASPDAC.2009.4796550},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChoC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/YooYC09,
author = {Jun{-}hee Yoo and
Sungjoo Yoo and
Kiyoung Choi},
title = {Multiprocessor System-on-Chip designs with active memory processors
for higher memory efficiency},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {806--811},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630118},
doi = {10.1145/1629911.1630118},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/YooYC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ichit/JoLCHCYY09,
author = {Manhwee Jo and
Ganghee Lee and
Kyungwook Chang and
Kyuseung Han and
Kiyoung Choi and
Hoonmo Yang and
Kiwook Yoon},
editor = {Geuk Lee and
Daniel Howard and
Jeong Jin Kang and
Dominik Slezak and
Tae Nam Ahn and
Chung{-}Huang Yang},
title = {Coarse-grained reconfigurable architecture for multiple application
domains: a case study},
booktitle = {Proceedings of the 2009 International Conference on Hybrid Information
Technology, {ICHIT} 2009, Daejeon, Korea, August 27-29, 2009},
series = {{ACM} International Conference Proceeding Series},
volume = {321},
pages = {546--553},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1644993.1645095},
doi = {10.1145/1644993.1645095},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ichit/JoLCHCYY09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijes/LeeCD08,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Evaluating memory architectures for media applications on Coarse-grained
Reconfigurable Architectures},
journal = {Int. J. Embed. Syst.},
volume = {3},
number = {3},
pages = {119--127},
year = {2008},
url = {https://doi.org/10.1504/IJES.2008.020293},
doi = {10.1504/IJES.2008.020293},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijes/LeeCD08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/HaCKFMY08,
author = {Soonhoi Ha and
Kiyoung Choi and
Taewhan Kim and
Kriszti{\'{a}}n Flautner and
Sang Lyul Min and
Wang Yi},
title = {Introduction to embedded systems week 2006 special issue},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {7},
number = {2},
pages = {8:1--8:3},
year = {2008},
url = {https://doi.org/10.1145/1331331.1331332},
doi = {10.1145/1331331.1331332},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/HaCKFMY08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/AhnHLSYCF08,
author = {Yongjin Ahn and
Keesung Han and
Ganghee Lee and
Hyunjik Song and
Jun{-}hee Yoo and
Kiyoung Choi and
Xingguang Feng},
title = {SoCDAL: System-on-chip design AcceLerator},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {13},
number = {1},
pages = {17:1--17:38},
year = {2008},
url = {https://doi.org/10.1145/1297666.1297683},
doi = {10.1145/1297666.1297683},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/AhnHLSYCF08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LeeYC08,
author = {Dongwook Lee and
Sungjoo Yoo and
Kiyoung Choi},
editor = {Vijaykrishnan Narayanan and
C. P. Ravikumar and
J{\"{o}}rg Henkel and
Ali Keshavarzi and
Vojin G. Oklobdzija and
Barry M. Pangrle},
title = {Entry control in network-on-chip for memory power reduction},
booktitle = {Proceedings of the 2008 International Symposium on Low Power Electronics
and Design, 2008, Bangalore, India, August 11-13, 2008},
pages = {171--176},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1393921.1393967},
doi = {10.1145/1393921.1393967},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/LeeYC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AravaJLC08,
author = {V. K. Prasad Arava and
Manhwee Jo and
HyoukJoong Lee and
Kiyoung Choi},
title = {A Generic Design for Encoding and Decoding Variable Length Codes in
Multi-codec Video Processing Engines},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2008, 7-9
April 2008, Montpellier, France},
pages = {197--202},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISVLSI.2008.49},
doi = {10.1109/ISVLSI.2008.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AravaJLC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/aspdac/2008,
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
publisher = {{IEEE}},
year = {2008},
url = {https://ieeexplore.ieee.org/xpl/conhome/4480121/proceeding},
isbn = {978-1-4244-1921-0},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/2008.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/ChoZYJC07,
author = {Youngchul Cho and
Nacer{-}Eddine Zergainoh and
Sungjoo Yoo and
Ahmed Amine Jerraya and
Kiyoung Choi},
title = {Scheduling with accurate communication delay model and scheduler implementation
for multiprocessor system-on-chip},
journal = {Des. Autom. Embed. Syst.},
volume = {11},
number = {2-3},
pages = {167--191},
year = {2007},
url = {https://doi.org/10.1007/s10617-007-9004-9},
doi = {10.1007/S10617-007-9004-9},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/ChoZYJC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/JungYC07,
author = {Jinyong Jung and
Sungjoo Yoo and
Kiyoung Choi},
title = {Fast cycle-approximate MPSoC simulation based on synchronization time-point
prediction},
journal = {Des. Autom. Embed. Syst.},
volume = {11},
number = {4},
pages = {223--247},
year = {2007},
url = {https://doi.org/10.1007/s10617-007-9010-y},
doi = {10.1007/S10617-007-9010-Y},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/JungYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LeeCD07,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Instruction set synthesis with efficient instruction encoding for
configurable processors},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {12},
number = {1},
pages = {9:1--9:37},
year = {2007},
url = {https://doi.org/10.1145/1217088.1217096},
doi = {10.1145/1217088.1217096},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LeeCD07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/LeeLC07,
author = {Imyong Lee and
Dongwook Lee and
Kiyoung Choi},
title = {Memory Operation Inclusive Instruction-Set Extensions and Data Path
Generation},
booktitle = {{IEEE} International Conference on Application-Specific Systems, Architectures
and Processors, {ASAP} 2007, Montr{\'{e}}al, Qu{\'{e}}bec,
Canada, July 8-11, 2007},
pages = {383--390},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASAP.2007.4459294},
doi = {10.1109/ASAP.2007.4459294},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/LeeLC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YooLYC07,
author = {Jun{-}hee Yoo and
Dongwook Lee and
Sungjoo Yoo and
Kiyoung Choi},
title = {Communication Architecture Synthesis of Cascaded Bus Matrix},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {171--177},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357981},
doi = {10.1109/ASPDAC.2007.357981},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/YooLYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ChoZCJ07,
author = {Youngchul Cho and
Nacer{-}Eddine Zergainoh and
Kiyoung Choi and
Ahmed Amine Jerraya},
title = {Low Runtime-Overhead Software Synthesis for Communicating Concurrent
Processes},
booktitle = {18th {IEEE} International Workshop on Rapid System Prototyping {(RSP}
2007), 28-30 May 2007, Porto Alegre, RS, Brazil},
pages = {195--201},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/RSP.2007.27},
doi = {10.1109/RSP.2007.27},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/ChoZCJ07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/ChoZJC07,
author = {Youngchul Cho and
Nacer{-}Eddine Zergainoh and
Ahmed Amine Jerraya and
Kiyoung Choi},
title = {Buffer Size Reduction through Control-Flow Decomposition},
booktitle = {13th {IEEE} International Conference on Embedded and Real-Time Computing
Systems and Applications {(RTCSA} 2007), 21-24 August 2007, Daegu,
Korea},
pages = {183--190},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/RTCSA.2007.25},
doi = {10.1109/RTCSA.2007.25},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/ChoZJC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/samos/LeeLAC07,
author = {Ganghee Lee and
Seokhyun Lee and
Yongjin Ahn and
Kiyoung Choi},
editor = {Holger Blume and
Georgi Gaydadjiev and
C. John Glossner and
Peter M. W. Knijnenburg},
title = {Automatic Bus Matrix Synthesis based on Hardware Interface Selection
for Fast Communication Design Space Exploration},
booktitle = {Proceedings of the 2007 International Conference on Embedded Computer
Systems: Architectures, Modeling and Simulation {(IC-SAMOS} 2007),
Samos, Greece, July 16-19, 2007},
pages = {50--57},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ICSAMOS.2007.4285733},
doi = {10.1109/ICSAMOS.2007.4285733},
timestamp = {Thu, 25 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/samos/LeeLAC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/JoAYC07,
author = {Manhwee Jo and
V. K. Prasad Arava and
Hoonmo Yang and
Kiyoung Choi},
title = {Implementation of floating-point operations for 3D graphics on a coarse-grained
reconfigurable architecture},
booktitle = {2007 {IEEE} International {SOC} Conference, Tampere, Finland, November
19-21, 2007},
pages = {127--130},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/SOCC.2007.4545442},
doi = {10.1109/SOCC.2007.4545442},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/JoAYC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/codes/2007,
editor = {Soonhoi Ha and
Kiyoung Choi and
Nikil D. Dutt and
J{\"{u}}rgen Teich},
title = {Proceedings of the 5th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1289816},
doi = {10.1145/1289816},
isbn = {978-1-59593-824-4},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-0710-4704,
author = {Yoonjin Kim and
Mary Kiemb and
Chulsoo Park and
Jinyong Jung and
Kiyoung Choi},
title = {Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture
for Domain-Specific Optimization},
journal = {CoRR},
volume = {abs/0710.4704},
year = {2007},
url = {http://arxiv.org/abs/0710.4704},
eprinttype = {arXiv},
eprint = {0710.4704},
timestamp = {Mon, 13 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-0710-4704.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/YooFCCC06,
author = {Jun{-}hee Yoo and
Xingguang Feng and
Kiyoung Choi and
Eui{-}Young Chung and
Kyu{-}Myung Choi},
editor = {Fumiyasu Hirose},
title = {Worst case execution time analysis for synthesized hardware},
booktitle = {Proceedings of the 2006 Conference on Asia South Pacific Design Automation:
{ASP-DAC} 2006, Yokohama, Japan, January 24-27, 2006},
pages = {905--910},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ASPDAC.2006.1594801},
doi = {10.1109/ASPDAC.2006.1594801},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/YooFCCC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/AhnYPKKC06,
author = {Minwook Ahn and
Jonghee W. Yoon and
Yunheung Paek and
Yoonjin Kim and
Mary Kiemb and
Kiyoung Choi},
editor = {Georges G. E. Gielen},
title = {A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable
architectures},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {363--368},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.243737},
doi = {10.1109/DATE.2006.243737},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/AhnYPKKC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimPCP06,
author = {Yoonjin Kim and
Ilhyun Park and
Kiyoung Choi and
Yunheung Paek},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Power-conscious configuration cache structure and code mapping for
coarse-grained reconfigurable architecture},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {310--315},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165646},
doi = {10.1145/1165573.1165646},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KimPCP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/codes/2006,
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254},
doi = {10.1145/1176254},
isbn = {1-59593-370-0},
timestamp = {Mon, 26 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSC05,
author = {Daehong Kim and
Dongwan Shin and
Kiyoung Choi},
title = {Pipelining with common operands for power-efficient linear systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1023--1034},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857146},
doi = {10.1109/TVLSI.2005.857146},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ChoYCZJ05,
author = {Youngchul Cho and
Sungjoo Yoo and
Kiyoung Choi and
Nacer{-}Eddine Zergainoh and
Ahmed Amine Jerraya},
editor = {Tingao Tang},
title = {Scheduler implementation in {MP} SoC design},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {151--156},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120793},
doi = {10.1145/1120725.1120793},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ChoYCZJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KimKPJC05,
author = {Yoonjin Kim and
Mary Kiemb and
Chulsoo Park and
Jinyong Jung and
Kiyoung Choi},
title = {Resource Sharing and Pipelining in Coarse-Grained Reconfigurable Architecture
for Domain-Specific Optimization},
booktitle = {2005 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2005), 7-11 March 2005, Munich, Germany},
pages = {12--17},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/DATE.2005.260},
doi = {10.1109/DATE.2005.260},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KimKPJC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/KiembC04,
author = {Mary Kiemb and
Kiyoung Choi},
editor = {Mary Jane Irwin and
Wei Zhao and
Luciano Lavagno and
Scott A. Mahlke},
title = {Memory and architecture exploration with thread shifting for multithreaded
processors in embedded systems},
booktitle = {Proceedings of the 2004 International Conference on Compilers, Architecture,
and Synthesis for Embedded Systems, {CASES} 2004, Washington DC, USA,
September 22 - 25, 2004},
pages = {230--237},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1023833.1023865},
doi = {10.1145/1023833.1023865},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/KiembC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icra/KimCY04,
author = {Whee Kuk Kim and
Kiyoung Choi and
Byung{-}Ju Yi},
title = {A Mobility Analysis Method of Closed-chain Mechanisms with Over-constraints
and Non-holonomic Constraints},
booktitle = {Proceedings of the 2004 {IEEE} International Conference on Robotics
and Automation, {ICRA} 2004, April 26 - May 1, 2004, New Orleans,
LA, {USA}},
pages = {2801--2807},
publisher = {{IEEE}},
year = {2004},
url = {https://doi.org/10.1109/ROBOT.2004.1307485},
doi = {10.1109/ROBOT.2004.1307485},
timestamp = {Mon, 22 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icra/KimCY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KiembC04,
author = {Mary Kiemb and
Kiyoung Choi},
title = {Application-specific configuration of multithreaded processor architecture
for embedded applications},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {941--944},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KiembC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/islped/2004,
editor = {Rajiv V. Joshi and
Kiyoung Choi and
Vivek Tiwari and
Kaushik Roy},
title = {Proceedings of the 2004 International Symposium on Low Power Electronics
and Design, 2004, Newport Beach, California, USA, August 9-11, 2004},
publisher = {{ACM}},
year = {2004},
timestamp = {Wed, 27 Jul 2016 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/computer/DuttC03,
author = {Nikil D. Dutt and
Kiyoung Choi},
title = {Configurable Processors for Embedded Computing},
journal = {Computer},
volume = {36},
number = {1},
pages = {120--123},
year = {2003},
url = {https://doi.org/10.1109/MC.2003.1160063},
doi = {10.1109/MC.2003.1160063},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/computer/DuttC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/AhnKLPYCC03,
author = {Yongjin Ahn and
Daehong Kim and
Sunghyun Lee and
Sanggyu Park and
Sungjoo Yoo and
Kiyoung Choi and
Soo{-}Ik Chae},
title = {An Efficient Simulation Environment and Simulation Techniques for
Bluetooth Device Design},
journal = {Des. Autom. Embed. Syst.},
volume = {8},
number = {2-3},
pages = {119--138},
year = {2003},
url = {https://doi.org/10.1023/B:DAEM.0000003958.67283.86},
doi = {10.1023/B:DAEM.0000003958.67283.86},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/AhnKLPYCC03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/LeeCD03,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Compilation Approach for Coarse-Grained Reconfigurable Architectures},
journal = {{IEEE} Des. Test Comput.},
volume = {20},
number = {1},
pages = {26--33},
year = {2003},
url = {https://doi.org/10.1109/MDT.2003.1173050},
doi = {10.1109/MDT.2003.1173050},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/LeeCD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/LeeCD03,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
title = {Evaluating Memory Architectures for Media Applications on Coarse-Grained
Recon.gurable Architectures},
booktitle = {14th {IEEE} International Conference on Application-Specific Systems,
Architectures, and Processors {(ASAP} 2003), 24-26 June 2003, The
Hague, The Netherlands},
pages = {172--182},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ASAP.2003.10002},
doi = {10.1109/ASAP.2003.10002},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/LeeCD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChoLYCZ03,
author = {Youngchul Cho and
Ganghee Lee and
Sungjoo Yoo and
Kiyoung Choi and
Nacer{-}Eddine Zergainoh},
title = {Scheduling and Timing Analysis of {HW/SW} On-Chip Communication in
{MP} SoC Design},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {20132--20137},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/DATE.2003.1186684},
doi = {10.1109/DATE.2003.1186684},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ChoLYCZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LeeCD03,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
editor = {Ingrid Verbauwhede and
Hyung Roh},
title = {Energy-efficient instruction set synthesis for application-specific
processors},
booktitle = {Proceedings of the 2003 International Symposium on Low Power Electronics
and Design, 2003, Seoul, Korea, August 25-27, 2003},
pages = {330--333},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/871506.871588},
doi = {10.1145/871506.871588},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/LeeCD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lctrts/LeeCD03,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
editor = {Frank Mueller and
Ulrich Kremer},
title = {An algorithm for mapping loops onto coarse-grained reconfigurable
architectures},
booktitle = {Proceedings of the 2003 Conference on Languages, Compilers, and Tools
for Embedded Systems (LCTES'03). San Diego, California, USA, June
11-13, 2003},
pages = {183--188},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/780732.780758},
doi = {10.1145/780732.780758},
timestamp = {Fri, 25 Jun 2021 17:17:37 +0200},
biburl = {https://dblp.org/rec/conf/lctrts/LeeCD03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@incollection{DBLP:books/sp/03/ChoLCYZ03,
author = {Youngchul Cho and
Ganghee Lee and
Kiyoung Choi and
Sungjoo Yoo and
Nacer{-}Eddine Zergainoh},
editor = {Ahmed Amine Jerraya and
Sungjoo Yoo and
Diederik Verkest and
Norbert Wehn},
title = {Scheduling and Timing Analysis of {HW/SW} On-Chip Communication in
{MP} SoC Design},
booktitle = {Embedded Software for SoC},
pages = {125--136},
publisher = {Kluwer / Springer},
year = {2003},
url = {https://doi.org/10.1007/0-306-48709-8\_10},
doi = {10.1007/0-306-48709-8\_10},
timestamp = {Thu, 04 Jul 2019 16:02:30 +0200},
biburl = {https://dblp.org/rec/books/sp/03/ChoLCYZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LeeYC02,
author = {Sunghyun Lee and
Sungjoo Yoo and
Kiyoung Choi},
editor = {J{\"{o}}rg Henkel and
Xiaobo Sharon Hu and
Rajesh Gupta and
Sri Parameswaran},
title = {Reconfigurable SoC design with hierarchical {FSM} and synchronous
dataflow model},
booktitle = {Proceedings of the Tenth International Symposium on Hardware/Software
Codesign, {CODES} 2002, Estes Park, Colorado, USA, May 6-8, 2002},
pages = {199--204},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/774789.774830},
doi = {10.1145/774789.774830},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/LeeYC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/LeeCD02,
author = {Jong{-}eun Lee and
Kiyoung Choi and
Nikil D. Dutt},
editor = {Lawrence T. Pileggi and
Andreas Kuehlmann},
title = {Efficient instruction encoding for automatic instruction set design
of configurable ASIPs},
booktitle = {Proceedings of the 2002 {IEEE/ACM} International Conference on Computer-aided
Design, {ICCAD} 2002, San Jose, California, USA, November 10-14, 2002},
pages = {649--654},
publisher = {{ACM} / {IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1145/774572.774668},
doi = {10.1145/774572.774668},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/LeeCD02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/LeeCY02,
author = {Sunghyun Lee and
Kiyoung Choi and
Sungjoo Yoo},
editor = {Vivek De and
Mary Jane Irwin and
Ingrid Verbauwhede and
Christian Piguet},
title = {An intra-task dynamic voltage scaling method for SoC design with hierarchical
{FSM} and synchronous dataflow model},
booktitle = {Proceedings of the 2002 International Symposium on Low Power Electronics
and Design, 2002, Monterey, California, USA, August 12-14, 2002},
pages = {84--87},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/566408.566432},
doi = {10.1145/566408.566432},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/LeeCY02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkC01,
author = {Sanghun Park and
Kiyoung Choi},
title = {Performance-driven high-level synthesis with bit-level chaining andclock
selection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {20},
number = {2},
pages = {199--212},
year = {2001},
url = {https://doi.org/10.1109/43.908436},
doi = {10.1109/43.908436},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinCC01,
author = {Youngsoo Shin and
Soo{-}Ik Chae and
Kiyoung Choi},
title = {Partial bus-invert coding for power optimization of application-specific
systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {2},
pages = {377--383},
year = {2001},
url = {https://doi.org/10.1109/92.924059},
doi = {10.1109/92.924059},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinCC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShinCC01a,
author = {Youngsoo Shin and
Kiyoung Choi and
Young{-}Hoon Chang},
title = {Narrow bus encoding for low-power {DSP} systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {9},
number = {5},
pages = {656--660},
year = {2001},
url = {https://doi.org/10.1109/92.953499},
doi = {10.1109/92.953499},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShinCC01a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ShinCS01,
author = {Youngsoo Shin and
Kiyoung Choi and
Takayasu Sakurai},
title = {Power-conscious Scheduling for Real-time Embedded Systems Design},
journal = {{VLSI} Design},
volume = {12},
number = {2},
pages = {139--150},
year = {2001},
url = {https://doi.org/10.1155/2001/23925},
doi = {10.1155/2001/23925},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ShinCS01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JeonKSC01,
author = {Jinhwan Jeon and
Daehong Kim and
Dongwan Shin and
Kiyoung Choi},
editor = {Satoshi Goto},
title = {High-level synthesis under multi-cycle interconnect delay},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {662},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370576},
doi = {10.1145/370155.370576},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JeonKSC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/RhaC01,
author = {Kyoungseok Rha and
Kiyoung Choi},
editor = {Jan Madsen and
J{\"{o}}rg Henkel and
Xiaobo Sharon Hu},
title = {Area-efficient buffer binding based on a novel two-port {FIFO} structure},
booktitle = {Proceedings of the Ninth International Symposium on Hardware/Software
Codesign, {CODES} 2001, Copenhagen, Denmark, 2001},
pages = {122--127},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/371636.371700},
doi = {10.1145/371636.371700},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/RhaC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LimKC01,
author = {Sungtaek Lim and
Jihong Kim and
Kiyoung Choi},
editor = {Jan Madsen and
J{\"{o}}rg Henkel and
Xiaobo Sharon Hu},
title = {Scheduling-based code size reduction in processors with indirect addressing
mode},
booktitle = {Proceedings of the Ninth International Symposium on Hardware/Software
Codesign, {CODES} 2001, Copenhagen, Denmark, 2001},
pages = {165--169},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/371636.371710},
doi = {10.1145/371636.371710},
timestamp = {Thu, 13 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/LimKC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/JungYC01,
author = {Jinyong Jung and
Sungjoo Yoo and
Kiyoung Choi},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Performance improvement of multi-processor systems cosimulation based
on {SW} analysis},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {749--753},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915112},
doi = {10.1109/DATE.2001.915112},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/JungYC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/KimJLJC01,
author = {Daehong Kim and
Jinyong Jung and
Sunghyun Lee and
Jinhwan Jeon and
Kiyoung Choi},
editor = {Rolf Ernst},
title = {Behavior-to-Placed {RTL} Synthesis with Performance-Driven Placement},
booktitle = {Proceedings of the 2001 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 2001, San Jose, CA, USA, November 4-8, 2001},
pages = {320},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/ICCAD.2001.968640},
doi = {10.1109/ICCAD.2001.968640},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/KimJLJC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KimSC01,
author = {Daehong Kim and
Dongwan Shin and
Kiyoung Choi},
editor = {Enrico Macii and
Vivek De and
Mary Jane Irwin},
title = {Low power pipelining of linear systems: a common operand centric approach},
booktitle = {Proceedings of the 2001 International Symposium on Low Power Electronics
and Design, 2001, Huntington Beach, California, USA, 2001},
pages = {225--230},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/383082.383141},
doi = {10.1145/383082.383141},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/KimSC01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/YooC00,
author = {Sungjoo Yoo and
Kiyoung Choi},
title = {Optimizing Timed Cosimulation by Hybrid Synchronization},
journal = {Des. Autom. Embed. Syst.},
volume = {5},
number = {2},
pages = {129--152},
year = {2000},
url = {https://doi.org/10.1023/A:1008995606614},
doi = {10.1023/A:1008995606614},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/YooC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YooCH00,
author = {Sungjoo Yoo and
Kiyoung Choi and
Dong Sam Ha},
title = {Performance improvement of geographically distributed cosimulation
by hierarchically grouped messages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {8},
number = {5},
pages = {492--502},
year = {2000},
url = {https://doi.org/10.1109/92.894153},
doi = {10.1109/92.894153},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YooCH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JeongYLC00,
author = {Byungil Jeong and
Sungjoo Yoo and
Sunghyun Lee and
Kiyoung Choi},
title = {Hardware-software cosynthesis for run-time incrementally reconfigurable
FPGAs},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {169--174},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368598},
doi = {10.1145/368434.368598},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/JeongYLC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ShinC00,
author = {Youngsoo Shin and
Kiyoung Choi},
title = {Narrow bus encoding for low power systems},
booktitle = {Proceedings of {ASP-DAC} 2000, Asia and South Pacific Design Automation
Conference 2000, Yokohama, Japan},
pages = {217--220},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/368434.368609},
doi = {10.1145/368434.368609},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/ShinC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/YooRCJC00,
author = {Sungjoo Yoo and
Kyoungseok Rha and
Youngchul Cho and
Jinyong Jung and
Kiyoung Choi},
editor = {Frank Vahid and
Jan Madsen},
title = {Performance estimation of multiple-cache IP-based systems: case study
of an interdependency problem and application of an extended shared
memory model},
booktitle = {Proceedings of the Eighth International Workshop on Hardware/Software
Codesign, {CODES} 2000, San Diego, California, USA, 2000},
pages = {77--81},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/334012.334027},
doi = {10.1145/334012.334027},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/YooRCJC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ShinKC00,
author = {Youngsoo Shin and
Daehong Kim and
Kiyoung Choi},
editor = {Giovanni De Micheli},
title = {Schedulability-driven performance analysis of multiple mode embedded
real-time systems},
booktitle = {Proceedings of the 37th Conference on Design Automation, Los Angeles,
CA, USA, June 5-9, 2000},
pages = {495--500},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/337292.337556},
doi = {10.1145/337292.337556},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ShinKC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/YooLJRCC00,
author = {Sungjoo Yoo and
Jong{-}eun Lee and
Jinyong Jung and
Kyungseok Rha and
Youngchul Cho and
Kiyoung Choi},
editor = {Ivo Bolsens},
title = {Fast Hardware-Software Coverification by Optimistic Execution of Real
Processor},
booktitle = {2000 Design, Automation and Test in Europe {(DATE} 2000), 27-30 March
2000, Paris, France},
pages = {663--668},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2000},
url = {https://doi.org/10.1109/DATE.2000.840857},
doi = {10.1109/DATE.2000.840857},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/YooLJRCC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ShinCS00,
author = {Youngsoo Shin and
Kiyoung Choi and
Takayasu Sakurai},
editor = {Ellen Sentovich},
title = {Power Optimization of Real-Time Embedded Systems on Variable Speed
Processors},
booktitle = {Proceedings of the 2000 {IEEE/ACM} International Conference on Computer-Aided
Design, 2000, San Jose, California, USA, November 5-9, 2000},
pages = {365--368},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/ICCAD.2000.896499},
doi = {10.1109/ICCAD.2000.896499},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ShinCS00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/AhnCKH00,
author = {Taekyoon Ahn and
Kiyoung Choi and
Ki{-}Hyun Kim and
Seong{-}Kwan Hon},
title = {A new cost model for high-level power optimization and its application},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2000,
Emerging Technologies for the 21st Century, Geneva, Switzerland, 28-31
May 2000, Proceedings},
pages = {573--576},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/ISCAS.2000.856393},
doi = {10.1109/ISCAS.2000.856393},
timestamp = {Fri, 13 Aug 2021 09:26:01 +0200},
biburl = {https://dblp.org/rec/conf/iscas/AhnCKH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChoiJC00,
author = {Junghwan Choi and
Jinhwan Jeon and
Kiyoung Choi},
editor = {David T. Blaauw and
Christian C. Enz and
Thaddeus Gabara and
Enrico Macii},
title = {Power minimization of functional units partially guarded computation},
booktitle = {Proceedings of the 2000 International Symposium on Low Power Electronics
and Design, 2000, Rapallo, Italy, July 25-27, 2000},
pages = {131--136},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/344166.344549},
doi = {10.1145/344166.344549},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChoiJC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/WonC00,
author = {Jae{-}Hee Won and
Kiyoung Choi},
editor = {David T. Blaauw and
Christian C. Enz and
Thaddeus Gabara and
Enrico Macii},
title = {Low power self-timed Radix-2 division (poster session)},
booktitle = {Proceedings of the 2000 International Symposium on Low Power Electronics
and Design, 2000, Rapallo, Italy, July 25-27, 2000},
pages = {210--212},
publisher = {{ACM}},
year = {2000},
url = {https://doi.org/10.1145/344166.344590},
doi = {10.1145/344166.344590},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/WonC00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/YooC99,
author = {Sungjoo Yoo and
Kiyoung Choi},
editor = {Ahmed Amine Jerraya and
Luciano Lavagno and
Frank Vahid},
title = {Optimizing geographically distributed timed cosimulation by hierarchically
grouped messages},
booktitle = {Proceedings of the Seventh International Workshop on Hardware/Software
Codesign, {CODES} 1999, Rome, Italy, 1999},
pages = {100--104},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/301177.301497},
doi = {10.1145/301177.301497},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/YooC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ShinC99,
author = {Youngsoo Shin and
Kiyoung Choi},
editor = {Mary Jane Irwin},
title = {Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {134--139},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309901},
doi = {10.1145/309847.309901},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ShinC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ParkC99,
author = {Sanghun Park and
Kiyoung Choi},
editor = {Mary Jane Irwin},
title = {Performance-Driven Scheduling with Bit-Level Chaining},
booktitle = {Proceedings of the 36th Conference on Design Automation, New Orleans,
LA, USA, June 21-25, 1999},
pages = {286--291},
publisher = {{ACM} Press},
year = {1999},
url = {https://doi.org/10.1145/309847.309932},
doi = {10.1145/309847.309932},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ParkC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JeongYC99,
author = {Byungil Jeong and
Sungjoo Yoo and
Kiyoung Choi},
editor = {Sinan Kaptanoglu and
Steve Trimberger},
title = {Exploiting Early Partial Reconfiguration of Run-Time Reconfigurable
FPGAs in Embedded Systems Design},
booktitle = {Proceedings of the 1999 {ACM/SIGDA} Seventh International Symposium
on Field Programmable Gate Arrays, {FPGA} 1999, Monterey, CA, USA,
February 21-23, 1999},
pages = {247},
publisher = {{ACM}},
year = {1999},
url = {https://doi.org/10.1145/296399.296508},
doi = {10.1145/296399.296508},
timestamp = {Tue, 06 Nov 2018 16:58:22 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JeongYC99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/KimKSAC98,
author = {Yongjoo Kim and
Kyuseok Kim and
Youngsoo Shin and
Taekyoon Ahn and
Kiyoung Choi},
title = {An Integrated Cosimulation Environment for Heterogeneous Systems Prototyping},
journal = {Des. Autom. Embed. Syst.},
volume = {3},
number = {2-3},
pages = {163--186},
year = {1998},
url = {https://doi.org/10.1023/A:1008842424479},
doi = {10.1023/A:1008842424479},
timestamp = {Fri, 02 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/KimKSAC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/JeonC98,
author = {Jinhwan Jeon and
Kiyoung Choi},
title = {Loop Pipelining in Hardware-Software Partitioning},
booktitle = {Proceedings of the {ASP-DAC} '98, Asia and South Pacific Design Automation
Conference 1998, Pacifico Yokohama, Yokohama, Japan, February 10-13,
1998},
pages = {361--366},
publisher = {{IEEE}},
year = {1998},
url = {https://doi.org/10.1109/ASPDAC.1998.669501},
doi = {10.1109/ASPDAC.1998.669501},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/JeonC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/YooC98,
author = {Sungjoo Yoo and
Kiyoung Choi},
editor = {Gaetano Borriello and
Ahmed Amine Jerraya and
Luciano Lavagno},
title = {Optimistic distributed timed cosimulation based on thread simulation
model},
booktitle = {Proceedings of the Sixth International Workshop on Hardware/Software
Codesign, {CODES} 1998, Seattle, Washington, USA, March 15-18, 1998},
pages = {71--75},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/278241.278300},
doi = {10.1145/278241.278300},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/YooC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/ShinC98,
author = {Youngsoo Shin and
Kiyoung Choi},
title = {Rate Assignment for Embedded Reactive Real-Time Systems},
booktitle = {24th {EUROMICRO} '98 Conference, Engineering Systems and Software
for the Next Decade, 25-27 August 1998, Vesteras, Sweden},
pages = {10237},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/EURMIC.1998.711806},
doi = {10.1109/EURMIC.1998.711806},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/euromicro/ShinC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ShinCC98,
author = {Youngsoo Shin and
Soo{-}Ik Chae and
Kiyoung Choi},
editor = {Anantha P. Chandrakasan and
Sayfe Kiaei},
title = {Partial bus-invert coding for power optimization of system level bus},
booktitle = {Proceedings of the 1998 International Symposium on Low Power Electronics
and Design, 1998, Monterey, California, USA, August 10-12, 1998},
pages = {127--129},
publisher = {{ACM}},
year = {1998},
url = {https://doi.org/10.1145/280756.280829},
doi = {10.1145/280756.280829},
timestamp = {Mon, 27 Sep 2021 11:47:11 +0200},
biburl = {https://dblp.org/rec/conf/islped/ShinCC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ShinC97,
author = {Youngsoo Shin and
Kiyoung Choi},
title = {Enforcing Schedulability of Multi-Task Systems by Hardware-Software
Codesign},
booktitle = {Proceedings of the Fifth International Workshop on Hardware/Software
Codesign, {CODES/CASHE} 1997, March 24-26, 1997, Braunschweig, Germany},
pages = {3--7},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/HSC.1997.584571},
doi = {10.1109/HSC.1997.584571},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/ShinC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/KimC97,
author = {Daehong Kim and
Kiyoung Choi},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Power-conscious High Level Synthesis Using Loop Folding},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {441--445},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266194},
doi = {10.1145/266021.266194},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/KimC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ShinC97,
author = {Dongwan Shin and
Kiyoung Choi},
editor = {Brock Barton and
Massoud Pedram and
Anantha P. Chandrakasan and
Sayfe Kiaei},
title = {Low power high level synthesis by increasing data correlation},
booktitle = {Proceedings of the 1997 International Symposium on Low Power Electronics
and Design, 1997, Monterey, California, USA, August 18-20, 1997},
pages = {62--67},
publisher = {{ACM}},
year = {1997},
url = {https://doi.org/10.1145/263272.263284},
doi = {10.1145/263272.263284},
timestamp = {Mon, 27 Sep 2021 11:47:11 +0200},
biburl = {https://dblp.org/rec/conf/islped/ShinC97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeC96,
author = {KiJong Lee and
Kiyoung Choi},
title = {Self-timed divider based on {RSD} number system},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {4},
number = {2},
pages = {292--295},
year = {1996},
url = {https://doi.org/10.1109/92.502202},
doi = {10.1109/92.502202},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ShinC96,
author = {Youngsoo Shin and
Kiyoung Choi},
title = {Thread-based software synthesis for embedded system design},
booktitle = {1996 European Design and Test Conference, ED{\&}TC 1996, Paris,
France, March 11-14, 1996},
pages = {282--287},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/EDTC.1996.494314},
doi = {10.1109/EDTC.1996.494314},
timestamp = {Fri, 20 May 2022 15:52:30 +0200},
biburl = {https://dblp.org/rec/conf/date/ShinC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ShinC96,
author = {Youngsoo Shin and
Kiyoung Choi},
editor = {Rob A. Rutenbar and
Ralph H. J. M. Otten},
title = {Software synthesis through task decomposition by dependency analysis},
booktitle = {Proceedings of the 1996 {IEEE/ACM} International Conference on Computer-Aided
Design, {ICCAD} 1996, San Jose, CA, USA, November 10-14, 1996},
pages = {98--104},
publisher = {{IEEE} Computer Society / {ACM}},
year = {1996},
url = {https://doi.org/10.1109/ICCAD.1996.569170},
doi = {10.1109/ICCAD.1996.569170},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ShinC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/KimKSC96,
author = {Kyuseok Kim and
Yongjoo Kim and
Youngsoo Shin and
Kiyoung Choi},
title = {An integrated hardware-software cosimulation environment with automated
interface generation},
booktitle = {Seventh {IEEE} International Workshop on Rapid System Prototyping
{(RSP} '96), Thessaloniki, Greece, June 19-21, 1996},
pages = {66--71},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/IWRSP.1996.506729},
doi = {10.1109/IWRSP.1996.506729},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/KimKSC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/YooJHC96,
author = {Sungjoo Yoo and
Jinhwan Jeon and
Seongsoo Hong and
Kiyoung Choi},
title = {Hardware-Software Codesign of Resource-Constrained Real-Time Systems},
booktitle = {Third International Workshop on Real-Time Computing Systems Application
{(RTCSA} '96), October 30 - November 01, 1996, Seoul, Korea},
pages = {286},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/RTCSA.1996.554988},
doi = {10.1109/RTCSA.1996.554988},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rtcsa/YooJHC96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/KimKSASCS95,
author = {Yongjoo Kim and
Kyuseok Kim and
Youngsoo Shin and
Taekyoon Ahn and
Wonyong Sung and
Kiyoung Choi and
Soonhoi Ha},
editor = {Isao Shirakawa},
title = {An integrated hardware-software cosimulation environment for heterogeneous
systems prototyping},
booktitle = {Proceedings of the 1995 Conference on Asia Pacific Design Automation,
Makuhari, Massa, Chiba, Japan, August 29 - September 1, 1995},
publisher = {{ACM}},
year = {1995},
url = {https://doi.org/10.1145/224818.224848},
doi = {10.1145/224818.224848},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/KimKSASCS95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/KimSKWC95,
author = {Yongjoo Kim and
Youngsoo Shin and
Kyuseok Kim and
Jae{-}Hee Won and
Kiyoung Choi},
title = {Efficient Prototyping System Based on Incremental Design and Module-by-Module
Verification},
booktitle = {1995 {IEEE} International Symposium on Circuits and Systems, {ISCAS}
1995, Seattle, Washington, USA, April 30 - May 3, 1995},
pages = {924--927},
publisher = {{IEEE}},
year = {1995},
url = {https://doi.org/10.1109/ISCAS.1995.519916},
doi = {10.1109/ISCAS.1995.519916},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/KimSKWC95.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/ChoiLK94,
author = {Kiyoung Choi and
KiJong Lee and
Jun{-}Woo Kang},
title = {A Self-Timed Divider Using {RSD} Number System},
booktitle = {Proceedings 1994 {IEEE} International Conference on Computer Design:
{VLSI} in Computer {\&} Processors, {ICCD} '94, Cambridge, MA,
USA, October 10-12, 1994},
pages = {504--507},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/ICCD.1994.331961},
doi = {10.1109/ICCD.1994.331961},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/ChoiLK94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HwangBC88,
author = {Sun Young Hwang and
Tom Blank and
Kiyoung Choi},
title = {Fast functional simulation: an incremental approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {7},
number = {7},
pages = {765--774},
year = {1988},
url = {https://doi.org/10.1109/43.3947},
doi = {10.1109/43.3947},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HwangBC88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChoiHB88,
author = {Kiyoung Choi and
Sun Young Hwang and
Tom Blank},
editor = {Dennis W. Shaklee and
A. Richard Newton},
title = {Incremental-in-time Algorithm for Digital Simulation},
booktitle = {Proceedings of the 25th {ACM/IEEE} Conference on Design Automation,
{DAC} '88, Anaheim, CA, USA, June 12-15, 1988},
pages = {501--505},
publisher = {{ACM}},
year = {1988},
url = {http://portal.acm.org/citation.cfm?id=285730.285811},
timestamp = {Fri, 12 Mar 2021 15:27:48 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChoiHB88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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