BibTeX records: Hyang-Hwa Choi

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@inproceedings{DBLP:conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09,
  author       = {Hyun{-}Woo Lee and
                  Won{-}Joo Yun and
                  Young{-}Kyoung Choi and
                  Hyang{-}Hwa Choi and
                  Jong{-}Jin Lee and
                  Ki{-}Han Kim and
                  Shin{-}Deok Kang and
                  Ji{-}Yeon Yang and
                  Jae{-}Suck Kang and
                  Hyeng{-}Ouk Lee and
                  Dong{-}Uk Lee and
                  Sujeong Sim and
                  Young{-}Ju Kim and
                  Won{-}Jun Choi and
                  Keun{-}Soo Song and
                  Sang{-}Hoon Shin and
                  Hyung{-}Wook Moon and
                  Seung{-}Wook Kwack and
                  Jung{-}Woo Lee and
                  Nak{-}Kyu Park and
                  Kwan{-}Weon Kim and
                  Young{-}Jung Choi and
                  Jin{-}Hong Ahn and
                  Byong{-}Tae Chung},
  title        = {A 1.6V 3.3Gb/s {GDDR3} {DRAM} with dual-mode phase- and delay-locked
                  loop using power-noise management with unregulated power supply in
                  54nm {CMOS}},
  booktitle    = {{IEEE} International Solid-State Circuits Conference, {ISSCC} 2009,
                  Digest of Technical Papers, San Francisco, CA, USA, 8-12 February,
                  2009},
  pages        = {140--141},
  publisher    = {{IEEE}},
  year         = {2009},
  url          = {https://doi.org/10.1109/ISSCC.2009.4977347},
  doi          = {10.1109/ISSCC.2009.4977347},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/LeeYCCLKKYKLLSKCSSMKLPKCAC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08,
  author       = {Won{-}Joo Yun and
                  Hyun{-}Woo Lee and
                  Dongsuk Shin and
                  Shin{-}Deok Kang and
                  Ji{-}Yeon Yang and
                  Hyeng{-}Ouk Lee and
                  Dong{-}Uk Lee and
                  Sujeong Sim and
                  Young{-}Ju Kim and
                  Won{-}Jun Choi and
                  Keun{-}Soo Song and
                  Sang{-}Hoon Shin and
                  Hyang{-}Hwa Choi and
                  Hyung{-}Wook Moon and
                  Seung{-}Wook Kwack and
                  Jung{-}Woo Lee and
                  Young{-}Kyoung Choi and
                  Nak{-}Kyu Park and
                  Kwan{-}Weon Kim and
                  Young{-}Jung Choi and
                  Jin{-}Hong Ahn and
                  Ye Seok Yang},
  title        = {A 0.1-to-1.5GHz 4.2mW All-Digital {DLL} with Dual Duty-Cycle Correction
                  Circuit and Update Gear Circuit for {DRAM} in 66nm {CMOS} Technology},
  booktitle    = {2008 {IEEE} International Solid-State Circuits Conference, {ISSCC}
                  2008, Digest of Technical Papers, San Francisco, CA, USA, February
                  3-7, 2008},
  pages        = {282--283},
  publisher    = {{IEEE}},
  year         = {2008},
  url          = {https://doi.org/10.1109/ISSCC.2008.4523167},
  doi          = {10.1109/ISSCC.2008.4523167},
  timestamp    = {Wed, 16 Oct 2019 14:14:55 +0200},
  biburl       = {https://dblp.org/rec/conf/isscc/YunLSKYLLSKCSSCMKLCPKCAY08.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}