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BibTeX records: Yi-Kuang Chen
@article{DBLP:journals/jnca/LuTCC13, author = {Ta{-}Ping Lu and Amy J. C. Trappey and Yi{-}Kuang Chen and Yu{-}Da Chang}, title = {Collaborative design and analysis of supply chain network management key processes model}, journal = {J. Netw. Comput. Appl.}, volume = {36}, number = {6}, pages = {1503--1511}, year = {2013}, url = {https://doi.org/10.1016/j.jnca.2013.03.015}, doi = {10.1016/J.JNCA.2013.03.015}, timestamp = {Mon, 24 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/jnca/LuTCC13.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/cscwd/LuTCC12, author = {Ta{-}Ping Lu and Amy J. C. Trappey and Yi{-}Kuang Chen and Yu{-}Da Chang}, editor = {Liang Gao and Weiming Shen and Jean{-}Paul A. Barth{\`{e}}s and Junzhou Luo and Jianming Yong and Wenfeng Li and Weidong Li}, title = {Collaborative design of supply chain management key processes in the semiconductor industry}, booktitle = {{IEEE} 16th International Conference on Computer Supported Cooperative Work in Design, {CSCWD} 2012, May 23-25, 2012, Wuhan, China}, pages = {901--906}, publisher = {{IEEE}}, year = {2012}, url = {https://doi.org/10.1109/CSCWD.2012.6221928}, doi = {10.1109/CSCWD.2012.6221928}, timestamp = {Mon, 10 Oct 2022 09:54:55 +0200}, biburl = {https://dblp.org/rec/conf/cscwd/LuTCC12.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/LeeYWCLCH11, author = {Yu{-}Huei Lee and Yao{-}Yi Yang and Shih{-}Jung Wang and Ke{-}Horng Chen and Ying{-}Hsi Lin and Yi{-}Kuang Chen and Chen{-}Chih Huang}, title = {Interleaving Energy-Conservation Mode {(IECM)} Control in Single-Inductor Dual-Output {(SIDO)} Step-Down Converters With 91{\%} Peak Efficiency}, journal = {{IEEE} J. Solid State Circuits}, volume = {46}, number = {4}, pages = {904--915}, year = {2011}, url = {https://doi.org/10.1109/JSSC.2011.2108850}, doi = {10.1109/JSSC.2011.2108850}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/LeeYWCLCH11.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/jssc/LeeYCLWZCHKCH10, author = {Yu{-}Huei Lee and Yao{-}Yi Yang and Ke{-}Horng Chen and Ying{-}Hsi Lin and Shih{-}Jung Wang and Kuo{-}Lin Zheng and Po{-}Fung Chen and Chun{-}Yu Hsieh and Yu{-}Zhou Ke and Yi{-}Kuang Chen and Chen{-}Chih Huang}, title = {A {DVS} Embedded Power Management for High Efficiency Integrated SoC in {UWB} System}, journal = {{IEEE} J. Solid State Circuits}, volume = {45}, number = {11}, pages = {2227--2238}, year = {2010}, url = {https://doi.org/10.1109/JSSC.2010.2063610}, doi = {10.1109/JSSC.2010.2063610}, timestamp = {Sun, 30 Aug 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/jssc/LeeYCLWZCHKCH10.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@inproceedings{DBLP:conf/esscirc/LeeWYZCHHTKCCHL09, author = {Yu{-}Huei Lee and Shih{-}Jung Wang and Yao{-}Yi Yang and Kuo{-}Lin Zheng and Po{-}Fung Chen and Chun{-}Yu Hsieh and Ming{-}Hsin Huang and Yu{-}Nong Tsai and Yu{-}Zhou Ke and Ke{-}Horng Chen and Yi{-}Kuang Chen and Chen{-}Chih Huang and Ying{-}Hsi Lin}, title = {A high efficiency and compact size 65nm power management module with 1.2v low-voltage {PWM} controller for {UWB} system application}, booktitle = {35th European Solid-State Circuits Conference, {ESSCIRC} 2009, Athens, Greece, 14-18 September 2009}, pages = {272--275}, publisher = {{IEEE}}, year = {2009}, url = {https://doi.org/10.1109/ESSCIRC.2009.5326007}, doi = {10.1109/ESSCIRC.2009.5326007}, timestamp = {Mon, 09 Aug 2021 14:54:02 +0200}, biburl = {https://dblp.org/rec/conf/esscirc/LeeWYZCHHTKCCHL09.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cma/ChouSLC07, author = {Shuo{-}Yan Chou and Chun{-}Ying Shen and Shih{-}Wei Lin and Yi{-}Kuang Chen}, title = {{FALSCAL:} {A} fuzzy multidimensional scaling algorithm}, journal = {Comput. Math. Appl.}, volume = {53}, number = {5}, pages = {717--728}, year = {2007}, url = {https://doi.org/10.1016/j.camwa.2006.12.019}, doi = {10.1016/J.CAMWA.2006.12.019}, timestamp = {Thu, 11 Feb 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/cma/ChouSLC07.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/cor/ChenLC02, author = {Yi{-}Kuang Chen and Shih{-}Wei Lin and Shuo{-}Yan Chou}, title = {An efficient two-staged approach for generating block layouts}, journal = {Comput. Oper. Res.}, volume = {29}, number = {5}, pages = {489--504}, year = {2002}, url = {https://doi.org/10.1016/S0305-0548(00)00087-3}, doi = {10.1016/S0305-0548(00)00087-3}, timestamp = {Tue, 18 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/cor/ChenLC02.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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