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ORCIDBibTeX records: Karam S. Chatha
@article{DBLP:journals/esl/PandaC14,
author = {Amrit Panda and
Karam S. Chatha},
title = {An Embedded Architecture for Energy-Efficient Stream Computing},
journal = {{IEEE} Embed. Syst. Lett.},
volume = {6},
number = {3},
pages = {57--60},
year = {2014},
url = {https://doi.org/10.1109/LES.2014.2326895},
doi = {10.1109/LES.2014.2326895},
timestamp = {Thu, 10 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/esl/PandaC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/GinosarC14,
author = {Ran Ginosar and
Karam S. Chatha},
title = {Guest Editors' Introduction - Special Issue on Network-on-Chip},
journal = {{IEEE} Trans. Computers},
volume = {63},
number = {3},
pages = {527--528},
year = {2014},
url = {https://doi.org/10.1109/TC.2014.6},
doi = {10.1109/TC.2014.6},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/GinosarC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/PandaC14,
author = {Amrit Panda and
Karam S. Chatha},
title = {An embedded co-processor architecture for energy-efficient stream
computing},
booktitle = {12th {IEEE} Symposium on Embedded Systems for Real-time Multimedia,
ESTIMedia 2014, Greater Noida, India, October 16-17, 2014},
pages = {60--69},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/ESTIMedia.2014.6962346},
doi = {10.1109/ESTIMEDIA.2014.6962346},
timestamp = {Thu, 17 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/estimedia/PandaC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2014,
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106},
doi = {10.1145/2656106},
isbn = {978-1-4503-3050-3},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/2014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tecs/CheC13,
author = {Weijia Che and
Karam S. Chatha},
title = {Scheduling of synchronous data flow models onto scratchpad memory-based
embedded processors},
journal = {{ACM} Trans. Embed. Comput. Syst.},
volume = {13},
number = {1s},
pages = {30:1--30:25},
year = {2013},
url = {https://doi.org/10.1145/2536747.2536752},
doi = {10.1145/2536747.2536752},
timestamp = {Tue, 08 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tecs/CheC13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LeeCC12,
author = {Haeseung Lee and
Weijia Che and
Karam S. Chatha},
editor = {Ahmed Jerraya and
Luca P. Carloni and
Naehyuck Chang and
Franco Fummi},
title = {Dynamic scheduling of stream programs on embedded multi-core processors},
booktitle = {Proceedings of the 10th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2012, part of ESWeek '12
Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012},
pages = {93--102},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2380445.2380465},
doi = {10.1145/2380445.2380465},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/LeeCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LearyCC12,
author = {Glenn Leary and
Weijia Che and
Karam S. Chatha},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {System-level synthesis of memory architecture for stream processing
sub-systems of a MPSoC},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {672--677},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228481},
doi = {10.1145/2228360.2228481},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LearyCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CheC12,
author = {Weijia Che and
Karam S. Chatha},
editor = {Patrick Groeneveld and
Donatella Sciuto and
Soha Hassoun},
title = {Unrolling and retiming of stream applications onto embedded multicore
processors},
booktitle = {The 49th Annual Design Automation Conference 2012, {DAC} '12, San
Francisco, CA, USA, June 3-7, 2012},
pages = {1272--1277},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2228360.2228598},
doi = {10.1145/2228360.2228598},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CheC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanumaiahVC11,
author = {Vinay Hanumaiah and
Sarma B. K. Vrudhula and
Karam S. Chatha},
title = {Performance Optimal Online {DVFS} and Task Migration Techniques for
Thermally Constrained Multi-Core Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {30},
number = {11},
pages = {1677--1690},
year = {2011},
url = {https://doi.org/10.1109/TCAD.2011.2161308},
doi = {10.1109/TCAD.2011.2161308},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanumaiahVC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CheC11,
author = {Weijia Che and
Karam S. Chatha},
editor = {Leon Stok and
Nikil D. Dutt and
Soha Hassoun},
title = {Compilation of stream programs onto scratchpad memory based embedded
multicore processors through retiming},
booktitle = {Proceedings of the 48th Design Automation Conference, {DAC} 2011,
San Diego, California, USA, June 5-10, 2011},
pages = {122--127},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2024724.2024753},
doi = {10.1145/2024724.2024753},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CheC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/estimedia/CheC11,
author = {Weijia Che and
Karam S. Chatha},
title = {Scheduling of stream programs onto {SPM} enhanced processors with
code overlay},
booktitle = {9th {IEEE} Symposium on Embedded Systems for Real-Time Multimedia,
ESTIMedia 2011, Taipei, Taiwan, October 13-14, 2011},
pages = {9--18},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ESTIMedia.2011.6088530},
doi = {10.1109/ESTIMEDIA.2011.6088530},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/estimedia/CheC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/nocs/2011,
editor = {Radu Marculescu and
Michael Kishinevsky and
Ran Ginosar and
Karam S. Chatha},
title = {{NOCS} 2011, Fifth {ACM/IEEE} International Symposium on Networks-on-Chip,
Pittsburgh, Pennsylvania, USA, May 1-4, 2011},
publisher = {{ACM/IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1145/1999946},
doi = {10.1145/1999946},
isbn = {978-1-4503-0720-8},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/nocs/2011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/asap/CheC10,
author = {Weijia Che and
Karam S. Chatha},
editor = {Fran{\c{c}}ois Charot and
Frank Hannig and
J{\"{u}}rgen Teich and
Christophe Wolinski},
title = {Design of an Automatic Target Recognition algorithm on the {IBM} Cell
Broadband Engine},
booktitle = {21st {IEEE} International Conference on Application-specific Systems
Architectures and Processors, {ASAP} 2010, Rennes, France, 7-9 July
2010},
pages = {21--28},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ASAP.2010.5540770},
doi = {10.1109/ASAP.2010.5540770},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/asap/CheC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LearyC10,
author = {Glenn Leary and
Karam S. Chatha},
editor = {Tony Givargis and
Adam Donlin},
title = {A holistic approach to network-on-chip synthesis},
booktitle = {Proceedings of the 8th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2010, part of ESWeek '10
Sixth Embedded Systems Week, Scottsdale, AZ, USA, October 24-28, 2010},
pages = {213--222},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1878961.1879001},
doi = {10.1145/1878961.1879001},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/LearyC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/BakerPGKC10,
author = {Michael A. Baker and
Amrit Panda and
Nikhil Ghadge and
Aniruddha Kadne and
Karam S. Chatha},
editor = {Tony Givargis and
Adam Donlin},
title = {A performance model and code overlay generator for scratchpad enhanced
embedded processors},
booktitle = {Proceedings of the 8th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2010, part of ESWeek '10
Sixth Embedded Systems Week, Scottsdale, AZ, USA, October 24-28, 2010},
pages = {287--296},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1878961.1879011},
doi = {10.1145/1878961.1879011},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/BakerPGKC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZhangC10,
author = {Sushu Zhang and
Karam S. Chatha},
editor = {Sachin S. Sapatnekar},
title = {Thermal aware task sequencing on embedded processors},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {585--590},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837418},
doi = {10.1145/1837274.1837418},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZhangC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ChePC10,
author = {Weijia Che and
Amrit Panda and
Karam S. Chatha},
editor = {Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller and
Enrico Macii},
title = {Compilation of stream programs for multicore processors that incorporate
scratchpad memories},
booktitle = {Design, Automation and Test in Europe, {DATE} 2010, Dresden, Germany,
March 8-12, 2010},
pages = {1118--1123},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/DATE.2010.5456976},
doi = {10.1109/DATE.2010.5456976},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/ChePC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/CheC10,
author = {Weijia Che and
Karam S. Chatha},
editor = {Louis Scheffer and
Joel R. Phillips and
Alan J. Hu},
title = {Scheduling of synchronous data flow models on scratchpad memory based
embedded processors},
booktitle = {2010 International Conference on Computer-Aided Design, {ICCAD} 2010,
San Jose, CA, USA, November 7-11, 2010},
pages = {205--212},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICCAD.2010.5654150},
doi = {10.1109/ICCAD.2010.5654150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/CheC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BakerC10,
author = {Michael A. Baker and
Karam S. Chatha},
title = {A lightweight run-time scheduler for multitasking multicore stream
applications},
booktitle = {28th International Conference on Computer Design, {ICCD} 2010, 3-6
October 2010, Amsterdam, The Netherlands, Proceedings},
pages = {297--304},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/ICCD.2010.5647732},
doi = {10.1109/ICCD.2010.5647732},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BakerC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/LearyC10,
author = {Glenn Leary and
Karam S. Chatha},
title = {Design of NoC for SoC with Multiple Use Cases Requiring Guaranteed
Performance},
booktitle = {{VLSI} Design 2010: 23rd International Conference on {VLSI} Design,
9th International Conference on Embedded Systems, Bangalore, India,
3-7 January 2010},
pages = {200--205},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/VLSI.Design.2010.73},
doi = {10.1109/VLSI.DESIGN.2010.73},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/LearyC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/cee/MohantyMC09,
author = {Saraju P. Mohanty and
Nasir D. Memon and
Karam S. Chatha},
title = {Circuits and systems for real-time security and copyright protection
of multimedia},
journal = {Comput. Electr. Eng.},
volume = {35},
number = {2},
pages = {231--234},
year = {2009},
url = {https://doi.org/10.1016/j.compeleceng.2008.06.007},
doi = {10.1016/J.COMPELECENG.2008.06.007},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/cee/MohantyMC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LearySMC09,
author = {Glenn Leary and
Krishnan Srinivasan and
Krishna Mehta and
Karam S. Chatha},
title = {Design of Network-on-Chip Architectures With a Genetic Algorithm-Based
Technique},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {17},
number = {5},
pages = {674--687},
year = {2009},
url = {https://doi.org/10.1109/TVLSI.2008.2011205},
doi = {10.1109/TVLSI.2008.2011205},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LearySMC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/BakerDCV09,
author = {Michael A. Baker and
Pravin Dalale and
Karam S. Chatha and
Sarma B. K. Vrudhula},
editor = {Wolfgang Rosenstiel and
Kazutoshi Wakabayashi},
title = {A scalable parallel {H.264} decoder on the cell broadband engine architecture},
booktitle = {Proceedings of the 7th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2009, Grenoble, France,
October 11-16, 2009},
pages = {353--362},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629435.1629484},
doi = {10.1145/1629435.1629484},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/BakerDCV09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LearyC09,
author = {Glenn Leary and
Karam S. Chatha},
editor = {Wolfgang Rosenstiel and
Kazutoshi Wakabayashi},
title = {Automated technique for design of NoC with minimal communication latency},
booktitle = {Proceedings of the 7th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2009, Grenoble, France,
October 11-16, 2009},
pages = {471--480},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629435.1629499},
doi = {10.1145/1629435.1629499},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/LearyC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/HanumaiahRVC09,
author = {Vinay Hanumaiah and
Ravishankar Rao and
Sarma B. K. Vrudhula and
Karam S. Chatha},
title = {Throughput optimal task allocation under thermal constraints for multi-core
processors},
booktitle = {Proceedings of the 46th Design Automation Conference, {DAC} 2009,
San Francisco, CA, USA, July 26-31, 2009},
pages = {776--781},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1629911.1630112},
doi = {10.1145/1629911.1630112},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/HanumaiahRVC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/HanumaiahVC09,
author = {Vinay Hanumaiah and
Sarma B. K. Vrudhula and
Karam S. Chatha},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Performance optimal speed control of multi-core processors under thermal
constraints},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {1548--1551},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090908},
doi = {10.1109/DATE.2009.5090908},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/HanumaiahVC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/HanumaiahVC09,
author = {Vinay Hanumaiah and
Sarma B. K. Vrudhula and
Karam S. Chatha},
editor = {Jaijeet S. Roychowdhury},
title = {Maximizing performance of thermally constrained multi-core processors
by dynamic voltage and frequency control},
booktitle = {2009 International Conference on Computer-Aided Design, {ICCAD} 2009,
San Jose, CA, USA, November 2-5, 2009},
pages = {310--313},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1687399.1687458},
doi = {10.1145/1687399.1687458},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/HanumaiahVC09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZhangCK09,
author = {Sushu Zhang and
Karam S. Chatha and
Goran Konjevod},
editor = {J{\"{o}}rg Henkel and
Ali Keshavarzi and
Naehyuck Chang and
Tahir Ghani},
title = {Near optimal battery-aware energy management},
booktitle = {Proceedings of the 2009 International Symposium on Low Power Electronics
and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009},
pages = {249--254},
publisher = {{ACM}},
year = {2009},
url = {https://doi.org/10.1145/1594233.1594293},
doi = {10.1145/1594233.1594293},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ZhangCK09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChathakSK08,
author = {Karam S. Chatha and
Krishnan Srinivasan and
Goran Konjevod},
title = {Automated Techniques for Synthesis of Application-Specific Network-on-Chip
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {27},
number = {8},
pages = {1425--1438},
year = {2008},
url = {https://doi.org/10.1109/TCAD.2008.925775},
doi = {10.1109/TCAD.2008.925775},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChathakSK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/ZhangC08,
author = {Sushu Zhang and
Karam S. Chatha},
editor = {Chong{-}Min Kyung and
Kiyoung Choi and
Soonhoi Ha},
title = {Automated techniques for energy efficient scheduling on homogeneous
and heterogeneous chip multi-processor architectures},
booktitle = {Proceedings of the 13th Asia South Pacific Design Automation Conference,
{ASP-DAC} 2008, Seoul, Korea, January 21-24, 2008},
pages = {61--66},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ASPDAC.2008.4484026},
doi = {10.1109/ASPDAC.2008.4484026},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/ZhangC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/BakerPCL08,
author = {Michael A. Baker and
Viswesh Parameswaran and
Karam S. Chatha and
Baoxin Li},
editor = {Catherine H. Gebotys and
Grant Martin},
title = {Power reduction via macroblock prioritization for power aware {H.264}
video applications},
booktitle = {Proceedings of the 6th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2008, Atlanta, GA, USA,
October 19-24, 2008},
pages = {261--266},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1450135.1450195},
doi = {10.1145/1450135.1450195},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/BakerPCL08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhangC08,
author = {Sushu Zhang and
Karam S. Chatha},
editor = {Sani R. Nassif and
Jaijeet S. Roychowdhury},
title = {System-level thermal aware design of applications with uncertain execution
time},
booktitle = {2008 International Conference on Computer-Aided Design, {ICCAD} 2008,
San Jose, CA, USA, November 10-13, 2008},
pages = {242--249},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ICCAD.2008.4681581},
doi = {10.1109/ICCAD.2008.4681581},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhangC08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/SrinivasanC07,
author = {Krishnan Srinivasan and
Karam S. Chatha},
title = {Integer linear programming and heuristic techniques for system-level
low power scheduling on multiprocessor architectures under throughput
constraints},
journal = {Integr.},
volume = {40},
number = {3},
pages = {326--354},
year = {2007},
url = {https://doi.org/10.1016/j.vlsi.2006.01.001},
doi = {10.1016/J.VLSI.2006.01.001},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/SrinivasanC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mta/PengCMCR07,
author = {Lina Peng and
K. Sel{\c{c}}uk Candan and
Christopher B. Mayer and
Karam S. Chatha and
Kyung Dong Ryu},
title = {Optimization of media processing workflows with adaptive operator
behaviors},
journal = {Multim. Tools Appl.},
volume = {33},
number = {3},
pages = {245--272},
year = {2007},
url = {https://doi.org/10.1007/s11042-007-0105-z},
doi = {10.1007/S11042-007-0105-Z},
timestamp = {Mon, 11 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mta/PengCMCR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/OstlerCRS07,
author = {Christopher Ostler and
Karam S. Chatha and
Vijay Ramamurthi and
Krishnan Srinivasan},
title = {{ILP} and heuristic techniques for system-level design on network
processor architectures},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {12},
number = {4},
pages = {48},
year = {2007},
url = {https://doi.org/10.1145/1278349.1278361},
doi = {10.1145/1278349.1278361},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/OstlerCRS07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SrinivasanCK07,
author = {Krishnan Srinivasan and
Karam S. Chatha and
Goran Konjevod},
title = {Application Specific Network-on-Chip Design with Guaranteed Quality
Approximation Algorithms},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {184--190},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357983},
doi = {10.1109/ASPDAC.2007.357983},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/SrinivasanCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/OstlerCK07,
author = {Christopher Ostler and
Karam S. Chatha and
Goran Konjevod},
title = {Approximation Algorithm for Process Mapping on Network Processor Architectures},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {577--582},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.358048},
doi = {10.1109/ASPDAC.2007.358048},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/OstlerCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/LearyMC07,
author = {Glenn Leary and
Krishna Mehta and
Karam S. Chatha},
editor = {Soonhoi Ha and
Kiyoung Choi and
Nikil D. Dutt and
J{\"{u}}rgen Teich},
title = {Performance and resource optimization of NoC router architecture for
master and slave {IP} cores},
booktitle = {Proceedings of the 5th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
pages = {155--160},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1289816.1289856},
doi = {10.1145/1289816.1289856},
timestamp = {Sat, 05 Sep 2020 18:08:48 +0200},
biburl = {https://dblp.org/rec/conf/codes/LearyMC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/BakerSC07,
author = {Michael A. Baker and
Aviral Shrivastava and
Karam S. Chatha},
editor = {Soonhoi Ha and
Kiyoung Choi and
Nikil D. Dutt and
J{\"{u}}rgen Teich},
title = {Smart driver for power reduction in next generation bistable electrophoretic
display technology},
booktitle = {Proceedings of the 5th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2007, Salzburg, Austria,
September 30 - October 3, 2007},
pages = {197--202},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1289816.1289865},
doi = {10.1145/1289816.1289865},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/BakerSC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/OstlerC07,
author = {Christopher Ostler and
Karam S. Chatha},
title = {Approximation Algorithm for Data Mapping on Block Multi-threaded Network
Processor Architectures},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {801--804},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278680},
doi = {10.1145/1278480.1278680},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/OstlerC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/OstlerC07,
author = {Christopher Ostler and
Karam S. Chatha},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {An {ILP} formulation for system-level application mapping on network
processor architectures},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {99--104},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://doi.org/10.1109/DATE.2007.364574},
doi = {10.1109/DATE.2007.364574},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/OstlerC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ZhangC07,
author = {Sushu Zhang and
Karam S. Chatha},
editor = {Georges G. E. Gielen},
title = {Approximation algorithm for the temperature-aware scheduling problem},
booktitle = {2007 International Conference on Computer-Aided Design, {ICCAD} 2007,
San Jose, CA, USA, November 5-8, 2007},
pages = {281--288},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ICCAD.2007.4397278},
doi = {10.1109/ICCAD.2007.4397278},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/ZhangC07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ZhangCK07,
author = {Sushu Zhang and
Karam S. Chatha and
Goran Konjevod},
editor = {Diana Marculescu and
Anand Raghunathan and
Ali Keshavarzi and
Vijaykrishnan Narayanan},
title = {Approximation algorithms for power minimization of earliest deadline
first and rate monotonic schedules},
booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics
and Design, 2007, Portland, OR, USA, August 27-29, 2007},
pages = {225--230},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1283780.1283828},
doi = {10.1145/1283780.1283828},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/ZhangCK07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SrinivasanCK06,
author = {Krishnan Srinivasan and
Karam S. Chatha and
Goran Konjevod},
title = {Linear-programming-based techniques for synthesis of network-on-chip
architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {14},
number = {4},
pages = {407--420},
year = {2006},
url = {https://doi.org/10.1109/TVLSI.2006.871762},
doi = {10.1109/TVLSI.2006.871762},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SrinivasanCK06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/civr/PengKCCSCS06,
author = {Lina Peng and
Gisik Kwon and
Yinpeng Chen and
K. Sel{\c{c}}uk Candan and
Hari Sundaram and
Karam S. Chatha and
Maria Luisa Sapino},
editor = {Hari Sundaram and
Milind R. Naphade and
John R. Smith and
Yong Rui},
title = {Modular Design of Media Retrieval Workflows Using {ARIA}},
booktitle = {Image and Video Retrieval, 5th International Conference, {CIVR} 2006,
Tempe, AZ, USA, July 13-15, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4071},
pages = {491--494},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11788034\_51},
doi = {10.1007/11788034\_51},
timestamp = {Sat, 19 Oct 2019 19:59:00 +0200},
biburl = {https://dblp.org/rec/conf/civr/PengKCCSCS06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/SrinivasanC06,
author = {Krishnan Srinivasan and
Karam S. Chatha},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Layout aware design of mesh based NoC architectures},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {136--141},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176288},
doi = {10.1145/1176254.1176288},
timestamp = {Mon, 26 Nov 2018 12:14:45 +0100},
biburl = {https://dblp.org/rec/conf/codes/SrinivasanC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SrinivasanC06,
author = {Krishnan Srinivasan and
Karam S. Chatha},
editor = {Georges G. E. Gielen},
title = {A low complexity heuristic for design of custom network-on-chip architectures},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2006, Munich, Germany, March 6-10, 2006},
pages = {130--135},
publisher = {European Design and Automation Association, Leuven, Belgium},
year = {2006},
url = {https://doi.org/10.1109/DATE.2006.244034},
doi = {10.1109/DATE.2006.244034},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/SrinivasanC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/SrinivasanC06,
author = {Krishnan Srinivasan and
Karam S. Chatha},
title = {A Methodology for Layout Aware Design and Optimization of Custom Network-on-Chip
Architectures},
booktitle = {7th International Symposium on Quality of Electronic Design {(ISQED}
2006), 27-29 March 2006, San Jose, CA, {USA}},
pages = {352--357},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/ISQED.2006.13},
doi = {10.1109/ISQED.2006.13},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/SrinivasanC06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/VellankiBC05,
author = {Praveen Vellanki and
Nilanjan Banerjee and
Karam S. Chatha},
title = {Quality-of-service and error control techniques for mesh-based network-on-chip
architectures},
journal = {Integr.},
volume = {38},
number = {3},
pages = {353--382},
year = {2005},
url = {https://doi.org/10.1016/j.vlsi.2004.07.009},
doi = {10.1016/J.VLSI.2004.07.009},
timestamp = {Thu, 20 Feb 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/VellankiBC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/SrinivasanC05,
author = {Krishnan Srinivasan and
Karam S. Chatha},
editor = {Tingao Tang},
title = {{SAGA:} synthesis technique for guaranteed throughput NoC architectures},
booktitle = {Proceedings of the 2005 Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2005, Shanghai, China, January 18-21, 2005},
pages = {489--494},
publisher = {{ACM} Press},
year = {2005},
url = {https://doi.org/10.1145/1120725.1120919},
doi = {10.1145/1120725.1120919},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/SrinivasanC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/SrinivasanCK05,
author = {Krishnan Srinivasan and
Karam S. Chatha and
Goran Konjevod},
title = {An automated technique for topology and route generation of application
specific on-chip interconnection networks},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {231--237},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560070},
doi = {10.1109/ICCAD.2005.1560070},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/SrinivasanCK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SrinivasanC05,
author = {Krishnan Srinivasan and
Karam S. Chatha},
editor = {Kaushik Roy and
Vivek Tiwari},
title = {A technique for low energy mapping and routing in network-on-chip
architectures},
booktitle = {Proceedings of the 2005 International Symposium on Low Power Electronics
and Design, 2005, San Diego, California, USA, August 8-10, 2005},
pages = {387--392},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1077603.1077695},
doi = {10.1145/1077603.1077695},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/SrinivasanC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RamamurthiMOC05,
author = {Vijaykumar Ramamurthi and
Jason McCollum and
Christopher Ostler and
Karam S. Chatha},
title = {System Level Methodology for Programming {CMP} Based Multi-Threaded
Network Processor Architectures},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {110--116},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.71},
doi = {10.1109/ISVLSI.2005.71},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RamamurthiMOC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mm/PengKCRCSC05,
author = {Lina Peng and
Gisik Kwon and
K. Sel{\c{c}}uk Candan and
Kyung Dong Ryu and
Karam S. Chatha and
Hari Sundaram and
Yinpeng Chen},
editor = {HongJiang Zhang and
Tat{-}Seng Chua and
Ralf Steinmetz and
Mohan S. Kankanhalli and
Lynn Wilcox},
title = {Media processing workflow design and execution with {ARIA}},
booktitle = {Proceedings of the 13th {ACM} International Conference on Multimedia,
Singapore, November 6-11, 2005},
pages = {800--801},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1101149.1101322},
doi = {10.1145/1101149.1101322},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mm/PengKCRCSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/RanganC05,
author = {Nagendran Rangan and
Karam S. Chatha},
title = {A Technique for Throughput and Register Optimization during Resource
Constrained Pipelined Scheduling},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {564--569},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.35},
doi = {10.1109/ICVD.2005.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/RanganC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanC05,
author = {Krishnan Srinivasan and
Karam S. Chatha},
title = {{ISIS:} {A} Genetic Algorithm Based Technique for Custom On-Chip Interconnection
Network Synthesis},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {623--628},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.113},
doi = {10.1109/ICVD.2005.113},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/BanerjeeVC04,
author = {Nilanjan Banerjee and
Praveen Vellanki and
Karam S. Chatha},
title = {A Power and Performance Model for Network-on-Chip Architectures},
booktitle = {2004 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2004), 16-20 February 2004, Paris, France},
pages = {1250--1255},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/DATE.2004.1269067},
doi = {10.1109/DATE.2004.1269067},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/BanerjeeVC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/VellankiBC04,
author = {Praveen Vellanki and
Nilanjan Banerjee and
Karam S. Chatha},
editor = {David Garrett and
John C. Lach and
Charles A. Zukowski},
title = {Quality-of-service and error control techniques for network-on-chip
architectures},
booktitle = {Proceedings of the 14th {ACM} Great Lakes Symposium on {VLSI} 2004,
Boston, MA, USA, April 26-28, 2004},
pages = {45--50},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/988952.988964},
doi = {10.1145/988952.988964},
timestamp = {Fri, 20 Aug 2021 16:30:37 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/VellankiBC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/SrinivasanCK04,
author = {Krishnan Srinivasan and
Karam S. Chatha and
Goran Konjevod},
title = {Linear Programming based Techniques for Synthesis of Network-on-Chip
Architectures},
booktitle = {22nd {IEEE} International Conference on Computer Design: {VLSI} in
Computers {\&} Processors {(ICCD} 2004), 11-13 October 2004, San
Jose, CA, USA, Proceedings},
pages = {422--429},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICCD.2004.1347957},
doi = {10.1109/ICCD.2004.1347957},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/SrinivasanCK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SrinivasanTRC04,
author = {Krishnan Srinivasan and
Nagender Telkar and
Vijay Ramamurthi and
Karam S. Chatha},
title = {System-Level Design Techniques for Throughput and Power Optimization
of Multiprocessor SoC Architectures},
booktitle = {2004 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2004), Emerging Trends in {VLSI} Systems Design, 19-20 February 2004,
Lafayette, LA, {USA}},
pages = {39--45},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISVLSI.2004.1339506},
doi = {10.1109/ISVLSI.2004.1339506},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SrinivasanTRC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SrinivasanRC04,
author = {Krishnan Srinivasan and
Vijay Ramamurthi and
Karam S. Chatha},
title = {A Technique for Energy versus Quality of Service Trade-Off for {MPEG-2}
Decoder},
booktitle = {2004 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2004), Emerging Trends in {VLSI} Systems Design, 19-20 February 2004,
Lafayette, LA, {USA}},
pages = {313--316},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ISVLSI.2004.1339569},
doi = {10.1109/ISVLSI.2004.1339569},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SrinivasanRC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mis/CandanPRCM04,
author = {K. Sel{\c{c}}uk Candan and
Lina Peng and
Kyung Dong Ryu and
Karam S. Chatha and
Christopher B. Mayer},
editor = {Maria Luisa Sapino and
Prashant J. Shenoy},
title = {Efficient Stream Routing in Quality- and Resource-Adaptive Flow Architectures},
booktitle = {{MIS} 2004, 10th International Workshop on Multimedia Information
Systems, August 25-27, 2004, University of Maryland, College Park,
MD, USA, Position Papers},
pages = {30--39},
year = {2004},
timestamp = {Tue, 22 May 2007 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mis/CandanPRCM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mm/PengCRCS04,
author = {Lina Peng and
K. Sel{\c{c}}uk Candan and
Kyung Dong Ryu and
Karam S. Chatha and
Hari Sundaram},
editor = {Henning Schulzrinne and
Nevenka Dimitrova and
Martina Angela Sasse and
Sue B. Moon and
Rainer Lienhart},
title = {{ARIA:} an adaptive and programmable media-flow architecture for interactive
arts},
booktitle = {Proceedings of the 12th {ACM} International Conference on Multimedia,
New York, NY, USA, October 10-16, 2004},
pages = {532--535},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1027527.1027657},
doi = {10.1145/1027527.1027657},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mm/PengCRCS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/SrinivasanC04,
author = {Krishnan Srinivasan and
Karam S. Chatha},
title = {An {ILP} Formulation for System Level Throughput and Power Optimization
in Multiprocessor SoC Architectures},
booktitle = {17th International Conference on {VLSI} Design {(VLSI} Design 2004),
with the 3rd International Conference on Embedded Systems Design,
5-9 January 2004, Mumbai, India},
pages = {255--260},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICVD.2004.1260933},
doi = {10.1109/ICVD.2004.1260933},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/SrinivasanC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChathaV02,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {Hardware-software partitioning and pipelined scheduling of transformative
applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {10},
number = {3},
pages = {193--208},
year = {2002},
url = {https://doi.org/10.1109/TVLSI.2002.1043323},
doi = {10.1109/TVLSI.2002.1043323},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChathaV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ChathaV01,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Jan Madsen and
J{\"{o}}rg Henkel and
Xiaobo Sharon Hu},
title = {{MAGELLAN:} multiway hardware-software partitioning and scheduling
for latency minimization of hierarchical control-dataflow task graphs},
booktitle = {Proceedings of the Ninth International Symposium on Hardware/Software
Codesign, {CODES} 2001, Copenhagen, Denmark, 2001},
pages = {42--47},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/371636.371671},
doi = {10.1145/371636.371671},
timestamp = {Mon, 09 Aug 2021 14:54:01 +0200},
biburl = {https://dblp.org/rec/conf/codes/ChathaV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/ChathaV00,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {An Iterative Algorithm for Hardware-Software Partitioning, Hardware
Design Space Exploration and Scheduling},
journal = {Des. Autom. Embed. Syst.},
volume = {5},
number = {3-4},
pages = {281--293},
year = {2000},
url = {https://doi.org/10.1023/A:1008954218909},
doi = {10.1023/A:1008954218909},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dafes/ChathaV00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpl/ChathaV99,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Patrick Lysaght and
James Irvine and
Reiner W. Hartenstein},
title = {Hardware-Software Codesign for Dynamically Reconfigurable Architectures},
booktitle = {Field-Programmable Logic and Applications, 9th International Workshop,
FPL'99, Glasgow, UK, August 30 - September 1, 1999, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {1673},
pages = {175--184},
publisher = {Springer},
year = {1999},
url = {https://doi.org/10.1007/978-3-540-48302-1\_18},
doi = {10.1007/978-3-540-48302-1\_18},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpl/ChathaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ChathaV99,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {An Iterative Algorithm for Partitioning and Scheduling of Area Constrained
{HW-SW} Systems},
booktitle = {Proceedings of the Tenth {IEEE} International Workshop on Rapid System
Prototyping {(RSP} 1999), Clearwater, Florida, USA, June 16-18, 1999},
pages = {134--139},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/IWRSP.1999.779043},
doi = {10.1109/IWRSP.1999.779043},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/ChathaV99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Gaetano Borriello and
Ahmed Amine Jerraya and
Luciano Lavagno},
title = {{RECOD:} a retiming heuristic to optimize resource and memory utilization
in {HW/SW} codesigns},
booktitle = {Proceedings of the Sixth International Workshop on Hardware/Software
Codesign, {CODES} 1998, Seattle, Washington, USA, March 15-18, 1998},
pages = {139--143},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1145/278241.278324},
doi = {10.1145/278241.278324},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/codes/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isss/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
editor = {Francky Catthoor},
title = {A Tool for Partitioning and Pipelined Scheduling of Hardware-Software
Systems},
booktitle = {Proceedings of the 11th International Symposium on System Synthesis,
{ISSS} '98, Hsinchu, Taiwan, December 2-4, 1998},
pages = {145--151},
publisher = {{ACM} / {IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/ISSS.1998.730616},
doi = {10.1109/ISSS.1998.730616},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isss/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rsp/ChathaV98,
author = {Karam S. Chatha and
Ranga Vemuri},
title = {Performance Evaluation Tool for Rapid Prototyping of Hardware-Software
Codesigns},
booktitle = {Proceedings of the Ninth {IEEE} International Workshop on Rapid System
Prototyping {(RSP} 1998), Leuven, Belgium, June 3-5, 1998},
pages = {218--224},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/IWRSP.1998.676695},
doi = {10.1109/IWRSP.1998.676695},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/rsp/ChathaV98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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