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ORCIDBibTeX records: Paulo F. Butzen
@article{DBLP:journals/et/BalenGORSSAMAGMB23,
author = {Tiago R. Balen and
Carlos J. Gonz{\'{a}}lez and
Ingrid F. V. Oliveira and
Leomar S. da Rosa Jr. and
Rafael Iankowski Soares and
Rafael B. Schvittz and
Nemitala Added and
Eduardo L. A. Macchione and
Vitor A. P. Aguiar and
Marcilei Aparecida Guazzelli and
Nilberto H. Medina and
Paulo F. Butzen},
title = {Evaluating the Reliability of Different Voting Schemes for Fault Tolerant
Approximate Systems},
journal = {J. Electron. Test.},
volume = {39},
number = {4},
pages = {409--420},
year = {2023},
url = {https://doi.org/10.1007/s10836-023-06072-9},
doi = {10.1007/S10836-023-06072-9},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/BalenGORSSAMAGMB23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PeraltaNBKR23,
author = {Renato D. Peralta and
Joao P. Nespolo and
Paulo F. Butzen and
Mariana Kolberg and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {An Improved method to join BDDs for incompletely specified Boolean
functions},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2023,
Monterey, CA, USA, May 21-25, 2023},
pages = {1--5},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISCAS46773.2023.10181893},
doi = {10.1109/ISCAS46773.2023.10181893},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/PeraltaNBKR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AmmesBRR23,
author = {Gabriel Ammes and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Evaluation of Digital Circuit Design by Combining Two - and Multi-Level
Approximate Logic Synthesis},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2023, Foz
do Iguacu, Brazil, June 20-23, 2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/ISVLSI59464.2023.10238642},
doi = {10.1109/ISVLSI59464.2023.10238642},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AmmesBRR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/AmmesMBRR23,
author = {Gabriel Ammes and
Guilherme B. Manske and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {{ATMR} design by construction based on two-level {ALS}},
booktitle = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,
2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SBCCI60457.2023.10261973},
doi = {10.1109/SBCCI60457.2023.10261973},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/AmmesMBRR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/MarquesBWZBBM23,
author = {Cleiton Magano Marques and
Leonardo Heitich Brendler and
Fr{\'{e}}d{\'{e}}ric Wrobel and
Alexandra L. Zimpeck and
Walter E. Calienes Bartra and
Paulo F. Butzen and
Cristina Meinhardt},
title = {A Detailed Electrical Analysis of {SEE} on 28 nm {FDSOI} {SRAM} Architectures},
booktitle = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,
2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SBCCI60457.2023.10261665},
doi = {10.1109/SBCCI60457.2023.10261665},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/MarquesBWZBBM23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/NespoloPBR23,
author = {Joao P. Nespolo and
Renato D. Peralta and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Effect of Unique Table Implementation in the Performance of {BDD}
Packages},
booktitle = {36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2023, Rio de Janeiro, Brazil, August 28 - Sept. 1,
2023},
pages = {1--6},
publisher = {{IEEE}},
year = {2023},
url = {https://doi.org/10.1109/SBCCI60457.2023.10261960},
doi = {10.1109/SBCCI60457.2023.10261960},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/NespoloPBR23.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/esticas/DiasMBB22,
author = {Cesar de S. Dias and
Felipe S. Marranghello and
Raphael Martins Brum and
Paulo F. Butzen},
title = {A Predictive Approach for Conditional Execution of Memristive Material
Implication Stateful Logic Operations},
journal = {{IEEE} J. Emerg. Sel. Topics Circuits Syst.},
volume = {12},
number = {4},
pages = {878--887},
year = {2022},
url = {https://doi.org/10.1109/JETCAS.2022.3221053},
doi = {10.1109/JETCAS.2022.3221053},
timestamp = {Sun, 15 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/esticas/DiasMBB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/BerndtMRB22,
author = {Augusto Andre Souza Berndt and
Cristina Meinhardt and
Andr{\'{e}} In{\'{a}}cio Reis and
Paulo F. Butzen},
title = {Optimizing machine learning logic circuits with constant signal propagation},
journal = {Integr.},
volume = {87},
pages = {293--305},
year = {2022},
url = {https://doi.org/10.1016/j.vlsi.2022.08.004},
doi = {10.1016/J.VLSI.2022.08.004},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/integration/BerndtMRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmmesNBGR22,
author = {Gabriel Ammes and
Walter Lau Neto and
Paulo F. Butzen and
Pierre{-}Emmanuel Gaillardon and
Renato P. Ribas},
title = {A Two-Level Approximate Logic Synthesis Combining Cube Insertion and
Removal},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {41},
number = {11},
pages = {5126--5130},
year = {2022},
url = {https://doi.org/10.1109/TCAD.2022.3143489},
doi = {10.1109/TCAD.2022.3143489},
timestamp = {Sun, 13 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/AmmesNBGR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/OliveiraPSRBS22,
author = {Ingrid F. V. Oliveira and
Matheus F. Pontes and
Rafael B. Schvittz and
Leomar S. da Rosa Jr. and
Paulo F. Butzen and
Rafael Iankowski Soares},
title = {Fault Tolerance Evaluation of Different Majority Voter Designs},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {185--189},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9938002},
doi = {10.1109/ISCAS48785.2022.9938002},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/OliveiraPSRBS22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/PontesOSRB22,
author = {Matheus F. Pontes and
Ingrid F. V. Oliveira and
Rafael B. Schvittz and
Leomar Soares da Rosa Jr. and
Paulo F. Butzen},
title = {The Impact of Logic Gates Susceptibility in Overall Circuit Reliability
Analysis},
booktitle = {{IEEE} International Symposium on Circuits and Systems, {ISCAS} 2022,
Austin, TX, USA, May 27 - June 1, 2022},
pages = {1610--1614},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISCAS48785.2022.9937573},
doi = {10.1109/ISCAS48785.2022.9937573},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iscas/PontesOSRB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/BrandaoNPBR22,
author = {Eduarde D. Brand{\~{a}}o and
Joao P. Nespolo and
Renato D. Peralta and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis},
title = {Possible Reductions to Generate circuits from BDDs},
booktitle = {{IEEE} Computer Society Annual Symposium on VLSI, {ISVLSI} 2022, Nicosia,
Cyprus, July 4-6, 2022},
pages = {406--409},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/ISVLSI54635.2022.00091},
doi = {10.1109/ISVLSI54635.2022.00091},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/BrandaoNPBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/ManskeFBR22,
author = {Guilherme B. Manske and
Clayton R. Farias and
Paulo F. Butzen and
Leomar S. da Rosa},
title = {A Fast Approximate Function Generation Method to {ATMR} Architecture},
booktitle = {13th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2022, Puerto Varas, Chile, March 1-4, 2022},
pages = {1--4},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LASCAS53948.2022.9789047},
doi = {10.1109/LASCAS53948.2022.9789047},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lascas/ManskeFBR22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/FariasSBB22,
author = {Clayton R. Farias and
Rafael B. Schvittz and
Tiago R. Balen and
Paulo F. Butzen},
title = {Evaluating Soft Error Reliability of Combinational Circuits Using
a Monte Carlo Based Method},
booktitle = {23rd {IEEE} Latin American Test Symposium, {LATS} 2022, Montevideo,
Uruguay, September 5-8, 2022},
pages = {1--6},
publisher = {{IEEE}},
year = {2022},
url = {https://doi.org/10.1109/LATS57337.2022.9936911},
doi = {10.1109/LATS57337.2022.9936911},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latw/FariasSBB22.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/MarquesMB21,
author = {Cleiton Magano Marques and
Cristina Meinhardt and
Paulo Francisco Butzen},
title = {Soft Errors Sensitivity of {SRAM} Cells in Hold, Write, Read and Half-Selected
Conditions},
journal = {J. Electron. Test.},
volume = {37},
number = {2},
pages = {263--270},
year = {2021},
url = {https://doi.org/10.1007/s10836-021-05944-2},
doi = {10.1007/S10836-021-05944-2},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/MarquesMB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/RaiNMZYYFMPRABC21,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
booktitle = {Design, Automation {\&} Test in Europe Conference {\&} Exhibition,
{DATE} 2021, Grenoble, France, February 1-5, 2021},
pages = {1026--1031},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.23919/DATE51398.2021.9473972},
doi = {10.23919/DATE51398.2021.9473972},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/RaiNMZYYFMPRABC21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/HangMBM21,
author = {Maria Eduarda de Melo Hang and
Cleiton Magano Marques and
Paulo F. Butzen and
Cristina Meinhardt},
title = {Soft Error Sensibility Window at FinFET {DICE} {SRAM}},
booktitle = {12th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2021, Arequipa, Peru, February 21-24, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/LASCAS51355.2021.9459173},
doi = {10.1109/LASCAS51355.2021.9459173},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lascas/HangMBM21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/OliveiraDB021,
author = {Isadora Oliveira and
Marcelo Danigno and
Paulo F. Butzen and
Ricardo Reis},
title = {Benchmarking Open Access {VLSI} Partitioning Tools},
booktitle = {12th {IEEE} Latin America Symposium on Circuits and System, {LASCAS}
2021, Arequipa, Peru, February 21-24, 2021},
pages = {1--4},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/LASCAS51355.2021.9459131},
doi = {10.1109/LASCAS51355.2021.9459131},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/lascas/OliveiraDB021.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/BalenGOSAMAGMB21,
author = {Tiago R. Balen and
Carlos J. Gonz{\'{a}}lez and
Ingrid F. V. Oliveira and
Rafael B. Schvittz and
Nemitala Added and
Eduardo L. A. Macchione and
Vitor A. P. de Aguiar and
Marcilei Aparecida Guazzelli and
Nilberto H. Medina and
Paulo F. Butzen},
title = {Reliability Evaluation of Voters for Fault Tolerant Approximate Systems},
booktitle = {22nd {IEEE} Latin American Test Symposium, {LATS} 2021, Punta del
Este, Uruguay, October 27-29, 2021},
pages = {1--6},
publisher = {{IEEE}},
year = {2021},
url = {https://doi.org/10.1109/LATS53581.2021.9651736},
doi = {10.1109/LATS53581.2021.9651736},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/latw/BalenGOSAMAGMB21.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2112-00621,
author = {Gabriel Ammes and
Walter Lau Neto and
Paulo F. Butzen and
Pierre{-}Emmanuel Gaillardon and
Renato P. Ribas},
title = {A Two-Level Approximate Logic Synthesis Combining Cube Insertion and
Removal},
journal = {CoRR},
volume = {abs/2112.00621},
year = {2021},
url = {https://arxiv.org/abs/2112.00621},
eprinttype = {arXiv},
eprint = {2112.00621},
timestamp = {Tue, 07 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/corr/abs-2112-00621.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/FogacaMDOB020,
author = {Mateus Foga{\c{c}}a and
Eder Monteiro and
Marcelo Danigno and
Isadora Oliveira and
Paulo F. Butzen and
Ricardo Reis},
title = {Contributions to OpenROAD from Abroad: Experiences and Learnings :
Invited Paper},
booktitle = {{IEEE/ACM} International Conference On Computer Aided Design, {ICCAD}
2020, San Diego, CA, USA, November 2-5, 2020},
pages = {113:1--113:8},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1145/3400302.3415737},
doi = {10.1145/3400302.3415737},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/FogacaMDOB020.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SchvittzBR20,
author = {Rafael B. Schvittz and
Paulo F. Butzen and
Leomar S. da Rosa},
title = {Methods for Susceptibility Analysis of Logic Gates in the Presence
of Single Event Transients},
booktitle = {{IEEE} International Test Conference, {ITC} 2020, Washington, DC,
USA, November 1-6, 2020},
pages = {1--9},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/ITC44778.2020.9325252},
doi = {10.1109/ITC44778.2020.9325252},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/itc/SchvittzBR20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/MarquesMB20,
author = {Cleiton Magano Marques and
Cristina Meinhardt and
Paulo F. Butzen},
title = {Soft Error Reliability of {SRAM} cells during the three operation
states},
booktitle = {{IEEE} Latin-American Test Symposium, {LATS} 2020, Maceio, Brazil,
March 30 - April 2, 2020},
pages = {1--6},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.1109/LATS49555.2020.9093684},
doi = {10.1109/LATS49555.2020.9093684},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/MarquesMB20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/corr/abs-2012-02530,
author = {Shubham Rai and
Walter Lau Neto and
Yukio Miyasaka and
Xinpei Zhang and
Mingfei Yu and
Qingyang Yi and
Masahiro Fujita and
Guilherme B. Manske and
Matheus F. Pontes and
Leomar S. da Rosa Jr. and
Marilton S. de Aguiar and
Paulo F. Butzen and
Po{-}Chun Chien and
Yu{-}Shan Huang and
Hoa{-}Ren Wang and
Jie{-}Hong R. Jiang and
Jiaqi Gu and
Zheng Zhao and
Zixuan Jiang and
David Z. Pan and
Brunno A. Abreu and
Isac de Souza Campos and
Augusto Andre Souza Berndt and
Cristina Meinhardt and
J{\^{o}}nata Tyska Carvalho and
Mateus Grellert and
Sergio Bampi and
Aditya Lohana and
Akash Kumar and
Wei Zeng and
Azadeh Davoodi and
Rasit Onur Topaloglu and
Yuan Zhou and
Jordan Dotzel and
Yichi Zhang and
Hanyu Wang and
Zhiru Zhang and
Valerio Tenace and
Pierre{-}Emmanuel Gaillardon and
Alan Mishchenko and
Satrajit Chatterjee},
title = {Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization},
journal = {CoRR},
volume = {abs/2012.02530},
year = {2020},
url = {https://arxiv.org/abs/2012.02530},
eprinttype = {arXiv},
eprint = {2012.02530},
timestamp = {Thu, 24 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/corr/abs-2012-02530.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/FerreiraBMR19,
author = {Jorge Ferreira and
Paulo F. Butzen and
Cristina Meinhardt and
Ricardo A. L. Reis},
title = {{FBM:} {A} Simple and Fast Algorithm for Placement Legalization},
booktitle = {26th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2019, Genoa, Italy, November 27-29, 2019},
pages = {209--212},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICECS46596.2019.8965013},
doi = {10.1109/ICECS46596.2019.8965013},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/FerreiraBMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/DanignoBFOMFR19,
author = {Marcelo Danigno and
Paulo F. Butzen and
Jorge Ferreira and
Andr{\'{e}} Oliveira and
Eder Monteiro and
Mateus Foga{\c{c}}a and
Ricardo Augusto da Luz Reis},
title = {Proposal and Evaluation of Pin Access Algorithms for Detailed Routing},
booktitle = {26th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2019, Genoa, Italy, November 27-29, 2019},
pages = {602--605},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/ICECS46596.2019.8965194},
doi = {10.1109/ICECS46596.2019.8965194},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/DanignoBFOMFR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/BerndtMBR19,
author = {Augusto Andre Souza Berndt and
Alan Mishchenko and
Paulo Francisco Butzen and
Andr{\'{e}} In{\'{a}}cio Reis},
editor = {Jo{\~{a}}o Antonio Martino and
Marcelo Lubaszewski and
Matteo Sonza Reorda},
title = {Reduction of neural network circuits by constant and nearly constant
signal propagation},
booktitle = {Proceedings of the 32nd Symposium on Integrated Circuits and Systems
Design, {SBCCI} 2019, Sao Paulo, Brazil, August 26-30, 2019},
pages = {29},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3338852.3339874},
doi = {10.1145/3338852.3339874},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/BerndtMBR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzFRB19,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar S. da Rosa and
Paulo F. Butzen},
editor = {Carolina Metzler and
Pierre{-}Emmanuel Gaillardon and
Giovanni De Micheli and
Carlos Silva C{\'{a}}rdenas and
Ricardo Reis},
title = {An Improved Technique for Logic Gate Susceptibility Evaluation of
Single Event Transient Faults},
booktitle = {VLSI-SoC: New Technology Enabler - 27th {IFIP} {WG} 10.5/IEEE International
Conference on Very Large Scale Integration, VLSI-SoC 2019, Cusco,
Peru, October 6-9, 2019, Revised and Extended Selected Papers},
series = {{IFIP} Advances in Information and Communication Technology},
volume = {586},
pages = {69--88},
publisher = {Springer},
year = {2019},
url = {https://doi.org/10.1007/978-3-030-53273-4\_4},
doi = {10.1007/978-3-030-53273-4\_4},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzFRB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzFSB19,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar Soares and
Paulo Francisco Butzen},
title = {A Simplified Layout-Level method for Single Event Transient Faults
Susceptibility on Logic Gates},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {185--190},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920333},
doi = {10.1109/VLSI-SOC.2019.8920333},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzFSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchvittzSB19,
author = {Rafael B. Schvittz and
Leomar Soares and
Paulo Francisco Butzen},
title = {Exploring Logic Gates Layout to Improve the Accuracy of Circuit Reliability
Estimation},
booktitle = {27th {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2019, Cuzco, Peru, October 6-9, 2019},
pages = {234--235},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.1109/VLSI-SoC.2019.8920385},
doi = {10.1109/VLSI-SOC.2019.8920385},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SchvittzSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/AlmeidaMBSRM18,
author = {Roberto B. Almeida and
Cleiton Magano Marques and
Paulo F. Butzen and
F{\'{a}}bio G. R. G. da Silva and
Ricardo A. L. Reis and
Cristina Meinhardt},
title = {Analysis of 6{\unicode{8239}}T {SRAM} cell in sub-45{\unicode{8239}}nm
{CMOS} and FinFET technologies},
journal = {Microelectron. Reliab.},
volume = {88-90},
pages = {196--202},
year = {2018},
url = {https://doi.org/10.1016/j.microrel.2018.07.134},
doi = {10.1016/J.MICROREL.2018.07.134},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/AlmeidaMBSRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SchvittzFRB18,
author = {Rafael B. Schvittz and
Denis Teixeira Franco and
Leomar S. da Rosa Jr. and
Paulo F. Butzen},
title = {Probabilistic Method for Reliability Estimation of {SP-} Networks
considering Single Event Transient Faults},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {357--360},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617918},
doi = {10.1109/ICECS.2018.8617918},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SchvittzFRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/PontesBSRF18,
author = {Matheus F. Pontes and
Paulo F. Butzen and
Rafael B. Schvittz and
Leomar S. da Rosa Jr. and
Denis Teixeira Franco},
title = {The Suitability of the {SPR-MP} Method to Evaluate the Reliability
of Logic Circuits},
booktitle = {25th {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2018, Bordeaux, France, December 9-12, 2018},
pages = {433--436},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/ICECS.2018.8617852},
doi = {10.1109/ICECS.2018.8617852},
timestamp = {Thu, 05 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/PontesBSRF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/lascas/SchvittzPMFNRB18,
author = {Rafael B. Schvittz and
Matheus F. Pontes and
Cristina Meinhardt and
Denis Teixeira Franco and
Lirida A. B. Naviner and
Leomar S. da Rosa and
Paulo F. Butzen},
title = {Reliability evaluation of circuits designed in multi- and single-stage
versions},
booktitle = {9th {IEEE} Latin American Symposium on Circuits {\&} Systems,
{LASCAS} 2018, Puerto Vallarta, Mexico, February 25-28, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/LASCAS.2018.8399927},
doi = {10.1109/LASCAS.2018.8399927},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/lascas/SchvittzPMFNRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/OliveiraSB18,
author = {Ingrid F. V. Oliveira and
Rafael B. Schvittz and
Paulo F. Butzen},
title = {Fault masking ratio analysis of majority voters topologies},
booktitle = {19th {IEEE} Latin-American Test Symposium, {LATS} 2018, Sao Paulo,
Brazil, March 12-14, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/LATW.2018.8349664},
doi = {10.1109/LATW.2018.8349664},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/OliveiraSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/AlmeidaBM18,
author = {Roberto B. Almeida and
Paulo F. Butzen and
Cristina Meinhardt},
title = {16NM 6T and 8T {CMOS} {SRAM} Cell Robustness Against Process Variability
and Aging Effects},
booktitle = {31st Symposium on Integrated Circuits and Systems Design, {SBCCI}
2018, Bento Gon{\c{c}}alves, RS, Brazil, August 27-31, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SBCCI.2018.8533253},
doi = {10.1109/SBCCI.2018.8533253},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/AlmeidaBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/DiasB18,
author = {Cesar de S. Dias and
Paulo F. Butzen},
title = {A Novel {SPICE} Model of Memristive Devices with Threshold Current
Based Control},
booktitle = {31st Symposium on Integrated Circuits and Systems Design, {SBCCI}
2018, Bento Gon{\c{c}}alves, RS, Brazil, August 27-31, 2018},
pages = {1--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/SBCCI.2018.8533256},
doi = {10.1109/SBCCI.2018.8533256},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/DiasB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/PortoBF17,
author = {Gabriel S. Porto and
Paulo F. Butzen and
Denis Teixeira Franco},
title = {Exploring BDDs to reduce test pattern set},
booktitle = {18th {IEEE} Latin American Test Symposium, {LATS} 2017, Bogot{\'{a}},
Colombia, March 13-15, 2017},
pages = {1--4},
publisher = {{IEEE}},
year = {2017},
url = {https://doi.org/10.1109/LATW.2017.7906743},
doi = {10.1109/LATW.2017.7906743},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/PortoBF17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/SlimaniBNWC16,
author = {Mariem Slimani and
Paulo F. Butzen and
Lirida A. B. Naviner and
Y. Wang and
Hao Cai},
title = {Reliability analysis of hybrid spin transfer torque magnetic tunnel
junction/CMOS majority voters},
journal = {Microelectron. Reliab.},
volume = {64},
pages = {48--53},
year = {2016},
url = {https://doi.org/10.1016/j.microrel.2016.07.074},
doi = {10.1016/J.MICROREL.2016.07.074},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/SlimaniBNWC16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SilvaBM16,
author = {F{\'{a}}bio G. R. G. da Silva and
Paulo F. Butzen and
Cristina Meinhardt},
title = {{PVT} variability analysis of FinFET and {CMOS} {XOR} circuits at
16nm},
booktitle = {2016 {IEEE} International Conference on Electronics, Circuits and
Systems, {ICECS} 2016, Monte Carlo, Monaco, December 11-14, 2016},
pages = {528--531},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/ICECS.2016.7841255},
doi = {10.1109/ICECS.2016.7841255},
timestamp = {Wed, 05 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SilvaBM16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/SchivittzFMB16,
author = {Rafael B. Schivittz and
Denis Teixeira Franco and
Cristina Meinhardt and
Paulo F. Butzen},
title = {A probabilistic model for stuck-on faults in combinational logic gates},
booktitle = {17th Latin-American Test Symposium, {LATS} 2016, Foz do Iguacu, Brazil,
April 6-8, 2016},
pages = {39--44},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/LATW.2016.7483337},
doi = {10.1109/LATW.2016.7483337},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/SchivittzFMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/LieblMB16,
author = {Eduardo Liebl and
Cristina Meinhardt and
Paulo F. Butzen},
title = {Reliability analysis of majority voters under permanent faults},
booktitle = {17th Latin-American Test Symposium, {LATS} 2016, Foz do Iguacu, Brazil,
April 6-8, 2016},
pages = {180},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/LATW.2016.7483360},
doi = {10.1109/LATW.2016.7483360},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/LieblMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/SchivittzFFNMB16,
author = {Rafael B. Schivittz and
Rafael Fritz and
Denis Teixeira Franco and
Lirida A. B. Naviner and
Cristina Meinhardt and
Paulo F. Butzen},
title = {Inserting permanent fault input dependence on {PTM} to improve robustness
evaluation},
booktitle = {29th Symposium on Integrated Circuits and Systems Design, {SBCCI}
2016, Belo Horizonte, Brazil, August 29 - September 3, 2016},
pages = {1--6},
publisher = {{IEEE}},
year = {2016},
url = {https://doi.org/10.1109/SBCCI.2016.7724070},
doi = {10.1109/SBCCI.2016.7724070},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/SchivittzFFNMB16.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/AvelarBR15,
author = {Helder H. Avelar and
Paulo F. Butzen and
Renato P. Ribas},
title = {Automatic circuit generation for sequential logic debug},
booktitle = {2015 {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},
pages = {141--144},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICECS.2015.7440269},
doi = {10.1109/ICECS.2015.7440269},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/AvelarBR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SchivittzMB15,
author = {Rafael B. Schivittz and
Cristina Meinhardt and
Paulo F. Butzen},
title = {An evaluation of {BTI} degradation of 32nm standard cells},
booktitle = {2015 {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2015, Cairo, Egypt, December 6-9, 2015},
pages = {661--664},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/ICECS.2015.7440403},
doi = {10.1109/ICECS.2015.7440403},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SchivittzMB15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FlachMFPBJR15,
author = {Guilherme Flach and
Jucemar Monteiro and
Mateus Foga{\c{c}}a and
Julia Casarin Puget and
Paulo F. Butzen and
Marcelo O. Johann and
Ricardo Augusto da Luz Reis},
title = {An Incremental Timing-Driven flow using quadratic formulation for
detailed placement},
booktitle = {2015 {IFIP/IEEE} International Conference on Very Large Scale Integration,
VLSI-SoC 2015, Daejeon, South Korea, October 5-7, 2015},
pages = {1--6},
publisher = {{IEEE}},
year = {2015},
url = {https://doi.org/10.1109/VLSI-SoC.2015.7314382},
doi = {10.1109/VLSI-SOC.2015.7314382},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FlachMFPBJR15.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/NunesBRR13,
author = {Cicero Nunes and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {BTI, {HCI} and {TDDB} aging impact in flip-flops},
journal = {Microelectron. Reliab.},
volume = {53},
number = {9-11},
pages = {1355--1359},
year = {2013},
url = {https://doi.org/10.1016/j.microrel.2013.07.044},
doi = {10.1016/J.MICROREL.2013.07.044},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/NunesBRR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/ButzenBRR13,
author = {Paulo F. Butzen and
Vin{\'{\i}}cius Dal Bem and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {{BTI} and {HCI} first-order aging estimation for early use in standard
cell technology mapping},
journal = {Microelectron. Reliab.},
volume = {53},
number = {9-11},
pages = {1360--1364},
year = {2013},
url = {https://doi.org/10.1016/j.microrel.2013.07.087},
doi = {10.1016/J.MICROREL.2013.07.087},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/ButzenBRR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/NunesBRR13,
author = {Cicero Nunes and
Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {A methodology to evaluate the aging impact on flip-flops performance},
booktitle = {26th Symposium on Integrated Circuits and Systems Design, {SBCCI}
2013, Curitiba, Brazil, September 2-6, 2013},
pages = {1--6},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/SBCCI.2013.6644860},
doi = {10.1109/SBCCI.2013.6644860},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/NunesBRR13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/ButzenBRR12,
author = {Paulo F. Butzen and
Vin{\'{\i}}cius Dal Bem and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Design of {CMOS} logic gates with enhanced robustness against aging
degradation},
journal = {Microelectron. Reliab.},
volume = {52},
number = {9-10},
pages = {1822--1826},
year = {2012},
url = {https://doi.org/10.1016/j.microrel.2012.06.092},
doi = {10.1016/J.MICROREL.2012.06.092},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/ButzenBRR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KeaneVBK11,
author = {John Keane and
Shrinivas Venkatraman and
Paulo F. Butzen and
Chris H. Kim},
title = {An Array-Based Test Circuit for Fully Automated Gate Dielectric Breakdown
Characterization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {5},
pages = {787--795},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2010.2041258},
doi = {10.1109/TVLSI.2010.2041258},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KeaneVBK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/BemBMRR11,
author = {Vin{\'{\i}}cius Dal Bem and
Paulo F. Butzen and
Felipe S. Marranghello and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Impact and optimization of lithography-aware regular layout in digital
circuit design},
booktitle = {{IEEE} 29th International Conference on Computer Design, {ICCD} 2011,
Amherst, MA, USA, October 9-12, 2011},
pages = {279--284},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/ICCD.2011.6081409},
doi = {10.1109/ICCD.2011.6081409},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/BemBMRR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/BemBKCRR11,
author = {Vin{\'{\i}}cius Dal Bem and
Paulo F. Butzen and
Carlos Eduardo Klock and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
editor = {Antonio Carlos Cavalcanti and
Elmar U. K. Melcher and
J{\"{u}}rgen Becker},
title = {Area impact analysis of via-configurable regular fabric for digital
integrated circuit design},
booktitle = {24th Symposium on Integrated Circuits and Systems Design, {SBCCI}
'11, Jo{\~{a}}o Pessoa, Brazil, August 30 - September 2, 2011},
pages = {103--108},
publisher = {{ACM}},
year = {2011},
url = {https://doi.org/10.1145/2020876.2020901},
doi = {10.1145/2020876.2020901},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/sbcci/BemBKCRR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/ButzenBRR10,
author = {Paulo F. Butzen and
Vin{\'{\i}}cius Dal Bem and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Leakage Analysis Considering the Effect of Inter-Cell Wire Resistance
for Nanoscaled {CMOS} Circuits},
journal = {J. Low Power Electron.},
volume = {6},
number = {1},
pages = {192--200},
year = {2010},
url = {https://doi.org/10.1166/jolpe.2010.1070},
doi = {10.1166/JOLPE.2010.1070},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/ButzenBRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/ButzenRFRR10,
author = {Paulo F. Butzen and
Leomar S. da Rosa Jr. and
Erasmo J. D. Chiappetta Filho and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Standby power consumption estimation by interacting leakage current
mechanisms in nanoscaled {CMOS} digital circuits},
journal = {Microelectron. J.},
volume = {41},
number = {4},
pages = {247--255},
year = {2010},
url = {https://doi.org/10.1016/j.mejo.2010.03.003},
doi = {10.1016/J.MEJO.2010.03.003},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mj/ButzenRFRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mr/ButzenBRR10,
author = {Paulo F. Butzen and
Vin{\'{\i}}cius Dal Bem and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {Transistor network restructuring against {NBTI} degradation},
journal = {Microelectron. Reliab.},
volume = {50},
number = {9-11},
pages = {1298--1303},
year = {2010},
url = {https://doi.org/10.1016/j.microrel.2010.07.140},
doi = {10.1016/J.MICROREL.2010.07.140},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/mr/ButzenBRR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ButzenRR09,
author = {Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
editor = {Jos{\'{e}} Monteiro and
Rene van Leuken},
title = {Routing Resistance Influence in Loading Effect on Leakage Analysis},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 19th International Workshop, {PATMOS} 2009, Delft,
The Netherlands, September 9-11, 2009, Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5953},
pages = {317--325},
publisher = {Springer},
year = {2009},
url = {https://doi.org/10.1007/978-3-642-11802-9\_36},
doi = {10.1007/978-3-642-11802-9\_36},
timestamp = {Tue, 13 Sep 2022 21:45:42 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ButzenRR09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/KeaneVBK08,
author = {John Keane and
Shrinivas Venkatraman and
Paulo F. Butzen and
Chris H. Kim},
title = {An array-based test circuit for fully automated gate dielectric breakdown
characterization},
booktitle = {Proceedings of the {IEEE} 2008 Custom Integrated Circuits Conference,
{CICC} 2008, DoubleTree Hotel, San Jose, California, USA, September
21-24, 2008},
pages = {121--124},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/CICC.2008.4672036},
doi = {10.1109/CICC.2008.4672036},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cicc/KeaneVBK08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ButzenRFMRR08,
author = {Paulo F. Butzen and
Leomar S. da Rosa Jr. and
Erasmo J. D. Chiappetta Filho and
Dionatan S. Moura and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Simple and accurate method for fast static currentestimation in cmos
complex gates with interaction ofleakage mechanisms},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {407--410},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366207},
doi = {10.1145/1366110.1366207},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ButzenRFMRR08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ButzenRKR07,
author = {Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Chris H. Kim and
Renato P. Ribas},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Modeling and estimating leakage current in series-parallel {CMOS}
networks},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {269--274},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228852},
doi = {10.1145/1228784.1228852},
timestamp = {Wed, 16 Aug 2023 21:16:32 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/ButzenRKR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ButzenRKR07,
author = {Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Chris H. Kim and
Renato P. Ribas},
title = {Modeling Subthreshold Leakage Current in General Transistor Networks},
booktitle = {2007 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2007), May 9-11, 2007, Porto Alegre, Brazil},
pages = {512--513},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ISVLSI.2007.68},
doi = {10.1109/ISVLSI.2007.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ButzenRKR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ButzenRKR07,
author = {Paulo F. Butzen and
Andr{\'{e}} In{\'{a}}cio Reis and
Chris H. Kim and
Renato P. Ribas},
editor = {Nadine Az{\'{e}}mard and
Lars J. Svensson},
title = {Subthreshold Leakage Modeling and Estimation of General {CMOS} Complex
Gates},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 17th International Workshop, {PATMOS} 2007, Gothenburg,
Sweden, September 3-5, 2007, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4644},
pages = {474--484},
publisher = {Springer},
year = {2007},
url = {https://doi.org/10.1007/978-3-540-74442-9\_46},
doi = {10.1007/978-3-540-74442-9\_46},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ButzenRKR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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