BibTeX records: José V. Busquets-Mataix

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@article{DBLP:journals/tjs/DominguezMBH19,
  author       = {Carlos Dom{\'{\i}}nguez and
                  Juan{-}Miguel Martinez{-}Rubio and
                  Jos{\'{e}} V. Busquets{-}Mataix and
                  Houcine Hassan},
  title        = {Human-computer cooperation platform for developing real-time robotic
                  applications},
  journal      = {J. Supercomput.},
  volume       = {75},
  number       = {4},
  pages        = {1849--1868},
  year         = {2019},
  url          = {https://doi.org/10.1007/s11227-018-2343-4},
  doi          = {10.1007/S11227-018-2343-4},
  timestamp    = {Fri, 22 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/tjs/DominguezMBH19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Busquets-MataixCC11,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Carlos Catal{\'{a}} and
                  Antonio Mart{\'{\i}} Campoy},
  editor       = {Jos{\'{e}} L. Ayala and
                  Braulio Garc{\'{\i}}a{-}C{\'{a}}mara and
                  Manuel Prieto and
                  Martino Ruggiero and
                  Gilles Sicard},
  title        = {Architecture Extensions for Efficient Management of Scratch-Pad Memory},
  booktitle    = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization,
                  and Simulation - 21st International Workshop, {PATMOS} 2011, Madrid,
                  Spain, September 26-29, 2011. Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {6951},
  pages        = {43--52},
  publisher    = {Springer},
  year         = {2011},
  url          = {https://doi.org/10.1007/978-3-642-24154-3\_5},
  doi          = {10.1007/978-3-642-24154-3\_5},
  timestamp    = {Sun, 02 Oct 2022 16:13:24 +0200},
  biburl       = {https://dblp.org/rec/conf/patmos/Busquets-MataixCC11.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/CampoyPIB05,
  author       = {Antonio Mart{\'{\i}} Campoy and
                  Isabelle Puaut and
                  Angel Perles Ivars and
                  Jos{\'{e}} V. Busquets{-}Mataix},
  title        = {Cache Contents Selection for Statically-Locked Instruction Caches:
                  An Algorithm Comparison},
  booktitle    = {17th Euromicro Conference on Real-Time Systems {(ECRTS} 2005), 6-8
                  July 2005, Palma de Mallorca, Spain, Proceedings},
  pages        = {49--56},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ECRTS.2005.34},
  doi          = {10.1109/ECRTS.2005.34},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ecrts/CampoyPIB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icess/CampoyTSRB05,
  author       = {Antonio Mart{\'{\i}} Campoy and
                  Eugenio Tamura and
                  Sergio S{\'{a}}ez and
                  Francisco Rodr{\'{\i}}guez and
                  Jos{\'{e}} V. Busquets{-}Mataix},
  editor       = {Laurence Tianruo Yang and
                  Xingshe Zhou and
                  Wei Zhao and
                  Zhaohui Wu and
                  Yian Zhu and
                  Man Lin},
  title        = {On Using Locking Caches in Embedded Real-Time Systems},
  booktitle    = {Embedded Software and Systems, Second International Conference, {ICESS}
                  2005, Xi'an, China, December 16-18, 2005, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {3820},
  pages        = {150--159},
  publisher    = {Springer},
  year         = {2005},
  url          = {https://doi.org/10.1007/11599555\_17},
  doi          = {10.1007/11599555\_17},
  timestamp    = {Thu, 06 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/icess/CampoyTSRB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/CampoySPB03,
  author       = {Antonio Mart{\'{\i}} Campoy and
                  Sergio S{\'{a}}ez and
                  Angel Perles and
                  J. V. Busquets},
  editor       = {Jing Chen and
                  Seongsoo Hong},
  title        = {Schedulability Analysis in {EDF} Scheduler with Cache Memories},
  booktitle    = {Real-Time and Embedded Computing Systems and Applications, 9th International
                  Conference, {RTCSA} 2003, Tainan, Taiwan, February 18-20, 2003. Revised
                  Papers},
  series       = {Lecture Notes in Computer Science},
  volume       = {2968},
  pages        = {328--341},
  publisher    = {Springer},
  year         = {2003},
  url          = {https://doi.org/10.1007/978-3-540-24686-2\_20},
  doi          = {10.1007/978-3-540-24686-2\_20},
  timestamp    = {Thu, 06 May 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/rtcsa/CampoySPB03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jsa/Busquets-MataixGGW00,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Daniel Gil and
                  Pedro J. Gil and
                  Andy J. Wellings},
  title        = {Techniques to increase the schedulable utilization of cache-based
                  preemptive real-time systems},
  journal      = {J. Syst. Archit.},
  volume       = {46},
  number       = {4},
  pages        = {357--378},
  year         = {2000},
  url          = {https://doi.org/10.1016/S1383-7621(99)00011-9},
  doi          = {10.1016/S1383-7621(99)00011-9},
  timestamp    = {Tue, 19 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/jsa/Busquets-MataixGGW00.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mam/CampeloRROGLBAS99,
  author       = {Jos{\'{e}} Carlos Campelo and
                  Francisco Rodr{\'{\i}}guez and
                  Alicia Rubio and
                  Rafael Ors and
                  Pedro J. Gil and
                  Lenin Lemus and
                  J. V. Busquets and
                  Jos{\'{e}} Albaladejo and
                  Juan Jos{\'{e}} Serrano},
  title        = {Distributed industrial control systems: a fault-tolerant architecture},
  journal      = {Microprocess. Microsystems},
  volume       = {23},
  number       = {2},
  pages        = {103--112},
  year         = {1999},
  url          = {https://doi.org/10.1016/S0141-9331(99)00019-8},
  doi          = {10.1016/S0141-9331(99)00019-8},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/mam/CampeloRROGLBAS99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/edcc/GilMBBG99,
  author       = {Daniel Gil and
                  R. Mart{\'{\i}}nez and
                  J. V. Busquets and
                  Juan Carlos Baraza and
                  Pedro J. Gil},
  editor       = {Jan Hlavicka and
                  Erik Maehle and
                  Andr{\'{a}}s Pataricza},
  title        = {Fault Injection into {VHDL} Models: Experimental Validation of a Fault
                  Tolerant Microcomputer System},
  booktitle    = {Dependable Computing - EDCC-3, Third European Dependable Computing
                  Conference, Prague, Czech Republic, September 15-17, 1999, Proceedings},
  series       = {Lecture Notes in Computer Science},
  volume       = {1667},
  pages        = {191--208},
  publisher    = {Springer},
  year         = {1999},
  url          = {https://doi.org/10.1007/3-540-48254-7\_14},
  doi          = {10.1007/3-540-48254-7\_14},
  timestamp    = {Tue, 14 May 2019 10:00:54 +0200},
  biburl       = {https://dblp.org/rec/conf/edcc/GilMBBG99.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/euromicro/GilBBG98,
  author       = {Daniel Gil and
                  Juan Carlos Baraza and
                  J. V. Busquets and
                  Pedro J. Gil},
  title        = {Fault Injection into {VHDL} Models: Analysis of the Error Syndrome
                  of a Microcomputer System},
  booktitle    = {24th {EUROMICRO} '98 Conference, Engineering Systems and Software
                  for the Next Decade, 25-27 August 1998, Vesteras, Sweden},
  pages        = {10418--10425},
  publisher    = {{IEEE} Computer Society},
  year         = {1998},
  url          = {https://doi.org/10.1109/EURMIC.1998.711835},
  doi          = {10.1109/EURMIC.1998.711835},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/euromicro/GilBBG98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/Busquets-MataixSW97,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Juan Jos{\'{e}} Serrano and
                  Andy J. Wellings},
  title        = {Hybrid instruction cache partitioning for preemptive real-time systems},
  booktitle    = {Proceedings of the Ninth Euromicro Workshop on Real-Time Systems,
                  {RTS} 1997, 11-13 June, 1997, Toledo, Spain},
  pages        = {56--63},
  publisher    = {{IEEE} Computer Society},
  year         = {1997},
  url          = {https://doi.org/10.1109/EMWRTS.1997.613764},
  doi          = {10.1109/EMWRTS.1997.613764},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ecrts/Busquets-MataixSW97.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ecrts/Busquets-MataixSCGW96,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Juan Jos{\'{e}} Serrano and
                  Rafael Ors Carot and
                  Pedro J. Gil and
                  Andrew J. Wellings},
  title        = {Adding Instruction Cache Effect to an Exact Schedulability Analysis
                  of Preemptive Real-Time Systems},
  booktitle    = {Proceedings of the Eighth Euromicro Workshop on Real-Time Systems,
                  {RTS} 1996, L'Aquila, Italy, June 12-14, 1996},
  pages        = {271--276},
  publisher    = {{IEEE} Computer Society},
  year         = {1996},
  url          = {https://doi.org/10.1109/EMWRTS.1996.557940},
  doi          = {10.1109/EMWRTS.1996.557940},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/ecrts/Busquets-MataixSCGW96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtas/Busquets-MataixSOGW96,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Juan Jos{\'{e}} Serrano and
                  Rafael Ors and
                  Pedro J. Gil and
                  Andy J. Wellings},
  title        = {Adding instruction cache effect to schedulability analysis of preemptive
                  real-time systems},
  booktitle    = {2nd {IEEE} Real-Time Technology and Applications Symposium, {RTAS}
                  '96, Boston, MA, USA, June 10-12, 1996},
  pages        = {204--212},
  publisher    = {{IEEE} Computer Society},
  year         = {1996},
  url          = {https://doi.org/10.1109/RTTAS.1996.509537},
  doi          = {10.1109/RTTAS.1996.509537},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/rtas/Busquets-MataixSOGW96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/Busquets-MataixSOGW96,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Juan Jos{\'{e}} Serrano and
                  Rafael Ors and
                  Pedro J. Gil and
                  Andy J. Wellings},
  title        = {Using harmonic task-sets to increase the schedulable utilization of
                  cache-based preemptive real-time systems},
  booktitle    = {Third International Workshop on Real-Time Computing Systems Application
                  {(RTCSA} '96), October 30 - November 01, 1996, Seoul, Korea},
  pages        = {195--202},
  publisher    = {{IEEE} Computer Society},
  year         = {1996},
  url          = {https://doi.org/10.1109/RTCSA.1996.554977},
  doi          = {10.1109/RTCSA.1996.554977},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/rtcsa/Busquets-MataixSOGW96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/rtcsa/Busquets-MataixS95,
  author       = {Jos{\'{e}} V. Busquets{-}Mataix and
                  Juan Jos{\'{e}} Serrano},
  title        = {The impact of extrinsic cache performance on predictability of real-time
                  systems},
  booktitle    = {2nd International Workshop on Real-Time Computing Systems and Applications,
                  October 25 - 27, 1995, Tokyo, Japan},
  pages        = {8--15},
  publisher    = {{IEEE} Computer Society},
  year         = {1995},
  url          = {https://doi.org/10.1109/RTCSA.1995.528744},
  doi          = {10.1109/RTCSA.1995.528744},
  timestamp    = {Thu, 23 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/rtcsa/Busquets-MataixS95.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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