Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDBibTeX records: Magdy S. Abadir
@article{DBLP:journals/tvlsi/AliotoAABBCCCCC19,
author = {Massimo Alioto and
Magdy S. Abadir and
Tughrul Arslan and
Chirn Chye Boon and
Andreas Burg and
Chip{-}Hong Chang and
Meng{-}Fan Chang and
Yao{-}Wen Chang and
Poki Chen and
Pasquale Corsonello and
Paolo Crovetti and
Shiro Dosho and
Rolf Drechsler and
Ibrahim Abe M. Elfadel and
Ruonan Han and
Masanori Hashimoto and
Chun{-}Huat Heng and
Deukhyoun Heo and
Tsung{-}Yi Ho and
Houman Homayoun and
Yuh{-}Shyan Hwang and
Ajay Joshi and
Rajiv V. Joshi and
Tanay Karnik and
Chulwoo Kim and
Tony Tae{-}Hyoung Kim and
Jaydeep Kulkarni and
Volkan Kursun and
Yoonmyung Lee and
Hai Helen Li and
Huawei Li and
Prabhat Mishra and
Baker Mohammad and
Mehran Mozaffari Kermani and
Makoto Nagata and
Koji Nii and
Partha Pratim Pande and
Bipul C. Paul and
Vasilis F. Pavlidis and
Jos{\'{e}} Pineda de Gyvez and
Ioannis Savidis and
Patrick Schaumont and
Fabio Sebastiano and
Anirban Sengupta and
Mingoo Seok and
Mircea R. Stan and
Mark M. Tehranipoor and
Aida Todri{-}Sanial and
Marian Verhelst and
Valerio Vignoli and
Xiaoqing Wen and
Jiang Xu and
Wei Zhang and
Zhengya Zhang and
Jun Zhou and
Mark Zwolinski and
Stacey Weber},
title = {Editorial {TVLSI} Positioning - Continuing and Accelerating an Upward
Trajectory},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {27},
number = {2},
pages = {253--280},
year = {2019},
url = {https://doi.org/10.1109/TVLSI.2018.2886389},
doi = {10.1109/TVLSI.2018.2886389},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AliotoAABBCCCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirBCW17,
author = {Magdy S. Abadir and
Jayanta Bhadra and
Wen Chen and
Li{-}C. Wang},
title = {Guest Editors' Introduction: Emerging Challenges and Solutions in
SoC Verification},
journal = {{IEEE} Des. Test},
volume = {34},
number = {5},
pages = {5--6},
year = {2017},
url = {https://doi.org/10.1109/MDAT.2017.2729938},
doi = {10.1109/MDAT.2017.2729938},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/AbadirBCW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/ChenRBAW17,
author = {Wen Chen and
Sandip Ray and
Jayanta Bhadra and
Magdy S. Abadir and
Li{-}C. Wang},
title = {Challenges and Trends in Modern SoC Design Verification},
journal = {{IEEE} Des. Test},
volume = {34},
number = {5},
pages = {7--22},
year = {2017},
url = {https://doi.org/10.1109/MDAT.2017.2735383},
doi = {10.1109/MDAT.2017.2735383},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/ChenRBAW17.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangA14,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {Data Mining In {EDA} - Basic Principles, Promises, and Constraints},
booktitle = {The 51st Annual Design Automation Conference 2014, {DAC} '14, San
Francisco, CA, USA, June 1-5, 2014},
pages = {159:1--159:6},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2593069.2596675},
doi = {10.1145/2593069.2596675},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WangA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/TikkanenSWA14,
author = {Jeff Tikkanen and
Nik Sumikawa and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Multivariate outlier modeling for capturing customer returns - How
simple it can be},
booktitle = {2014 {IEEE} 20th International On-Line Testing Symposium, {IOLTS}
2014, Platja d'Aro, Girona, Spain, July 7-9, 2014},
pages = {164--169},
publisher = {{IEEE}},
year = {2014},
url = {https://doi.org/10.1109/IOLTS.2014.6873663},
doi = {10.1109/IOLTS.2014.6873663},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/iolts/TikkanenSWA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/TikkanenSSWA14,
author = {Jeff Tikkanen and
Sebastian Siatkowski and
Nik Sumikawa and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Yield optimization using advanced statistical correlation methods},
booktitle = {2014 International Test Conference, {ITC} 2014, Seattle, WA, USA,
October 20-23, 2014},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2014},
url = {https://doi.org/10.1109/TEST.2014.7035326},
doi = {10.1109/TEST.2014.7035326},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/TikkanenSSWA14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/RayBAW13,
author = {Sandip Ray and
Jay Bhadra and
Magdy S. Abadir and
Li{-}C. Wang},
title = {Guest Editorial: Test and Verification Challenges for Future Microprocessors
and SoC Designs},
journal = {J. Electron. Test.},
volume = {29},
number = {5},
pages = {621--623},
year = {2013},
url = {https://doi.org/10.1007/s10836-013-5411-y},
doi = {10.1007/S10836-013-5411-Y},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/RayBAW13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ChenWBA13,
author = {Wen Chen and
Li{-}C. Wang and
Jay Bhadra and
Magdy S. Abadir},
title = {Simulation knowledge extraction and reuse in constrained random processor
verification},
booktitle = {The 50th Annual Design Automation Conference 2013, {DAC} '13, Austin,
TX, USA, May 29 - June 07, 2013},
pages = {120:1--120:6},
publisher = {{ACM}},
year = {2013},
url = {https://doi.org/10.1145/2463209.2488881},
doi = {10.1145/2463209.2488881},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ChenWBA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SumikawaWA13,
author = {Nik Sumikawa and
Li{-}C. Wang and
Magdy S. Abadir},
title = {A pattern mining framework for inter-wafer abnormality analysis},
booktitle = {2013 {IEEE} International Test Conference, {ITC} 2013, Anaheim, CA,
USA, September 6-13, 2013},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2013},
url = {https://doi.org/10.1109/TEST.2013.6651890},
doi = {10.1109/TEST.2013.6651890},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SumikawaWA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NassifPA13,
author = {Sani R. Nassif and
Yale N. Patt and
Magdy S. Abadir},
editor = {Martin Margala and
Ricardo Augusto da Luz Reis and
Alex Orailoglu and
Luigi Carro and
Lu{\'{\i}}s Miguel Silveira and
H. Fatih Ugurdag},
title = {Keynote 1 - {VLSI} 2.0: R{\&}D Post Moore},
booktitle = {21st {IEEE/IFIP} International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLSI-SoC.2013.6673229},
doi = {10.1109/VLSI-SOC.2013.6673229},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/NassifPA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/ChenWBA13,
author = {Wen Chen and
Li{-}C. Wang and
Jayanta Bhadra and
Magdy S. Abadir},
title = {Novel test analysis to improve structural coverage - {A} commercial
experiment},
booktitle = {2013 International Symposium on {VLSI} Design, Automation, and Test,
{VLSI-DAT} 2013, Hsinchu, Taiwan, April 22-24, 2013},
pages = {1--4},
publisher = {{IEEE}},
year = {2013},
url = {https://doi.org/10.1109/VLDI-DAT.2013.6533851},
doi = {10.1109/VLDI-DAT.2013.6533851},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/ChenWBA13.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/RayBAWG12,
author = {Sandip Ray and
Jayanta Bhadra and
Magdy S. Abadir and
Li{-}C. Wang and
Aarti Gupta},
title = {Introduction to special section on verification challenges in the
concurrent world},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {17},
number = {3},
pages = {19:1--19:3},
year = {2012},
url = {https://doi.org/10.1145/2209291.2209292},
doi = {10.1145/2209291.2209292},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/RayBAWG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/ChenSWBFA12,
author = {Wen Chen and
Nik Sumikawa and
Li{-}C. Wang and
Jayanta Bhadra and
Xiushan Feng and
Magdy S. Abadir},
editor = {Alan J. Hu},
title = {Novel test detection to improve simulation efficiency - {A} commercial
experiment},
booktitle = {2012 {IEEE/ACM} International Conference on Computer-Aided Design,
{ICCAD} 2012, San Jose, CA, USA, November 5-8, 2012},
pages = {101--108},
publisher = {{ACM}},
year = {2012},
url = {https://doi.org/10.1145/2429384.2429404},
doi = {10.1145/2429384.2429404},
timestamp = {Mon, 09 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iccad/ChenSWBFA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SumikawaTWWA12,
author = {Nik Sumikawa and
Jeff Tikkanen and
Li{-}C. Wang and
LeRoy Winemberg and
Magdy S. Abadir},
title = {Screening customer returns with multivariate test analysis},
booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA,
USA, November 5-8, 2012},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/TEST.2012.6401547},
doi = {10.1109/TEST.2012.6401547},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SumikawaTWWA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SumikawaWA12,
author = {Nik Sumikawa and
Li{-}C. Wang and
Magdy S. Abadir},
title = {An experiment of burn-in time reduction based on parametric test analysis},
booktitle = {2012 {IEEE} International Test Conference, {ITC} 2012, Anaheim, CA,
USA, November 5-8, 2012},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2012},
url = {https://doi.org/10.1109/TEST.2012.6401595},
doi = {10.1109/TEST.2012.6401595},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SumikawaWA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi-dat/AbadirSCW12,
author = {Magdy S. Abadir and
Nik Sumikawa and
Wen Chen and
Li{-}C. Wang},
title = {Data mining based prediction paradigm and its applications in design
automation},
booktitle = {Proceedings of Technical Program of 2012 {VLSI} Design, Automation
and Test, {VLSI-DAT} 2012, Hsinchu, Taiwan, April 23-25, 2012},
pages = {1},
publisher = {{IEEE}},
year = {2012},
url = {https://doi.org/10.1109/VLSI-DAT.2012.6212643},
doi = {10.1109/VLSI-DAT.2012.6212643},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vlsi-dat/AbadirSCW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/DrmanacSWWA11,
author = {Dragoljub Gagi Drmanac and
Nik Sumikawa and
LeRoy Winemberg and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Multidimensional parametric test set optimization of wafer probe data
for predicting in field failures and setting tighter test limits},
booktitle = {Design, Automation and Test in Europe, {DATE} 2011, Grenoble, France,
March 14-18, 2011},
pages = {794--799},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/DATE.2011.5763135},
doi = {10.1109/DATE.2011.5763135},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/DrmanacSWWA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/SumikawaDWWA11,
author = {Nik Sumikawa and
Dragoljub Gagi Drmanac and
Li{-}C. Wang and
LeRoy Winemberg and
Magdy S. Abadir},
editor = {Bill Eklow and
R. D. (Shawn) Blanton},
title = {Forward prediction based on wafer sort data - {A} case study},
booktitle = {2011 {IEEE} International Test Conference, {ITC} 2011, Anaheim, CA,
USA, September 20-22, 2011},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/TEST.2011.6139174},
doi = {10.1109/TEST.2011.6139174},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/SumikawaDWWA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/SumikawaDWWA11,
author = {Nik Sumikawa and
Dragoljub Gagi Drmanac and
Li{-}C. Wang and
LeRoy Winemberg and
Magdy S. Abadir},
title = {Understanding customer returns from a test perspective},
booktitle = {29th {IEEE} {VLSI} Test Symposium, {VTS} 2011, May 1-5, 2011, Dana
Point, California, {USA}},
pages = {2--7},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://doi.org/10.1109/VTS.2011.5783746},
doi = {10.1109/VTS.2011.5783746},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/vts/SumikawaDWWA11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtv/2011,
editor = {Magdy S. Abadir and
Jay Bhadra and
Li{-}C. Wang},
title = {12th International Workshop on Microprocessor Test and Verification,
{MTV} 2011, Austin, TX, USA, December 5-7, 2011},
publisher = {{IEEE} Computer Society},
year = {2011},
url = {https://ieeexplore.ieee.org/xpl/conhome/6142154/proceeding},
isbn = {978-1-4577-2101-4},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/2011.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BastaniCWA10,
author = {Pouria Bastani and
Nicholas Callegari and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch},
journal = {{IEEE} Des. Test Comput.},
volume = {27},
number = {3},
pages = {42--53},
year = {2010},
url = {https://doi.org/10.1109/MDT.2009.95},
doi = {10.1109/MDT.2009.95},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BastaniCWA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/CallegariDWA10,
author = {Nicholas Callegari and
Dragoljub Gagi Drmanac and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Sachin S. Sapatnekar},
title = {Classification rule learning using subgroup discovery of cross-domain
attributes responsible for design-silicon mismatch},
booktitle = {Proceedings of the 47th Design Automation Conference, {DAC} 2010,
Anaheim, California, USA, July 13-18, 2010},
pages = {374--379},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1837274.1837368},
doi = {10.1145/1837274.1837368},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/CallegariDWA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/SenA10,
author = {Alper Sen and
Magdy S. Abadir},
title = {Coverage metrics for verification of concurrent SystemC designs using
mutation testing},
booktitle = {{IEEE} International High Level Design Validation and Test Workshop,
{HLDVT} 2010, Anaheim, CA, USA, 10-12 June 2010},
pages = {75--81},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://doi.org/10.1109/HLDVT.2010.5496659},
doi = {10.1109/HLDVT.2010.5496659},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/SenA10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/sbcci/Abadir10,
author = {Magdy S. Abadir},
editor = {Jo{\~{a}}o Antonio Martino and
Guido Araujo and
Alex Orailoglu and
Felipe Klein},
title = {Design for reality: knowledge discovery in design and test data},
booktitle = {Proceedings of the 23rd Annual Symposium on Integrated Circuits and
Systems Design, {SBCCI} 2010, S{\~{a}}o Paulo, Brazil, September 6-9,
2010},
pages = {54},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1854153.1854169},
doi = {10.1145/1854153.1854169},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/sbcci/Abadir10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtv/2010,
editor = {Magdy S. Abadir and
Jay Bhadra and
Li{-}C. Wang},
title = {11th International Workshop on Microprocessor Test and Verification,
{MTV} 2010, Austin, TX, USA, December 13-15, 2010},
publisher = {{IEEE} Computer Society},
year = {2010},
url = {https://ieeexplore.ieee.org/xpl/conhome/5975323/proceeding},
isbn = {978-0-7695-4354-3},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/2010.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CallegariBWA09,
author = {Nicholas Callegari and
Pouria Bastani and
Li{-}C. Wang and
Magdy S. Abadir},
title = {A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing
Mismatch},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {28},
number = {11},
pages = {1728--1741},
year = {2009},
url = {https://doi.org/10.1109/TCAD.2009.2030394},
doi = {10.1109/TCAD.2009.2030394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CallegariBWA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KhajehGDKEKA09,
author = {Amin Khajeh and
Aseem Gupta and
Nikil D. Dutt and
Fadi J. Kurdahi and
Ahmed M. Eltawil and
Kamal S. Khouri and
Magdy S. Abadir},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {{TRAM:} {A} tool for Temperature and Reliability Aware Memory Design},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {340--345},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090685},
doi = {10.1109/DATE.2009.5090685},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KhajehGDKEKA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/DrmanacBWA09,
author = {Dragoljub Gagi Drmanac and
Brendon Bolin and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Gordon W. Roberts and
Bill Eklow},
title = {Minimizing outlier delay test cost in the presence of systematic variability},
booktitle = {2009 {IEEE} International Test Conference, {ITC} 2009, Austin, TX,
USA, November 1-6, 2009},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2009},
url = {https://doi.org/10.1109/TEST.2009.5355643},
doi = {10.1109/TEST.2009.5355643},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/DrmanacBWA09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BastaniWA08,
author = {Pouria Bastani and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Linking Statistical Learning to Diagnosis},
journal = {{IEEE} Des. Test Comput.},
volume = {25},
number = {3},
pages = {232--239},
year = {2008},
url = {https://doi.org/10.1109/MDT.2008.79},
doi = {10.1109/MDT.2008.79},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BastaniWA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhadraTA08,
author = {Jayanta Bhadra and
Ekaterina Trofimova and
Magdy S. Abadir},
title = {Validating Power Architecture\({}^{\mbox{TM}}\) Technology-Based MPSoCs
Through Executable Specifications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {4},
pages = {388--396},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.917418},
doi = {10.1109/TVLSI.2008.917418},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhadraTA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/BastaniCWA08,
author = {Pouria Bastani and
Nicholas Callegari and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Limor Fix},
title = {Statistical diagnosis of unmodeled systematic timing effects},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {355--360},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391566},
doi = {10.1145/1391469.1391566},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/BastaniCWA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/SenOA08,
author = {Alper Sen and
Vinit Ogale and
Magdy S. Abadir},
editor = {Limor Fix},
title = {Predictive runtime verification of multi-processor SoCs in SystemC},
booktitle = {Proceedings of the 45th Design Automation Conference, {DAC} 2008,
Anaheim, CA, USA, June 8-13, 2008},
pages = {948--953},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1391469.1391708},
doi = {10.1145/1391469.1391708},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/SenOA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/GuptaDKKA08,
author = {Aseem Gupta and
Nikil D. Dutt and
Fadi J. Kurdahi and
Kamal S. Khouri and
Magdy S. Abadir},
title = {Thermal Aware Global Routing of {VLSI} Chips for Enhanced Reliability},
booktitle = {9th International Symposium on Quality of Electronic Design {(ISQED}
2008), 17-19 March 2008, San Jose, CA, {USA}},
pages = {470--475},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/ISQED.2008.4479779},
doi = {10.1109/ISQED.2008.4479779},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isqed/GuptaDKKA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BastaniCWA08,
author = {Pouria Bastani and
Nicholas Callegari and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Douglas Young and
Nur A. Touba},
title = {Diagnosis of design-silicon timing mismatch with feature encoding
and importance ranking - the methodology explained},
booktitle = {2008 {IEEE} International Test Conference, {ITC} 2008, Santa Clara,
California, USA, October 26-31, 2008},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2008},
url = {https://doi.org/10.1109/TEST.2008.4700588},
doi = {10.1109/TEST.2008.4700588},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BastaniCWA08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BhadraAW07,
author = {Jayanta Bhadra and
Magdy S. Abadir and
Li{-}C. Wang},
title = {Guest Editors' Introduction: Attacking Functional Verification through
Hybrid Techniques},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {2},
pages = {110--111},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.45},
doi = {10.1109/MDT.2007.45},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BhadraAW07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BhadraAWR07,
author = {Jayanta Bhadra and
Magdy S. Abadir and
Li{-}C. Wang and
Sandip Ray},
title = {A Survey of Hybrid Techniques for Functional Verification},
journal = {{IEEE} Des. Test Comput.},
volume = {24},
number = {2},
pages = {112--122},
year = {2007},
url = {https://doi.org/10.1109/MDT.2007.30},
doi = {10.1109/MDT.2007.30},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BhadraAWR07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/GuptaDKKA07,
author = {Aseem Gupta and
Nikil D. Dutt and
Fadi J. Kurdahi and
Kamal S. Khouri and
Magdy S. Abadir},
title = {{LEAF:} {A} System Level Leakage-Aware Floorplanner for SoCs},
booktitle = {Proceedings of the 12th Conference on Asia South Pacific Design Automation,
{ASP-DAC} 2007, Yokohama, Japan, January 23-26, 2007},
pages = {274--279},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/ASPDAC.2007.357998},
doi = {10.1109/ASPDAC.2007.357998},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/GuptaDKKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangBA07,
author = {Li{-}C. Wang and
Pouria Bastani and
Magdy S. Abadir},
title = {Design-Silicon Timing Correlation {A} Data Mining Perspective},
booktitle = {Proceedings of the 44th Design Automation Conference, {DAC} 2007,
San Diego, CA, USA, June 4-8, 2007},
pages = {384--389},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1145/1278480.1278580},
doi = {10.1145/1278480.1278580},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WangBA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/MangassarianVSNA07,
author = {Hratch Mangassarian and
Andreas G. Veneris and
Sean Safarpour and
Farid N. Najm and
Magdy S. Abadir},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Maximum circuit activity estimation using pseudo-boolean satisfiability},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {1538--1543},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://dl.acm.org/citation.cfm?id=1266703},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/MangassarianVSNA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/BastaniLWSA07,
author = {Pouria Bastani and
Benjamin N. Lee and
Li{-}C. Wang and
Savithri Sundareswaran and
Magdy S. Abadir},
editor = {Jill Sibert and
Janusz Rajski},
title = {Analyzing the risk of timing modeling based on path delay tests},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437587},
doi = {10.1109/TEST.2007.4437587},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/BastaniLWSA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/WuLWA07,
author = {Sean Hsi Yuan Wu and
Benjamin N. Lee and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Jill Sibert and
Janusz Rajski},
title = {Statistical analysis and optimization of parametric delay test},
booktitle = {2007 {IEEE} International Test Conference, {ITC} 2007, Santa Clara,
California, USA, October 21-26, 2007},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/TEST.2007.4437626},
doi = {10.1109/TEST.2007.4437626},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/WuLWA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/GuptaDKKA07,
author = {Aseem Gupta and
Nikil D. Dutt and
Fadi J. Kurdahi and
Kamal S. Khouri and
Magdy S. Abadir},
title = {{STEFAL:} {A} System Level Temperature- and Floorplan-Aware Leakage
Power Estimator for SoCs},
booktitle = {20th International Conference on {VLSI} Design {(VLSI} Design 2007),
Sixth International Conference on Embedded Systems {(ICES} 2007),
6-10 January 2007, Bangalore, India},
pages = {559--564},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://doi.org/10.1109/VLSID.2007.150},
doi = {10.1109/VLSID.2007.150},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/GuptaDKKA07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtv/2007,
editor = {Magdy S. Abadir and
Li{-}C. Wang and
Jayanta Bhadra},
title = {Eighth International Workshop on Microprocessor Test and Verification
{(MTV} 2007), Common Challenges and Solutions, 5-6 December 2007,
Austin, Texas, {USA}},
publisher = {{IEEE} Computer Society},
year = {2007},
url = {https://ieeexplore.ieee.org/xpl/conhome/4620135/proceeding},
isbn = {978-0-7695-3241-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/2007.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/GuptaDKKA06,
author = {Aseem Gupta and
Nikil D. Dutt and
Fadi J. Kurdahi and
Kamal S. Khouri and
Magdy S. Abadir},
editor = {Reinaldo A. Bergamaschi and
Kiyoung Choi},
title = {Floorplan driven leakage power aware IP-based SoC design space exploration},
booktitle = {Proceedings of the 4th International Conference on Hardware/Software
Codesign and System Synthesis, {CODES+ISSS} 2006, Seoul, Korea, October
22-25, 2006},
pages = {118--123},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1176254.1176284},
doi = {10.1145/1176254.1176284},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/GuptaDKKA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/LeeWA06,
author = {Benjamin N. Lee and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Ellen Sentovich},
title = {Refined statistical static timing analysis through},
booktitle = {Proceedings of the 43rd Design Automation Conference, {DAC} 2006,
San Francisco, CA, USA, July 24-28, 2006},
pages = {149--154},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1146909.1146952},
doi = {10.1145/1146909.1146952},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/LeeWA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/GuzeyWWFA06,
author = {Onur Guzey and
Charles H.{-}P. Wen and
Li{-}C. Wang and
Tao Feng and
Magdy S. Abadir},
title = {Extracting a simplified view of design functionality via vector simulation},
booktitle = {Eleventh Annual {IEEE} International High-Level Design Validation
and Test Workshop 2006, Monterey, CA, USA, Nov 9-10, 2006},
pages = {195--202},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/HLDVT.2006.319991},
doi = {10.1109/HLDVT.2006.319991},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/GuzeyWWFA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hvc/GuzeyWWFMA06,
author = {Onur Guzey and
Charles H.{-}P. Wen and
Li{-}C. Wang and
Tao Feng and
Hillel Miller and
Magdy S. Abadir},
editor = {Eyal Bin and
Avi Ziv and
Shmuel Ur},
title = {Extracting a Simplified View of Design Functionality Based on Vector
Simulation},
booktitle = {Hardware and Software, Verification and Testing, Second International
Haifa Verification Conference, {HVC} 2006, Haifa, Israel, October
23-26, 2006. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {4383},
pages = {34--49},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/978-3-540-70889-6\_3},
doi = {10.1007/978-3-540-70889-6\_3},
timestamp = {Tue, 15 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hvc/GuzeyWWFMA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/Abadir06,
author = {Magdy S. Abadir},
title = {Floorplanning and Thermal Impact on Leakage Power and Proper Operation
of Complex {SOC} Designs},
booktitle = {12th {IEEE} International On-Line Testing Symposium {(IOLTS} 2006),
10-12 July 2006, Como, Italy},
pages = {81},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/IOLTS.2006.39},
doi = {10.1109/IOLTS.2006.39},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/Abadir06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LeeWA06,
author = {Benjamin N. Lee and
Li{-}C. Wang and
Magdy S. Abadir},
editor = {Scott Davidson and
Anne Gattiker},
title = {Issues on Test Optimization with Known Good Dies and Known Defective
Dies - {A} Statistical Perspective},
booktitle = {2006 {IEEE} International Test Conference, {ITC} 2006, Santa Clara,
CA, USA, October 22-27, 2006},
pages = {1--10},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/TEST.2006.297640},
doi = {10.1109/TEST.2006.297640},
timestamp = {Tue, 12 Dec 2023 09:46:27 +0100},
biburl = {https://dblp.org/rec/conf/itc/LeeWA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/KooMBA06,
author = {Heon{-}Mo Koo and
Prabhat Mishra and
Jayanta Bhadra and
Magdy S. Abadir},
editor = {Magdy S. Abadir and
Li{-}C. Wang and
Jayanta Bhadra},
title = {Directed Micro-architectural Test Generation for an Industrial Processor:
{A} Case Study},
booktitle = {Seventh International Workshop on Microprocessor Test and Verification
{(MTV} 2006), Common Challenges and Solutions, 4-5 December 2006,
Austin, Texas, {USA}},
pages = {33--36},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://doi.org/10.1109/MTV.2006.10},
doi = {10.1109/MTV.2006.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/KooMBA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/socc/BhadraTGA06,
author = {Jayanta Bhadra and
Ekaterina Trofimova and
Leonard J. Giordano and
Magdy S. Abadir},
title = {A Trace-Driven Validation Methodology for Multi-Processor {SOCS}},
booktitle = {2006 {IEEE} International {SOC} Conference, Austin, Texas, USA, September
24-27, 2006},
pages = {145--148},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/SOCC.2006.283869},
doi = {10.1109/SOCC.2006.283869},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/socc/BhadraTGA06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtv/2006,
editor = {Magdy S. Abadir and
Li{-}C. Wang and
Jayanta Bhadra},
title = {Seventh International Workshop on Microprocessor Test and Verification
{(MTV} 2006), Common Challenges and Solutions, 4-5 December 2006,
Austin, Texas, {USA}},
publisher = {{IEEE} Computer Society},
year = {2006},
url = {https://ieeexplore.ieee.org/xpl/conhome/4197205/proceeding},
isbn = {978-0-7695-2839-7},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/2006.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/VenerisCAS05,
author = {Andreas G. Veneris and
Robert Chang and
Magdy S. Abadir and
Sep Seyedi},
title = {Functional Fault Equivalence and Diagnostic Test Generation in Combinational
Logic Circuits Using Conventional {ATPG}},
journal = {J. Electron. Test.},
volume = {21},
number = {5},
pages = {495--502},
year = {2005},
url = {https://doi.org/10.1007/s10836-005-1543-z},
doi = {10.1007/S10836-005-1543-Z},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/VenerisCAS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/ijes/MishraDKA05,
author = {Prabhat Mishra and
Nikil D. Dutt and
Narayanan Krishnamurthy and
Magdy S. Abadir},
title = {A methodology for validation of microprocessors using symbolic simulation},
journal = {Int. J. Embed. Syst.},
volume = {1},
number = {1/2},
pages = {14--22},
year = {2005},
url = {https://doi.org/10.1504/IJES.2005.008805},
doi = {10.1504/IJES.2005.008805},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/ijes/MishraDKA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WassungZABH05,
author = {Dennis Wassung and
Yervant Zorian and
Magdy S. Abadir and
Mark Bapst and
Colin Harris},
editor = {William H. Joyner Jr. and
Grant Martin and
Andrew B. Kahng},
title = {Choosing flows and methodologies for SoC design},
booktitle = {Proceedings of the 42nd Design Automation Conference, {DAC} 2005,
San Diego, CA, USA, June 13-17, 2005},
pages = {167},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1065579.1065580},
doi = {10.1145/1065579.1065580},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WassungZABH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/LiuAVS05,
author = {Jiang Brandon Liu and
Magdy S. Abadir and
Andreas G. Veneris and
Sean Safarpour},
editor = {John C. Lach and
Gang Qu and
Yehea I. Ismail},
title = {Diagnosing multiple transition faults in the absence of timing information},
booktitle = {Proceedings of the 15th {ACM} Great Lakes Symposium on {VLSI} 2005,
Chicago, Illinois, USA, April 17-19, 2005},
pages = {193--196},
publisher = {{ACM}},
year = {2005},
url = {https://doi.org/10.1145/1057661.1057708},
doi = {10.1145/1057661.1057708},
timestamp = {Wed, 15 Dec 2021 17:59:57 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/LiuAVS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/AnandBSAD05,
author = {Himyanshu Anand and
Jayanta Bhadra and
Alper Sen and
Magdy S. Abadir and
Kenneth G. Davis},
title = {Establishing latch correspondence for embedded circuits of PowerPC
microprocessors},
booktitle = {Tenth {IEEE} International High-Level Design Validation and Test Workshop
2005, Napa Valley, CA, USA, November 30 - December 2, 2005},
pages = {37--44},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/HLDVT.2005.1568811},
doi = {10.1109/HLDVT.2005.1568811},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/AnandBSAD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AliSVAD05,
author = {Moayad Fahim Ali and
Sean Safarpour and
Andreas G. Veneris and
Magdy S. Abadir and
Rolf Drechsler},
title = {Post-verification debugging of hierarchical designs},
booktitle = {2005 International Conference on Computer-Aided Design, {ICCAD} 2005,
San Jose, CA, USA, November 6-10, 2005},
pages = {871--876},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICCAD.2005.1560184},
doi = {10.1109/ICCAD.2005.1560184},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AliSVAD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/LeeLWA05,
author = {Benjamin N. Lee and
Hui Li and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Hazard-aware statistical timing simulation and its applications in
screening frequency-dependent defects},
booktitle = {Proceedings 2005 {IEEE} International Test Conference, {ITC} 2005,
Austin, TX, USA, November 8-10, 2005},
pages = {10},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/TEST.2005.1583965},
doi = {10.1109/TEST.2005.1583965},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/LeeLWA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/AliSVAD05,
author = {Moayad Fahim Ali and
Sean Safarpour and
Andreas G. Veneris and
Magdy S. Abadir and
Rolf Drechsler},
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Post-Verification Debugging of Hierarchical Designs},
booktitle = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
pages = {42--47},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTV.2005.18},
doi = {10.1109/MTV.2005.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/AliSVAD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/BhadraABT05,
author = {Jayanta Bhadra and
Magdy S. Abadir and
David Burgess and
Ekaterina Trofimova},
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Automatic Generation of High Performance Embedded Memory Models for
PowerPC Microprocessors},
booktitle = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
pages = {111--118},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTV.2005.9},
doi = {10.1109/MTV.2005.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/BhadraABT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/KahneA05,
author = {Brian Kahne and
Magdy S. Abadir},
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Retiming Verification Using Sequential Equivalence Checking},
booktitle = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
pages = {138--142},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/MTV.2005.22},
doi = {10.1109/MTV.2005.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/KahneA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/PradhanAV05,
author = {Dhiraj K. Pradhan and
Magdy S. Abadir and
Mauricio Varea},
title = {Recent Advances in Verification, Equivalence Checking and SAT-Solvers},
booktitle = {18th International Conference on {VLSI} Design {(VLSI} Design 2005),
with the 4th International Conference on Embedded Systems Design,
3-7 January 2005, Kolkata, India},
pages = {14},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ICVD.2005.146},
doi = {10.1109/ICVD.2005.146},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/PradhanAV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/LeeWA05,
author = {Benjamin N. Lee and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Reducing Pattern Delay Variations for Screening Frequency Dependent
Defects},
booktitle = {23rd {IEEE} {VLSI} Test Symposium {(VTS} 2005), 1-5 May 2005, Palm
Springs, CA, {USA}},
pages = {153--160},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/VTS.2005.70},
doi = {10.1109/VTS.2005.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/LeeWA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/mtv/2005,
editor = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Sixth International Workshop on Microprocessor Test and Verification
{(MTV} 2005), Common Challenges and Solutions, 3-4 November 2005,
Austin, Texas, {USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://ieeexplore.ieee.org/xpl/conhome/4022212/proceeding},
isbn = {0-7695-2627-6},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/mtv/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirW04,
author = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Guest Editors' Introduction: The Verification and Test of Complex
Digital ICs},
journal = {{IEEE} Des. Test Comput.},
volume = {21},
number = {2},
pages = {80--82},
year = {2004},
url = {https://doi.org/10.1109/MDT.2004.1277899},
doi = {10.1109/MDT.2004.1277899},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AbadirW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/MishraDKA04,
author = {Prabhat Mishra and
Nikil D. Dutt and
Narayanan Krishnamurthy and
Magdy S. Abadir},
title = {A Top-Down Methodology for Microprocessor Validation},
journal = {{IEEE} Des. Test Comput.},
volume = {21},
number = {2},
pages = {122--131},
year = {2004},
url = {https://doi.org/10.1109/MDT.2004.1277905},
doi = {10.1109/MDT.2004.1277905},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/MishraDKA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BhadraKA04,
author = {Jayanta Bhadra and
Narayanan Krishnamurthy and
Magdy S. Abadir},
title = {Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification
and Manufacturing Test Generation},
journal = {{IEEE} Des. Test Comput.},
volume = {21},
number = {6},
pages = {494--502},
year = {2004},
url = {https://doi.org/10.1109/MDT.2004.87},
doi = {10.1109/MDT.2004.87},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BhadraKA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MamidipakaKDA04,
author = {Mahesh Mamidipaka and
Kamal S. Khouri and
Nikil D. Dutt and
Magdy S. Abadir},
title = {{IDAP:} a tool for high-level power estimation of custom array structures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {23},
number = {9},
pages = {1361--1369},
year = {2004},
url = {https://doi.org/10.1109/TCAD.2004.833609},
doi = {10.1109/TCAD.2004.833609},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MamidipakaKDA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/codes/MamidipakaKDA04,
author = {Mahesh Mamidipaka and
Kamal S. Khouri and
Nikil D. Dutt and
Magdy S. Abadir},
editor = {Alex Orailoglu and
Pai H. Chou and
Petru Eles and
Axel Jantsch},
title = {Analytical models for leakage power estimation of memory array structures},
booktitle = {Proceedings of the 2nd {IEEE/ACM/IFIP} International Conference on
Hardware/Software Codesign and System Synthesis, {CODES+ISSS} 2004,
Stockholm, Sweden, September 8-10, 2004},
pages = {146--151},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/1016720.1016757},
doi = {10.1145/1016720.1016757},
timestamp = {Wed, 04 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/codes/MamidipakaKDA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangMCA04,
author = {Li{-}C. Wang and
T. M. Mak and
Kwang{-}Ting Cheng and
Magdy S. Abadir},
editor = {Sharad Malik and
Limor Fix and
Andrew B. Kahng},
title = {On path-based learning and its applications in delay test and diagnosis},
booktitle = {Proceedings of the 41th Design Automation Conference, {DAC} 2004,
San Diego, CA, USA, June 7-11, 2004},
pages = {492--497},
publisher = {{ACM}},
year = {2004},
url = {https://doi.org/10.1145/996566.996704},
doi = {10.1145/996566.996704},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WangMCA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/AliVSSDA04,
author = {Moayad Fahim Ali and
Andreas G. Veneris and
Alexander Smith and
Sean Safarpour and
Rolf Drechsler and
Magdy S. Abadir},
title = {Debugging sequential circuits using Boolean satisfiability},
booktitle = {2004 International Conference on Computer-Aided Design, {ICCAD} 2004,
San Jose, CA, USA, November 7-11, 2004},
pages = {204--209},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2004},
url = {https://doi.org/10.1109/ICCAD.2004.1382572},
doi = {10.1109/ICCAD.2004.1382572},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/AliVSSDA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/VenerisCAA04,
author = {Andreas G. Veneris and
Robert Chang and
Magdy S. Abadir and
Mandana Amiri},
title = {Fault equivalence and diagnostic test generation using {ATPG}},
booktitle = {Proceedings of the 2004 International Symposium on Circuits and Systems,
{ISCAS} 2004, Vancouver, BC, Canada, May 23-26, 2004},
pages = {221--224},
publisher = {{IEEE}},
year = {2004},
timestamp = {Wed, 16 Oct 2019 14:14:49 +0200},
biburl = {https://dblp.org/rec/conf/iscas/VenerisCAA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ZengAKVWA04,
author = {Jing Zeng and
Magdy S. Abadir and
A. Kolhatkar and
G. Vandling and
Li{-}C. Wang and
Jacob A. Abraham},
title = {On Correlating Structural Tests with Functional Tests for Speed Binning
of High Performance Design},
booktitle = {Proceedings 2004 International Test Conference {(ITC} 2004), October
26-28, 2004, Charlotte, NC, {USA}},
pages = {31--37},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/TEST.2004.1386934},
doi = {10.1109/TEST.2004.1386934},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/ZengAKVWA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/AliVSASDS04,
author = {Moayad Fahim Ali and
Andreas G. Veneris and
Sean Safarpour and
Magdy S. Abadir and
Rolf Drechsler and
Alexander Smith},
title = {Debugging Sequential Circuits Using Boolean Satisfiability},
booktitle = {Fifth International Workshop on Microprocessor Test and Verification
{(MTV} 2004), Common Challenges and Solutions, 08-10 September 2004,
Austin, Texas, {USA}},
pages = {44--49},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/MTV.2004.7},
doi = {10.1109/MTV.2004.7},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/AliVSASDS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/KhanTAL04,
author = {M. Moiz Khan and
Spyros Tragoudas and
Magdy S. Abadir and
Jiang Brandon Liu},
title = {Identification of Gates for Covering all Critical Paths},
booktitle = {Fifth International Workshop on Microprocessor Test and Verification
{(MTV} 2004), Common Challenges and Solutions, 08-10 September 2004,
Austin, Texas, {USA}},
pages = {92--96},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/MTV.2004.15},
doi = {10.1109/MTV.2004.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/KhanTAL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/ZengAVWKA04,
author = {Jing Zeng and
Magdy S. Abadir and
G. Vandling and
Li{-}C. Wang and
S. Karako and
Jacob A. Abraham},
title = {On Correlating Structural Tests with Functional Tests for Speed Binning
of High Performance Design},
booktitle = {Fifth International Workshop on Microprocessor Test and Verification
{(MTV} 2004), Common Challenges and Solutions, 08-10 September 2004,
Austin, Texas, {USA}},
pages = {103--109},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/MTV.2004.17},
doi = {10.1109/MTV.2004.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/ZengAVWKA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsid/KrishnamurthyBAA04,
author = {Narayanan Krishnamurthy and
Jayanta Bhadra and
Magdy S. Abadir and
Jacob A. Abraham},
title = {Towards The Complete Elimination of Gate/Switch Level Simulations},
booktitle = {17th International Conference on {VLSI} Design {(VLSI} Design 2004),
with the 3rd International Conference on Embedded Systems Design,
5-9 January 2004, Mumbai, India},
pages = {115},
publisher = {{IEEE} Computer Society},
year = {2004},
url = {https://doi.org/10.1109/ICVD.2004.1260913},
doi = {10.1109/ICVD.2004.1260913},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsid/KrishnamurthyBAA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dafes/WangFCAP03,
author = {Li{-}C. Wang and
Tao Feng and
Kwang{-}Ting (Tim) Cheng and
Magdy S. Abadir and
Manish Pandey},
title = {Enhanced Symbolic Simulation for Functional Verification of Embedded
Array Systems},
journal = {Des. Autom. Embed. Syst.},
volume = {8},
number = {2-3},
pages = {173--188},
year = {2003},
url = {https://doi.org/10.1023/B:DAEM.0000003961.86651.2b},
doi = {10.1023/B:DAEM.0000003961.86651.2B},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dafes/WangFCAP03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/fmsd/AbadirAHKM03,
author = {Magdy S. Abadir and
Ken Albin and
John Havlicek and
Narayanan Krishnamurthy and
Andrew K. Martin},
title = {Formal Verification Successes at Motorola},
journal = {Formal Methods Syst. Des.},
volume = {22},
number = {2},
pages = {117--123},
year = {2003},
url = {https://doi.org/10.1023/A:1022917321255},
doi = {10.1023/A:1022917321255},
timestamp = {Fri, 13 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/fmsd/AbadirAHKM03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/VenerisSA03,
author = {Andreas G. Veneris and
Alexander Smith and
Magdy S. Abadir},
editor = {Hiroto Yasuura},
title = {Logic verification based on diagnosis techniques},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {93--98},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119791},
doi = {10.1145/1119772.1119791},
timestamp = {Thu, 11 Mar 2021 17:04:51 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/VenerisSA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/FengWCPA03,
author = {Tao Feng and
Li{-}C. Wang and
Kwang{-}Ting Cheng and
Manish Pandey and
Magdy S. Abadir},
editor = {Hiroto Yasuura},
title = {Enhanced symbolic simulation for efficient verification of embedded
array systems},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {302--307},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119830},
doi = {10.1145/1119772.1119830},
timestamp = {Tue, 15 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/FengWCPA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/McDougallPJZZPA03,
author = {Tim McDougall and
Atanas N. Parashkevov and
Simon Jolly and
Juhong Zhu and
Jing Zeng and
Carol Pyron and
Magdy S. Abadir},
editor = {Hiroto Yasuura},
title = {An automated method for test model generation from switch level circuits},
booktitle = {Proceedings of the 2003 Asia and South Pacific Design Automation Conference,
{ASP-DAC} '03, Kitakyushu, Japan, January 21-24, 2003},
pages = {769--774},
publisher = {{ACM}},
year = {2003},
url = {https://doi.org/10.1145/1119772.1119943},
doi = {10.1145/1119772.1119943},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/aspdac/McDougallPJZZPA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ats/AbadirZPZ03,
author = {Magdy S. Abadir and
Jing Zeng and
Carol Pyron and
Juhong Zhu},
title = {Automated Test Model Generation from Switch Level Custom Circuits},
booktitle = {12th Asian Test Symposium {(ATS} 2003), 17-19 November 2003, Xian,
China},
pages = {184--189},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/ATS.2003.1250807},
doi = {10.1109/ATS.2003.1250807},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/ats/AbadirZPZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/KrsticWCLA03,
author = {Angela Krstic and
Li{-}C. Wang and
Kwang{-}Ting Cheng and
Jing{-}Jia Liou and
Magdy S. Abadir},
title = {Delay Defect Diagnosis Based Upon Statistical Timing Models - The
First Step},
booktitle = {2003 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2003), 3-7 March 2003, Munich, Germany},
pages = {10328--10335},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/DATE.2003.10007},
doi = {10.1109/DATE.2003.10007},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/KrsticWCLA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/MamidipakaKDA03,
author = {Mahesh Mamidipaka and
Kamal S. Khouri and
Nikil D. Dutt and
Magdy S. Abadir},
title = {{IDAP:} {A} Tool for High Level Power Estimation of Custom Array Structures},
booktitle = {2003 International Conference on Computer-Aided Design, {ICCAD} 2003,
San Jose, CA, USA, November 9-13, 2003},
pages = {113--119},
publisher = {{IEEE} Computer Society / {ACM}},
year = {2003},
url = {https://doi.ieeecomputersociety.org/10.1109/ICCAD.2003.1257602},
doi = {10.1109/ICCAD.2003.1257602},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/MamidipakaKDA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/WangKLCMWA03,
author = {Li{-}C. Wang and
Angela Krstic and
Leonard Lee and
Kwang{-}Ting Cheng and
M. Ray Mercer and
Thomas W. Williams and
Magdy S. Abadir},
title = {Using Logic Models To Predict The Detection Behavior Of Statistical
Timing Defects},
booktitle = {Proceedings 2003 International Test Conference {(ITC} 2003), Breaking
Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte,
NC, {USA}},
pages = {1041--1050},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/TEST.2003.1271092},
doi = {10.1109/TEST.2003.1271092},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/WangKLCMWA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/mtv/BhadraKA03,
author = {Jayanta Bhadra and
Narayanan Krishnamurthy and
Magdy S. Abadir},
title = {A Methodology for Validating Manufacturing Test Vector Suites for
Custom Designed Scan-Based Circuits},
booktitle = {Fourth International Workshop on Microprocessor Test and Verification,
Common Challenges and Solutions {(MTV} 2003), May 29-30, 2003, Hyatt
Town Lake Hotel, Austin, Texas, {USA}},
pages = {32--37},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/MTV.2003.1250260},
doi = {10.1109/MTV.2003.1250260},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/mtv/BhadraKA03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AbadirZ03,
author = {Magdy S. Abadir and
Juhong Zhu},
title = {Transition Test Generation using Replicate-and-Reduce Transform for
Scan-based Designs},
booktitle = {21st {IEEE} {VLSI} Test Symposium {(VTS} 2003), 27 April - 1 May 2003,
Napa Valley, CA, {USA}},
pages = {22--30},
publisher = {{IEEE} Computer Society},
year = {2003},
url = {https://doi.org/10.1109/VTEST.2003.1197629},
doi = {10.1109/VTEST.2003.1197629},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AbadirZ03.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VenerisA02,
author = {Andreas G. Veneris and
Magdy S. Abadir},
title = {Design rewiring using {ATPG}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {21},
number = {12},
pages = {1469--1479},
year = {2002},
url = {https://doi.org/10.1109/TCAD.2002.804388},
doi = {10.1109/TCAD.2002.804388},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VenerisA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/ZengAA02,
author = {Jing Zeng and
Magdy S. Abadir and
Jacob A. Abraham},
title = {False timing path identification using {ATPG} techniques and delay-based
information},
booktitle = {Proceedings of the 39th Design Automation Conference, {DAC} 2002,
New Orleans, LA, USA, June 10-14, 2002},
pages = {562--565},
publisher = {{ACM}},
year = {2002},
url = {https://doi.org/10.1145/513918.514060},
doi = {10.1145/513918.514060},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/ZengAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/VenerisLAA02,
author = {Andreas G. Veneris and
Jiang Brandon Liu and
Mandana Amiri and
Magdy S. Abadir},
title = {Incremental Diagnosis and Correction of Multiple Faults and Errors},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {716--721},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998378},
doi = {10.1109/DATE.2002.998378},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/VenerisLAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/GoorAC02,
author = {Ad J. van de Goor and
Magdy S. Abadir and
Alan Carlin},
title = {Minimal Test for Coupling Faults in Word-Oriented Memories},
booktitle = {2002 Design, Automation and Test in Europe Conference and Exposition
{(DATE} 2002), 4-8 March 2002, Paris, France},
pages = {944--948},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/DATE.2002.998413},
doi = {10.1109/DATE.2002.998413},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/GoorAC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/ParthasarathyIFWCA02,
author = {Ganapathy Parthasarathy and
Madhu K. Iyer and
Tao Feng and
Li{-}C. Wang and
Kwang{-}Ting Cheng and
Magdy S. Abadir},
title = {Combining {ATPG} and Symbolic Simulation for Efficient Validation
of Embedded Array Systems},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {203--212},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041762},
doi = {10.1109/TEST.2002.1041762},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/ParthasarathyIFWCA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/VenerisAA02,
author = {Andreas G. Veneris and
Magdy S. Abadir and
Mandana Amiri},
title = {Design Rewiring Using {ATPG}},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {223--232},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041764},
doi = {10.1109/TEST.2002.1041764},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/VenerisAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/WangAZ02,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Juhong Zhu},
title = {On Testing High-Performance Custom Circuits without Explicit Testing
of the Internal Faults},
booktitle = {Proceedings {IEEE} International Test Conference 2002, Baltimore,
MD, USA, October 7-10, 2002},
pages = {398--406},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/TEST.2002.1041785},
doi = {10.1109/TEST.2002.1041785},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/WangAZ02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/WangA02,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {Validation and Verification of Complex Digital Systems: {A} Practical
Perspective},
booktitle = {3rd Latin American Test Workshop, {LATW} 2002, Montevideo, Uruguay,
February 10-13, 2002},
pages = {1},
publisher = {{IEEE}},
year = {2002},
timestamp = {Wed, 26 Jul 2023 15:57:25 +0200},
biburl = {https://dblp.org/rec/conf/latw/WangA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/LiuVA02,
author = {Jiang Brandon Liu and
Andreas G. Veneris and
Magdy S. Abadir},
title = {Efficient and Exact Diagnosis of Multiple Stuck-At Faults},
booktitle = {3rd Latin American Test Workshop, {LATW} 2002, Montevideo, Uruguay,
February 10-13, 2002},
pages = {132--136},
publisher = {{IEEE}},
year = {2002},
timestamp = {Wed, 26 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/LiuVA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KrishnamurthyBAA02,
author = {Narayanan Krishnamurthy and
Jayanta Bhadra and
Magdy S. Abadir and
Jacob A. Abraham},
title = {Is State Mapping Essential for Equivalence Checking Custom Memories
in Scan-Based Designs?},
booktitle = {20th {IEEE} {VLSI} Test Symposium {(VTS} 2002), Without Testing It's
a Gamble, 28 April - 2 May 2002, Monterey, CA, {USA}},
pages = {275--280},
publisher = {{IEEE} Computer Society},
year = {2002},
url = {https://doi.org/10.1109/VTS.2002.1011152},
doi = {10.1109/VTS.2002.1011152},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KrishnamurthyBAA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/KrishnamurthyAMA01,
author = {Narayanan Krishnamurthy and
Magdy S. Abadir and
Andrew K. Martin and
Jacob A. Abraham},
title = {Design and Development Paradigm for Industrial Formal Verification
{CAD} Tools},
journal = {{IEEE} Des. Test Comput.},
volume = {18},
number = {4},
pages = {26--35},
year = {2001},
url = {https://doi.org/10.1109/54.936246},
doi = {10.1109/54.936246},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/KrishnamurthyAMA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/BedsoleRCA01,
author = {Jay Bedsole and
Rajesh Raina and
Al Crouch and
Magdy S. Abadir},
title = {Very Low Cost Testers: Opportunities and Challenges},
journal = {{IEEE} Des. Test Comput.},
volume = {18},
number = {5},
pages = {60--69},
year = {2001},
url = {https://doi.org/10.1109/54.953273},
doi = {10.1109/54.953273},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/BedsoleRCA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/aspdac/VenerisAT01,
author = {Andreas G. Veneris and
Magdy S. Abadir and
Ivor Ting},
editor = {Satoshi Goto},
title = {Design rewiring based on diagnosis techniques},
booktitle = {Proceedings of {ASP-DAC} 2001, Asia and South Pacific Design Automation
Conference 2001, January 30-February 2, 2001, Yokohama, Japan},
pages = {479--484},
publisher = {{ACM}},
year = {2001},
url = {https://doi.org/10.1145/370155.370516},
doi = {10.1145/370155.370516},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/aspdac/VenerisAT01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/charme/BhadraMAA01,
author = {Jayanta Bhadra and
Andrew K. Martin and
Jacob A. Abraham and
Magdy S. Abadir},
editor = {Tiziana Margaria and
Thomas F. Melham},
title = {Using Abstract Specifications to Verify PowerPC\({}^{\mbox{TM}}\)
Custom Memories by Symbolic Trajectory Evaluation},
booktitle = {Correct Hardware Design and Verification Methods, 11th {IFIP} {WG}
10.5 Advanced Research Working Conference, {CHARME} 2001, Livingston,
Scotland, UK, September 4-7, 2001, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {2144},
pages = {386--402},
publisher = {Springer},
year = {2001},
url = {https://doi.org/10.1007/3-540-44798-9\_30},
doi = {10.1007/3-540-44798-9\_30},
timestamp = {Sun, 02 Jun 2019 21:23:48 +0200},
biburl = {https://dblp.org/rec/conf/charme/BhadraMAA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/ZengABA01,
author = {Jing Zeng and
Magdy S. Abadir and
Jayanta Bhadra and
Jacob A. Abraham},
editor = {Wolfgang Nebel and
Ahmed Jerraya},
title = {Full chip false timing path identification: applications to the PowerPCTM
microprocessors},
booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe,
{DATE} 2001, Munich, Germany, March 12-16, 2001},
pages = {514--519},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/DATE.2001.915072},
doi = {10.1109/DATE.2001.915072},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/ZengABA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/hldvt/BhadraMAA01,
author = {Jayanta Bhadra and
Andrew K. Martin and
Jacob A. Abraham and
Magdy S. Abadir},
title = {A language formalism for verification of PowerPC\({}^{\mbox{TM}}\)
custom memories using compositions of abstract specifications},
booktitle = {Proceedings of the Sixth {IEEE} International High-Level Design Validation
and Test Workshop 2001, Monterey, California, USA, November 7-9, 2001},
pages = {134--141},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/HLDVT.2001.972820},
doi = {10.1109/HLDVT.2001.972820},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/hldvt/BhadraMAA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iolts/BoseRA01,
author = {Mrinal Bose and
Elizabeth M. Rudnick and
Magdy S. Abadir},
title = {Automatic Bias Generation Using Pipeline Instruction State Coverage
for Biased Random Instruction Generation},
booktitle = {7th {IEEE} International On-Line Testing Workshop {(IOLTW} 2001),
9-11 July 2001, Taormina, Italy},
pages = {65},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/OLT.2001.937821},
doi = {10.1109/OLT.2001.937821},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iolts/BoseRA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isqed/AbadirW01,
author = {Magdy S. Abadir and
Li{-}C. Wang},
title = {Verification and Validation of Complex Digital Systems: An Industrial
Perspective},
booktitle = {2nd International Symposium on Quality of Electronic Design {(ISQED}
2001), 26-28 March 2001, San Jose, CA, {USA}},
pages = {11--12},
publisher = {{IEEE} Computer Society},
year = {2001},
timestamp = {Wed, 16 Oct 2019 14:14:55 +0200},
biburl = {https://dblp.org/rec/conf/isqed/AbadirW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/TingVA01,
author = {Ivor Ting and
Andreas G. Veneris and
Magdy S. Abadir},
title = {{ATPG} Driven Logic Synthesis for Delay and Power Minimization},
booktitle = {2nd Latin American Test Workshop, {LATW} 2001, Cancun, Mexico, February
11-14, 2001},
pages = {96--99},
publisher = {{IEEE}},
year = {2001},
timestamp = {Tue, 25 Jul 2023 13:25:31 +0200},
biburl = {https://dblp.org/rec/conf/latw/TingVA01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AbadirZW01,
author = {Magdy S. Abadir and
Juhong Zhu and
Li{-}C. Wang},
title = {Analysis of Testing Methodologies for Custom Designs in PowerPCTM
Microprocessor},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {252--259},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.org/10.1109/VTS.2001.923447},
doi = {10.1109/VTS.2001.923447},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AbadirZW01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AbadirDNPV01,
author = {Magdy S. Abadir and
Scott Davidson and
Vijay Nagasamy and
Dhiraj K. Pradhan and
Prab Varma},
title = {{ATPG} for Design Errors-Is It Possible?},
booktitle = {19th {IEEE} {VLSI} Test Symposium {(VTS} 2001), Test and Diagnosis
in a Nanometric World, 29 April - 3 May 2001, Marina Del Rey, CA,
{USA}},
pages = {283--285},
publisher = {{IEEE} Computer Society},
year = {2001},
url = {https://doi.ieeecomputersociety.org/10.1109/VTS.2001.10019},
doi = {10.1109/VTS.2001.10019},
timestamp = {Tue, 23 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AbadirDNPV01.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirD00,
author = {Magdy S. Abadir and
Sumit Dasgupta},
title = {Guest Editors' Introduction: Microprocessor Test and Verification},
journal = {{IEEE} Des. Test Comput.},
volume = {17},
number = {4},
pages = {4--5},
year = {2000},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AbadirD00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/KrishnamurthyMAA00,
author = {Narayanan Krishnamurthy and
Andrew K. Martin and
Magdy S. Abadir and
Jacob A. Abraham},
title = {Validating PowerPC Microprocessor Custom Memories},
journal = {{IEEE} Des. Test Comput.},
volume = {17},
number = {4},
pages = {61--76},
year = {2000},
url = {https://doi.org/10.1109/54.895007},
doi = {10.1109/54.895007},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/KrishnamurthyMAA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/Abadir00,
author = {Magdy S. Abadir},
title = {Guest Editorial},
journal = {J. Electron. Test.},
volume = {16},
number = {1-2},
pages = {9--10},
year = {2000},
url = {https://doi.org/10.1023/A:1008307832432},
doi = {10.1023/A:1008307832432},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/Abadir00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WangA00,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {On Efficiently Producing Quality Tests for Custom Circuits in PowerPC\({}^{\mbox{TM}}\)
Microprocessors},
journal = {J. Electron. Test.},
volume = {16},
number = {1-2},
pages = {121--130},
year = {2000},
url = {https://doi.org/10.1023/A:1008353109659},
doi = {10.1023/A:1008353109659},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WangA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WuLWCA00,
author = {Wen Ching Wu and
Chung{-}Len Lee and
Ming Shae Wu and
Jwu E. Chen and
Magdy S. Abadir},
title = {Oscillation Ring Delay Test for High Performance Microprocessors},
journal = {J. Electron. Test.},
volume = {16},
number = {1-2},
pages = {147--155},
year = {2000},
url = {https://doi.org/10.1023/A:1008365428314},
doi = {10.1023/A:1008365428314},
timestamp = {Tue, 07 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/et/WuLWCA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cicc/BhadraAA00,
author = {Jayanta Bhadra and
Magdy S. Abadir and
Jacob A. Abraham},
title = {A quick and inexpensive method to identify false critical paths using
{ATPG} techniques: an experiment with a PowerPC\({}^{\mbox{TM}}\)
microprocessor},
booktitle = {Proceedings of the {IEEE} 2000 Custom Integrated Circuits Conference,
{CICC} 2000, Orlando, FL, USA, May 21-24, 2000},
pages = {71--74},
publisher = {{IEEE}},
year = {2000},
url = {https://doi.org/10.1109/CICC.2000.852620},
doi = {10.1109/CICC.2000.852620},
timestamp = {Mon, 10 Oct 2022 09:13:21 +0200},
biburl = {https://dblp.org/rec/conf/cicc/BhadraAA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/BatraAA00,
author = {Jayanta Batra and
Magdy S. Abadir and
Jacob A. Abraham},
title = {A Quick and Inexpensive Method to Identify False Critical Paths Using
{ATPG} Techniques: an Experiment with a PowerPC Microprocessor},
booktitle = {1st Latin American Test Workshop, {LATW} 2000, Rio de Janeiro, RJ,
Brazil, March 13-15, 2000},
pages = {72--76},
publisher = {{IEEE}},
year = {2000},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/BatraAA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/latw/VenerisAH00,
author = {Andreas G. Veneris and
Magdy S. Abadir and
Ibrahim N. Haji},
title = {Design Optimization Based on Diagnosis Techniques},
booktitle = {1st Latin American Test Workshop, {LATW} 2000, Rio de Janeiro, RJ,
Brazil, March 13-15, 2000},
pages = {244--249},
publisher = {{IEEE}},
year = {2000},
timestamp = {Tue, 25 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/latw/VenerisAH00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/KrishnamurthyMAA00,
author = {Narayanan Krishnamurthy and
Andrew K. Martin and
Magdy S. Abadir and
Jacob A. Abraham},
title = {Validation of PowerPC(tm) Custom Memories using Symbolic Simulation},
booktitle = {18th {IEEE} {VLSI} Test Symposium {(VTS} 2000), 30 April - 4 May 2000,
Montreal, Canada},
pages = {9--14},
publisher = {{IEEE} Computer Society},
year = {2000},
url = {https://doi.org/10.1109/VTEST.2000.843820},
doi = {10.1109/VTEST.2000.843820},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/KrishnamurthyMAA00.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WangA99,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {Experience in Validation of PowerPCTM Microprocessor Embedded Arrays},
journal = {J. Electron. Test.},
volume = {15},
number = {1-2},
pages = {191--205},
year = {1999},
url = {https://doi.org/10.1023/A:1008352805631},
doi = {10.1023/A:1008352805631},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WangA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/AbadirR99,
author = {Magdy S. Abadir and
Rajesh Raina},
title = {Design-for-test methodology for Motorola PowerPC microprocessors},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {810--819},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805812},
doi = {10.1109/TEST.1999.805812},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/AbadirR99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/WangA99,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {Tradeoff analysis for producing high quality tests for custom circuits
in PowerPC microprocessors},
booktitle = {Proceedings {IEEE} International Test Conference 1999, Atlantic City,
NJ, USA, 27-30 September 1999},
pages = {830--838},
publisher = {{IEEE} Computer Society},
year = {1999},
url = {https://doi.org/10.1109/TEST.1999.805814},
doi = {10.1109/TEST.1999.805814},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/WangA99.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/WangA98,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {Test Generation Based on High-Level Assertion Specification for PowerPCTM
Microprocessor Embedded Arrays},
journal = {J. Electron. Test.},
volume = {13},
number = {2},
pages = {121--135},
year = {1998},
url = {https://doi.org/10.1023/A:1008353704141},
doi = {10.1023/A:1008353704141},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/WangA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangAZ98,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Jing Zeng},
title = {On measuring the effectiveness of various design validation approaches
for PowerPC microprocessor embedded arrays},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {524--532},
year = {1998},
url = {https://doi.org/10.1145/296333.296335},
doi = {10.1145/296333.296335},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WangAZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/WangAK98,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Nari Krishnamurthy},
editor = {Basant R. Chawla and
Randal E. Bryant and
Jan M. Rabaey},
title = {Automatic Generation of Assertions for Formal Verification of PowerPC
Microprocessor Arrays Using Symbolic Trajectory Evaluation},
booktitle = {Proceedings of the 35th Conference on Design Automation, Moscone center,
San Francico, California, USA, June 15-19, 1998},
pages = {534--537},
publisher = {{ACM} Press},
year = {1998},
url = {https://doi.org/10.1145/277044.277188},
doi = {10.1145/277044.277188},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/WangAK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/WangAZ98,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Jing Zeng},
editor = {Patrick M. Dewilde and
Franz J. Rammig and
Gerry Musgrave},
title = {Measuring the Effectiveness of Various Design Validation Approaches
For PowerPC(TM) Microprocessor Arrays},
booktitle = {1998 Design, Automation and Test in Europe {(DATE} '98), February
23-26, 1998, Le Palais des Congr{\`{e}}s de Paris, Paris, France},
pages = {273--277},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/DATE.1998.655867},
doi = {10.1109/DATE.1998.655867},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/date/WangAZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/ChandraWA98,
author = {Arun Chandra and
Li{-}C. Wang and
Magdy S. Abadir},
title = {Practical Considerations in Formal Equivalence Checking of PowerPC(tm)
Microprocessors},
booktitle = {8th Great Lakes Symposium on {VLSI} {(GLS-VLSI} '98), 19-21 February
1998, Lafayette, LA, {USA}},
pages = {362--367},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/GLSV.1998.665314},
doi = {10.1109/GLSV.1998.665314},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/glvlsi/ChandraWA98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/WangAZ98,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Jing Zeng},
title = {On Logic and Transistor Level Design Error Detection of Various Validation
Approaches for PowerPC(tm) Microprocessor Arrays},
booktitle = {16th {IEEE} {VLSI} Test Symposium {(VTS} '98), 28 April - 1 May 1998,
Princeton, NJ, {USA}},
pages = {260--265},
publisher = {{IEEE} Computer Society},
year = {1998},
url = {https://doi.org/10.1109/VTEST.1998.670878},
doi = {10.1109/VTEST.1998.670878},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/WangAZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AmblerA97,
author = {Tony Ambler and
Magdy S. Abadir},
title = {Design and Test Economics-An Extra Dimension},
journal = {{IEEE} Des. Test Comput.},
volume = {14},
number = {3},
pages = {15--16},
year = {1997},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AmblerA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirK97,
author = {Magdy S. Abadir and
Rohit Kapur},
title = {Cost-Driven Ranking of Memory Elements for Partial Intrusion},
journal = {{IEEE} Des. Test Comput.},
volume = {14},
number = {3},
pages = {45--50},
year = {1997},
url = {https://doi.org/10.1109/54.605994},
doi = {10.1109/54.605994},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AbadirK97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/MurphyAS97,
author = {Cynthia F. Murphy and
Magdy S. Abadir and
Peter Sandborn},
title = {Economic Analysis of Test Process Flows for Multichip Modules Using
Known Good Die},
journal = {J. Electron. Test.},
volume = {10},
number = {1-2},
pages = {151--166},
year = {1997},
url = {https://doi.org/10.1023/A:1008239018655},
doi = {10.1023/A:1008239018655},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/MurphyAS97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/JainBAAF97,
author = {Jawahar Jain and
James R. Bitner and
Magdy S. Abadir and
Jacob A. Abraham and
Donald S. Fussell},
title = {Indexed BDDs: Algorithmic Advances in Techniques to Represent and
Verify Boolean Functions},
journal = {{IEEE} Trans. Computers},
volume = {46},
number = {11},
pages = {1230--1245},
year = {1997},
url = {https://doi.org/10.1109/12.644298},
doi = {10.1109/12.644298},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/JainBAAF97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/PandeyRBA97,
author = {Manish Pandey and
Richard Raimi and
Randal E. Bryant and
Magdy S. Abadir},
editor = {Ellen J. Yoffa and
Giovanni De Micheli and
Jan M. Rabaey},
title = {Formal Verification of Content Addressable Memories Using Symbolic
Trajectory Evaluation},
booktitle = {Proceedings of the 34st Conference on Design Automation, Anaheim,
California, USA, Anaheim Convention Center, June 9-13, 1997},
pages = {167--172},
publisher = {{ACM} Press},
year = {1997},
url = {https://doi.org/10.1145/266021.266056},
doi = {10.1145/266021.266056},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/PandeyRBA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/WangA97,
author = {Li{-}C. Wang and
Magdy S. Abadir},
title = {A New Validation Methodology Combining Test and Formal Verification
for PowerPC\({}^{\mbox{TM}}\) Microprocessor Arrays},
booktitle = {Proceedings {IEEE} International Test Conference 1997, Washington,
DC, USA, November 3-5, 1997},
pages = {954--963},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.org/10.1109/TEST.1997.639711},
doi = {10.1109/TEST.1997.639711},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/WangA97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vts/AbadirAHHNW97,
author = {Magdy S. Abadir and
Jacob A. Abraham and
Hong Hao and
C. Hunter and
Wayne M. Needham and
Ron G. Walther},
title = {Microprocessor Test and Validation: Any New Avenues?},
booktitle = {15th {IEEE} {VLSI} Test Symposium (VTS'97), April 27-May 1, 1997,
Monterey, California, {USA}},
pages = {458--464},
publisher = {{IEEE} Computer Society},
year = {1997},
url = {https://doi.ieeecomputersociety.org/10.1109/VTS.1997.10015},
doi = {10.1109/VTS.1997.10015},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vts/AbadirAHHNW97.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/GangulyAP96,
author = {Neeta Ganguly and
Magdy S. Abadir and
Manish Pandey},
title = {PowerPC\({}^{\mbox{TM}}\) Array Verification Methodology using Formal
Techniques},
booktitle = {Proceedings {IEEE} International Test Conference 1996, Test and Design
Validity, Washington, DC, USA, October 20-25, 1996},
pages = {857--864},
publisher = {{IEEE} Computer Society},
year = {1996},
url = {https://doi.org/10.1109/TEST.1996.557147},
doi = {10.1109/TEST.1996.557147},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/itc/GangulyAP96.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirPBSD94,
author = {Magdy S. Abadir and
Ashish R. Parikh and
Linda Bal and
Peter Sandborn and
Ken Drake},
title = {Analyzing Multichip Module Testing Strategies},
journal = {{IEEE} Des. Test Comput.},
volume = {11},
number = {1},
pages = {40--52},
year = {1994},
url = {https://doi.org/10.1109/54.262321},
doi = {10.1109/54.262321},
timestamp = {Sun, 17 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/dt/AbadirPBSD94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/AbadirA94,
author = {Magdy S. Abadir and
Tony Ambler},
title = {Introduction},
journal = {J. Electron. Test.},
volume = {5},
number = {2-3},
pages = {129--130},
year = {1994},
url = {https://doi.org/10.1007/BF00972073},
doi = {10.1007/BF00972073},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/AbadirA94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/AbadirPBSM94,
author = {Magdy S. Abadir and
Ashish Parikh and
Linda Bal and
Peter Sandborn and
Cynthia F. Murphy},
title = {High Level Test Economics Advisor (Hi-TEA)},
journal = {J. Electron. Test.},
volume = {5},
number = {2-3},
pages = {195--206},
year = {1994},
url = {https://doi.org/10.1007/BF00972079},
doi = {10.1007/BF00972079},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/AbadirPBSM94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/et/SandbornGDABP94,
author = {Peter Sandborn and
Rajarshi Ghosh and
Ken Drake and
Magdy S. Abadir and
Linda Bal and
Ashish Parikh},
title = {Multichip systems trade-off analysis tool},
journal = {J. Electron. Test.},
volume = {5},
number = {2-3},
pages = {207--218},
year = {1994},
url = {https://doi.org/10.1007/BF00972080},
doi = {10.1007/BF00972080},
timestamp = {Fri, 11 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/et/SandbornGDABP94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/ftcs/BitnerJAAF94,
author = {James R. Bitner and
Jawahar Jain and
Magdy S. Abadir and
Jacob A. Abraham and
Donald S. Fussell},
title = {Efficient Algorithmic Circuit Verification Using Indexed BDDs},
booktitle = {Digest of Papers: FTCS/24, The Twenty-Fourth Annual International
Symposium on Fault-Tolerant Computing, Austin, Texas, USA, June 15-17,
1994},
pages = {266--275},
publisher = {{IEEE} Computer Society},
year = {1994},
url = {https://doi.org/10.1109/FTCS.1994.315633},
doi = {10.1109/FTCS.1994.315633},
timestamp = {Wed, 16 Oct 2019 14:14:57 +0200},
biburl = {https://dblp.org/rec/conf/ftcs/BitnerJAAF94.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccd/VishakantaiahTAA93,
author = {Praveen Vishakantaiah and
Thomas Thomas and
Jacob A. Abraham and
Magdy S. Abadir},
title = {{AMBIANT:} Automatic Generation of Behavioral Modifications for Testability},
booktitle = {Proceedings 1993 International Conference on Computer Design: {VLSI}
in Computers {\&} Processors, {ICCD} '93, Cambridge, MA, USA,
October 3-6, 1993},
pages = {63--66},
publisher = {{IEEE} Computer Society},
year = {1993},
url = {https://doi.org/10.1109/ICCD.1993.393404},
doi = {10.1109/ICCD.1993.393404},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccd/VishakantaiahTAA93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/VishakantaiahAA92,
author = {Praveen Vishakantaiah and
Jacob A. Abraham and
Magdy S. Abadir},
editor = {Daniel G. Schweikert},
title = {Automatic Test Knowledge Extraction from {VHDL} {(ATKET)}},
booktitle = {Proceedings of the 29th Design Automation Conference, Anaheim, California,
USA, June 8-12, 1992},
pages = {273--278},
publisher = {{IEEE} Computer Society Press},
year = {1992},
url = {http://portal.acm.org/citation.cfm?id=113938.149442},
timestamp = {Thu, 16 Mar 2017 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/dac/VishakantaiahAA92.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/AbadirNDS91,
author = {Magdy S. Abadir and
Joe Newman and
Desmond D'Souza and
Steve Spencer},
title = {Partitioning Hierarchical Designs for Testability},
booktitle = {Proceedings {IEEE} International Test Conference 1991, Test: Faster,
Better, Sooner, Nashville, TN, USA, October 26-30, 1991},
pages = {174--183},
publisher = {{IEEE} Computer Society},
year = {1991},
url = {https://doi.org/10.1109/TEST.1991.519508},
doi = {10.1109/TEST.1991.519508},
timestamp = {Wed, 16 Oct 2019 14:14:52 +0200},
biburl = {https://dblp.org/rec/conf/itc/AbadirNDS91.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/eurodac/AbadirF90,
author = {Magdy S. Abadir and
Jack Ferguson},
editor = {Gordon Adshead and
Jochen A. G. Jess},
title = {An improved layout verification algorithm {(LAVA)}},
booktitle = {European Design Automation Conference, {EURO-DAC} 1990, Glasgow, Scotland,
UK, March 12-15, 1990},
pages = {391--395},
publisher = {{IEEE} Computer Society},
year = {1990},
url = {https://doi.org/10.1109/EDAC.1990.136679},
doi = {10.1109/EDAC.1990.136679},
timestamp = {Wed, 16 Oct 2019 14:14:54 +0200},
biburl = {https://dblp.org/rec/conf/eurodac/AbadirF90.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iccad/Abadir89,
author = {Magdy S. Abadir},
title = {{TIGER:} testability insertion guidance expert system},
booktitle = {1989 {IEEE} International Conference on Computer-Aided Design, {ICCAD}
1989, Santa Clara, CA, USA, November 5-9, 1989. Digest of Technical
Papers},
pages = {562--565},
publisher = {{IEEE} Computer Society},
year = {1989},
url = {https://doi.org/10.1109/ICCAD.1989.77013},
doi = {10.1109/ICCAD.1989.77013},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/iccad/Abadir89.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AbadirFK88,
author = {Magdy S. Abadir and
Jack Ferguson and
Tom E. Kirkland},
title = {Logic design verification via test generation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {7},
number = {1},
pages = {138--148},
year = {1988},
url = {https://doi.org/10.1109/43.3141},
doi = {10.1109/43.3141},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AbadirFK88.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AbadirB86,
author = {Magdy S. Abadir and
Melvin A. Breuer},
title = {Test Schedules for {VLSI} Circuits Having Built-In Test Hardware},
journal = {{IEEE} Trans. Computers},
volume = {35},
number = {4},
pages = {361--367},
year = {1986},
url = {https://doi.org/10.1109/TC.1986.1676771},
doi = {10.1109/TC.1986.1676771},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/AbadirB86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tc/AbadirR86,
author = {Magdy S. Abadir and
Hassan K. Reghbati},
title = {Functional Test Generation for Digital Circuits Described Using Binary
Decision Diagrams},
journal = {{IEEE} Trans. Computers},
volume = {35},
number = {4},
pages = {375--379},
year = {1986},
url = {https://doi.org/10.1109/TC.1986.1676774},
doi = {10.1109/TC.1986.1676774},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tc/AbadirR86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/AbadirB86,
author = {Magdy S. Abadir and
Melvin A. Breuer},
title = {Scan Path with Look Ahead Shifting {(SPLASH)}},
booktitle = {Proceedings International Test Conference 1986, Washington, D.C.,
USA, September 1986},
pages = {696--704},
publisher = {{IEEE} Computer Society},
year = {1986},
timestamp = {Tue, 22 Oct 2002 12:22:37 +0200},
biburl = {https://dblp.org/rec/conf/itc/AbadirB86.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/dt/AbadirB85,
author = {Magdy S. Abadir and
Melvin A. Breuer},
title = {A Knowledge-Based System for Designing Testable {VLSI} Chips},
journal = {{IEEE} Des. Test},
volume = {2},
number = {4},
pages = {56--68},
year = {1985},
url = {https://doi.org/10.1109/MDT.1985.294746},
doi = {10.1109/MDT.1985.294746},
timestamp = {Fri, 05 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/dt/AbadirB85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/itc/AbadirR85,
author = {Magdy S. Abadir and
Hassan K. Reghbati},
title = {Functional Test Generation for {LSI} Circuits Described by Binary
Decision Diagrams},
booktitle = {Proceedings International Test Conference 1985, Philadelphia, PA,
USA, November 1985},
pages = {483--492},
publisher = {{IEEE} Computer Society},
year = {1985},
timestamp = {Mon, 11 Nov 2002 15:59:32 +0100},
biburl = {https://dblp.org/rec/conf/itc/AbadirR85.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/dac/AbadirR84,
author = {Magdy S. Abadir and
Hassan K. Reghbati},
editor = {Patricia H. Lambert and
Hillel Ofek and
Lawrence A. O'Neill and
Pat O. Pistilli and
Paul Losleben and
J. Daniel Nash and
Dennis W. Shaklee and
Bryan T. Preas and
Harvey N. Lerman},
title = {Test generation for {LSI:} {A} case study},
booktitle = {Proceedings of the 21st Design Automation Conference, {DAC} '84, Albuquerque,
New Mexico, June 25-27, 1984},
pages = {180--195},
publisher = {{ACM/IEEE}},
year = {1984},
url = {http://dl.acm.org/citation.cfm?id=800794},
timestamp = {Thu, 12 Aug 2021 08:58:02 +0200},
biburl = {https://dblp.org/rec/conf/dac/AbadirR84.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/csur/AbadirR83,
author = {Magdy S. Abadir and
Hassan K. Reghbati},
title = {Functional Testing of Semiconductor Random Access Memories},
journal = {{ACM} Comput. Surv.},
volume = {15},
number = {3},
pages = {175--198},
year = {1983},
url = {https://doi.org/10.1145/356914.356916},
doi = {10.1145/356914.356916},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/csur/AbadirR83.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/micro/AbadirR83,
author = {Magdy S. Abadir and
Hassan K. Reghbati},
title = {{LSI} Testing Techniques},
journal = {{IEEE} Micro},
volume = {3},
number = {1},
pages = {34--51},
year = {1983},
url = {https://doi.org/10.1109/MM.1983.291070},
doi = {10.1109/MM.1983.291070},
timestamp = {Sat, 20 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/micro/AbadirR83.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-04-25 02:17 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
