Volume 9, Numbers 1-2, January 1995

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  Ingrid Verbauwhede, Jan M. Rabaey: Guest editor's introduction design environments for DSP. 5-6
• 
  José Luis Pino, Soonhoi Ha, Edward A. Lee, Joseph T. Buck: Software synthesis for DSP using ptolemy. 7-21
• 
  Pierre G. Paulin, Clifford Liem, Trevor C. May, Shailesh Sutarwala: DSP design tool requirements for embedded systems: A telecommunications industrial perspective. 23-47
• 
  Gert Goossens, Dirk Lanneer, Marc Pauwels, Francis Depuydt, Koen Schoofs, Augusli Kifli, Marco Cornero, Paolo Petroni, Francky Catthoor, Hugo De Man: Integration of medium-throughput signal processing algorithms on flexible instruction-set architectures. 49-65
• 
  Ingrid Verbauwhede, Jan M. Rabaey: Synthesis for real time systems: Solutions and challenges. 67-88
• 
  Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh, Albert van der Werf: PHIDEO: High-level synthesis for high throughput applications. 89-104
• 
  Phillip Duncan, Ken Kindsfater, Lynette Liu, Rajeev Jain: Strategies for design automation of high speed digital filters. 105-119
• 
  Keshab K. Parhi: High-level algorithm and architecture transformations for DSP synthesis. 121-143

Volume 9, Number 3, April 1995

• 
  Benjamin W. Wah: Guest editor's introduction. 151
• 
  Dominique Lavenier, Frédéric Raimbault, Patrice Frison: I/O and computation overlap on SIMD systolic arrays. 153-165
• 
  K'Andrea C. Bickerstaff, Michael J. Schulte, Earl E. Swartzlander Jr.: Parallel reduced area multipliers. 181-191
• 
  Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin: Digit pipelined arithmetic on fine-grain array processors. 193-209
• 
  Ramaswamy Govindarajan, Guang R. Gao: Rate-optimal schedule for multi-rate DSP computations. 211-232
• 
  Wee-Chiew Tan, Teresa H. Y. Meng: A low-power high performance polygon renderer for computer graphics. 233-255
• 
  Paolo Ienne, Marc A. Viredaz: GENES IV: A bit-serial processing element for a multi-model neural-network accelerator. 257-273

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