Volume 6, Number 1, June 1993
: Recent VLSI neural networks in Japan.
Volume 6, Number 2, August 1993
Gordon J. Brebner
: Configurable array logic circuits for computing network error detection codes.
: FIR filters with field-programmable gate arrays.
Barry S. Fagin
: Quantitative measurements of FPGA utility in special and general purpose processors.
: A gate-level reconfigurable Monte carlo processor.
: Using FPGAs to implement self-timed systems.
Volume 6, Number 3, December 1993
David M. Mandelbaum
: A method for calculation of the square root using combinatorial logic.
, Li Zhu
: An expandable column fft architecture using circuit switching networks.
: High level synthesis and generation FPGAs with the BEDROC system.