Volume 4,
Number 1,
March 1996
- Herbert Dawid, Gerhard Fettweis, Heinrich Meyr:
A CMOS IC for Gb/s Viterbi decoding: system design and VLSI implementation.
17-31
- Jeffrey C. Gealow, F. P. Herrmann, L. T. Hsu, Charles Sodini:
System design for pixel-parallel image processing.
32-41
- Mani B. Srivastava, Anantha P. Chandrakasan, Robert W. Brodersen:
Predictive system shutdown and other architectural techniques for energy efficient programmable computation.
42-55
- Jean Vuillemin, Patrice Bertin, Didier Roncin, Mark Shand, H. H. Touati, Philippe Boucard:
Programmable active memories: reconfigurable systems come of age.
56-69
- Daniel D. Gajski, Sanjiv Narayan, Loganath Ramachandran, Frank Vahid, Peter Fung:
System design methodologies: aiming at the 100 h design cycle.
70-82
- Pao-Ann Hsiung, Sao-Jie Chen, Tsung-Chien Hu, Shih-Chiang Wang:
PSM: an object-oriented synthesis approach to multiprocessor system design.
83-97
- Ti-Yen Yen, Wayne Wolf:
An efficient graph algorithm for FSM scheduling.
98-112
- Michael A. Riepe, João P. Marques Silva, Karem A. Sakallah, Richard B. Brown:
Ravel-XL: a hardware accelerator for assigned-delay compiled-code logic gate simulation.
113-129
- Michele Favalli, Cecilia Metra:
Sensing circuit for on-line detection of delay faults.
130-133
- Sebastian T. J. Fenn, Mohammed Benaissa, David Taylor:
Finite field inversion over the dual basis.
134-137
- D. J. Kinniment:
An evaluation of asynchronous addition.
137-140
- Chin-Long Wey:
Built-in self-test (BIST) design of high-speed carry-free dividers.
141-145
- V. Chandramouli, Erik Brunvand, Kent F. Smith:
Self-Timed Design in GaAs - Case Study of a High-Speed, Parallel Multiplier.
146
Volume 4,
Number 2,
June 1996
- Pradip K. Jha, Nikil D. Dutt:
High-level library mapping for arithmetic components.
157-169
- Raj S. Mitra, Partha S. Roop, Anupam Basu:
A new algorithm for implementation of design functions by available devices.
170-180
- Smita Bakshi, Daniel D. Gajski:
Component selection for high-performance pipelines.
181-194
- Teresa Serrano-Gotarredona, Bernabé Linares-Barranco:
A real-time clustering microchip neural engine.
195-209
- Qing Zhu, Wayne Wei-Ming Dai:
Planar clock routing for high performance chip and package co-design.
210-226
- Uwe Sparmann, Sudhakar M. Reddy:
On the effectiveness of residue code checking for parallel two's complement multipliers.
227-239
- Charles J. Alpert, Andrew B. Kahng:
A general framework for vertex orderings with applications to circuit clustering.
240-246
- Stephen B. Furber, P. Day:
Four-phase micropipeline latch control circuits.
247-253
- Srimat T. Chakradhar, Savita Banerjee, Rabindra K. Roy, Dhiraj K. Pradhan:
Synthesis of initializable asynchronous circuits.
254-263
- Stanislaw J. Piestrak:
Design of minimal-level PLA self-testing checkers for m-out-of-n codes.
264-272
- Samit Chaudhuri, Robert A. Walker:
Computing lower bounds on functional units before scheduling.
273-279
- Hong Shin Jun, Sun Young Hwang:
Automatic synthesis of dynamically configured pipelines supporting variable data initiation intervals.
279-285
- José Luis Neves, Eby G. Friedman:
Design methodology for synthesizing clock distribution networks exploiting nonzero localized clock skew.
286-291
- KiJong Lee, Kiyoung Choi:
Self-timed divider based on RSD number system.
292-295
- Mahesh A. Iyer, Miron Abramovici:
FIRE: a fault-independent combinational redundancy identification algorithm.
295-301
Volume 4,
Number 3,
September 1996
- K. W. Hsu, Cherrice Traver:
Guest Editorial Introduction to the Special Issue on the 1995 IEEE ASIC Conference.
305
- Ming-Dou Ker, Chung-Yu Wu, Tao Cheng, Hun-Hsien Chang:
Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC.
307-321
- Jan-Erik Eklund, C. Svensson, Anders Åström:
VLSI implementation of a focal plane image processor-a realization of the near-sensor image processing concept.
322-335
- Christopher A. Ryan, Joseph G. Tront:
FX: a fast approximate fault simulator for the switch-level using VHDL.
336-345
- Chanhee Oh, M. Ray Mercer:
Efficient logic-level timing analysis using constraint-guided critical path search.
346-355
- Tom Hameenanttila, Jo Dale Carothers, Donghui Li:
Fast coupled noise estimation for crosstalk avoidance in the MCG multichip module autorouter.
356-368
- Tan-Li Chou, Kaushik Roy:
Accurate power estimation of CMOS sequential circuits.
369-380
- Patrick Lysaght, Jon Stockwood:
A simulation tool for dynamically reconfigurable field programmable gate arrays.
381-390
- Ivan C. Kraljic, Georges Quénot, Bertrand Zavidovique:
From real-time emulation to ASIC integration for image processing applications.
391-404
- P. Plaza, L. A. Merayo, J. C. Diaz, J. L. Conesa:
A 2.5 Gb/s ATM switch chip set.
405-416
Volume 4,
Number 4,
December 1996
- A. Grzeszczak, Mrinal K. Mandal, Sethuraman Panchanathan:
VLSI implementation of discrete wavelet transform.
421-433
- Srilata Raman, Lalit M. Patnaik:
Performance-driven MCM partitioning through an adaptive genetic algorithm.
434-444
- Ravichandran Ramachandran, Shih-Lien Lu:
Efficient arithmetic using self-timing.
445-454
- Sang-Soo Lee, C. A. Laber:
A 3.5 in 230 Mbytes read-channel chip set for magneto-optical disk drives.
455-463
- Nader Mir-Fakhraei:
ATM switching architectures for wafer-scale integration.
464-471
- Mark B. Josephs, Jelio T. Yantchev:
CMOS design of the tree arbiter element.
472-476
- Qingjian Yu, Ernest S. Kuh, Tianxiong Xue:
Moment models of general transmission lines with application to interconnect analysis and optimization.
477-494
- Chi-Ying Tsui, José C. Monteiro, Massoud Pedram, Srinivas Devadas, Alvin M. Despain, Bill Lin:
Correction to "Power Estimation Methods for Sequential Logic Circuits" [Correspondence].
495
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