Volume 17, Number 1, January 2009

• 
  Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele: Wire Topology Optimization for Low Power CMOS. 1-11
• 
  Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta: Low-Power, High-Speed Transceivers for Network-on-Chip Communication. 12-21
• 
  Jianli Zhuo, Chaitali Chakrabarti, Kyungsoo Lee, Naehyuck Chang, Sarma B. K. Vrudhula: Maximizing the Lifetime of Embedded Systems Powered by Fuel Cell-Battery Hybrids. 22-32
• 
  Hamid Mahmoodi, Vishy Tirumalashetty, Matthew Cooke, Kaushik Roy: Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. 33-44
• 
  Irith Pomeranz, Sudhakar M. Reddy: Random Test Generation With Input Cube Avoidance. 45-54
• 
  Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja: Probabilistic Error Modeling for Nano-Domain Logic Circuits. 55-65
• 
  Zhiyi Yu, Bevan M. Baas: High Performance, Energy Efficiency, and Scalability With GALS Chip Multiprocessors. 66-79
• 
  Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt: Fast Configurable-Cache Tuning With a Unified Second-Level Cache. 80-91
• 
  Olivier Muller, Amer Baghdadi, Michel Jézéquel: From Parallelism Levels to a Multi-ASIP Architecture for Turbo Decoding. 92-102
• 
  Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor: Hierarchical Segmentation for Hardware Function Evaluation. 103-116
• 
  Hua Wang, Miguel Miranda, Wim Dehaene, Francky Catthoor: Design and Synthesis of Pareto Buffers Offering Large Range Runtime Energy/Delay Tradeoffs Via Combined Buffer Size and Supply Voltage Tuning. 117-127
• 
  Jie Gu, John Keane, Chris H. Kim: Fuer Chris H. Kim 2 Eintraege in Db, Chris H. Kim und Chris Kim. Identisch. Siehe EE-Links: Univ. of Minnesota. Modeling, Analysis, and Application of Leakage Induced Damping Effect for Power Supply Integrity. 128-136
• 
  Zhuo Feng, Peng Li: Performance-Oriented Parameter Dimension Reduction of VLSI Circuits. 137-150
• 
  Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Bingfeng Mei, Francky Catthoor, Diederik Verkest: Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures. 151-155
• 
  Barbara Cerato, Guido Masera, Emanuele Viterbo: Decoding the Golden Code: A VLSI Design. 156-160

Volume 17, Number 2, February 2009

• 
  Francesco Menichelli, Mauro Olivieri: Static Minimization of Total Energy Consumption in Memory Subsystem for Scratchpad-Based Systems-on-Chips. 161-171
• 
  Alfio Dario Grasso, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti: Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell. 172-180
• 
  Jonathan Rosenfeld, Eby G. Friedman: Quasi-Resonant Interconnects: A Low Power, Low Latency Design Methodology. 181-193
• 
  Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim: A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. 194-206
• 
  Juan A. Carrasco, Víctor Suñé: An ROBDD-Based Combinatorial Method for the Evaluation of Yield of Defect-Tolerant Systems-on-Chip. 207-220
• 
  Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis: The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators. 221-233
• 
  Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt: Exploiting Application Data-Parallelism on Dynamically Reconfigurable Architectures: Placement and Architectural Considerations. 234-247
• 
  S. F. Nielsen, Jens Sparsø, Jan Madsen: Behavioral Synthesis of Asynchronous Circuits Using Syntax Directed Translation as Backend. 248-261
• 
  Jin Sha, Zhongfeng Wang, Minglun Gao, Li Li: Multi-Gb/s LDPC Code Design and Implementation. 262-268
• 
  Suganth Paul, Nikhil Jayakumar, Sunil P. Khatri: A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. 269-277
• 
  Massimo Alioto, Gaetano Palumbo, Massimo Poli: Analysis and Modeling of Energy Consumption in RLC Tree Circuits. 278
• 
  Jie Gu, Ramesh Harjani, Chris H. Kim: Design and Implementation of Active Decoupling Capacitor Circuits for Power Supply Regulation in Digital ICs. 292-301
• 
  M. Mottaghi-Dastjerdi, Ali Afzali-Kusha, Massoud Pedram: BZ-FAD: A Low-Power Low-Area Multiplier Based on Shift-and-Add Architecture. 302-306
• 
  Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen: A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus. 306-311
• 
  Jose Carlos Garcia-Montesdeoca, Juan A. Montiel-Nelson, Saeid Nooshabadi: CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects. 311-316

Volume 17, Number 3, March 2009

• 
  Avinoam Kolodny, Li-Shiuan Peh: Special Section on International Symposium on Networks-on-Chip (NOCS). 317-318
• 
  Arnab Banerjee, Pascal T. Wolkotte, Robert D. Mullins, Simon W. Moore, Gerard J. M. Smit: An Energy and Performance Exploration of Network-on-Chip Architectures. 319-329
• 
  Ümit Y. Ogras, Radu Marculescu, Diana Marculescu, Eun Gu Jung: Design and Management of Voltage-Frequency Island Partitioned Networks-on-Chip. 330-341
• 
  Shan Yan, Bill Lin: Custom Networks-on-Chip Architectures With Multicast Routing. 342-355
• 
  Andres Mejia, Maurizio Palesi, Jose Flich, Shashi Kumar, Pedro López, Rickard Holsmark, José Duato: Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs. 356-369
• 
  Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee, Se-Joong Lee, Hoi-Jun Yoo: 81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC. 370-383
• 
  Sergio Tota, Mario R. Casu, Massimo Ruo Roch, Luca Macchiarulo, Maurizio Zamboni: A Case Study for NoC-Based Homogeneous MPSoC Architectures. 384-388
• 
  Paul Pop, Viacheslav Izosimov, Petru Eles, Zebo Peng: Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication. 389-402
• 
  Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama: Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. 403-416
• 
  Peng Zhang, Don Xie, Wen Gao: Variable-Bin-Rate CABAC Engine for H.264/AVC High Definition Real-Time Decoding. 417-426
• 
  Puru Choudhary, Diana Marculescu: Power Management of Voltage/Frequency Island-Based Systems Using Hardware-Based Methods. 427-438
• 
  Yang Liu, Tong Zhang, Jiang Hu: Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. 439-443
• 
  Yinan Kong, Braden Phillips: Fast Scaling in the Residue Number System. 443-447
• 
  Jian Sun, David Giuliano, Siddharth Devarajan, Jian-Qiang Lu, T. Paul Chow, Ronald J. Gutmann: Fully Monolithic Cellular Buck Converter Design for 3-D Power Delivery. 447-451

Volume 17, Number 4, April 2009

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  Niraj K. Jha: Editorial Appointments for the 2009-2010 Term. 453-469
• 
  Minsu Choi, Fabrizio Lombardi, Nohpill Park: Introduction to the Special Section on Nanocircuits and Systems. 470-472
• 
  Helia Naeimi, André DeHon: Fault Secure Encoder and Decoder for NanoMemory Applications. 473-486
• 
  Pinaki Mazumder, Sing-Rong Li, Idongesit E. Ebong: Tunneling-Based Cellular Nonlinear Network Architectures for Image Processing. 487-495
• 
  William Rhett Davis, Eun Chu Oh, Ambarish M. Sule, Paul D. Franzon: Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies. 496-506
• 
  Timothy J. Dysart, Peter M. Kogge: Analyzing the Inherent Reliability of Moderately Sized Magnetic and Electrostatic QCA Circuits Via Probabilistic Transfer Matrices. 507-516
• 
  Kyung Ki Kim, Yong-Bin Kim: A Novel Adaptive Design Methodology for Minimum Leakage Power Considering PVT Variations on Nanoscale VLSI Systems. 517-528
• 
  Jianwei Dai, Lei Wang, Faquir Jain: Analysis of Defect Tolerance in Molecular Crossbar Electronics. 529-540
• 
  Pramod Kumar Meher: On Efficient Implementation of Accumulation in Finite Field Over GF(2^m) and its Applications. 541-550
• 
  Chunjie Duan, Victor H. Cordero Calle, Sunil P. Khatri: Efficient On-Chip Crosstalk Avoidance CODEC Design. 551-560
• 
  Khaled Benkrid, Ying Liu, Abdsamad Benkrid: A Highly Parameterized and Efficient FPGA-Based Skeleton for Pairwise Biological Sequence Alignment. 561-570
• 
  Hai Qi Liu, Wang Ling Goh, Liter Siek, Wei Meng Lim, Yue Ping Zhang: A Low-Noise Multi-GHz CMOS Multiloop Ring Oscillator With Coarse and Fine Frequency Tuning. 571-577
• 
  Hassan Hassan, Mohab Anis, Mohamed I. Elmasry: Total Power Modeling in FPGAs Under Spatial Correlation. 578-582
• 
  Zhiqiang Cui, Zhongfeng Wang, Youjian Liu: High-Throughput Layered LDPC Decoding Architecture. 582-587
• 
  Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar: Wafer-Level Defect Screening for "Big-D/Small-A" Mixed-Signal SoCs. 587-592

Volume 17, Number 5, May 2009

• 
  Yoonjin Kim, Rabi N. Mahapatra, Ilhyun Park, Kiyoung Choi: Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. 593-603
• 
  Nitin Mohan, Manoj Sachdev: Low-Leakage Storage Cells for Ternary Content Addressable Memories. 604-612
• 
  Pei-Yu Huang, Yu-Min Lee: Full-Chip Thermal Analysis for the Early Design Stage via Generalized Integral Transforms. 613-626
• 
  Nathaniel J. Guilar, Travis Kleeburg, Albert Chen, Diego R. Yankelevich, Rajeevan Amirtharajah: Integrated Solar Energy Harvesting and Storage. 627-637
• 
  Sherif A. Tawfik, Volkan Kursun: Low Power and High Speed Multi Threshold Voltage Interface Circuits. 638-645
• 
  Changyun Zhu, Zhengyu Gu, Robert P. Dick, Li Shang, Robert G. Knobel: Characterization of Single-Electron Tunneling Transistors for Designing Low-Power Embedded Systems. 646-659
• 
  Felipe Klein, Roberto Leao, Guido Araujo, Luiz C. V. dos Santos, Rodolfo Azevedo: A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization. 660-673
• 
  Glenn Leary, Krishnan Srinivasan, Krishna Mehta, Karam S. Chatha: Design of Network-on-Chip Architectures With a Genetic Algorithm-Based Technique. 674-687
• 
  Min-Sheng Kao, Jen-Ming Wu, Chih-Hsing Lin, Fanta Chen, Ching-Te Chiu, Shawn S. H. Hsu: A 10-Gb/s CML I/O Circuit for Backplane Interconnection in 0.18- $\mu$ m CMOS Technology. 688-696
• 
  Loganathan Lingappan, Vijay Gangaram, Niraj K. Jha, Sreejit Chakravarty: Fast Enhancement of Validation Test Sets for Improving the Stuck-at Fault Coverage of RTL Circuits. 697-708
• 
  Abdsamad Benkrid, Khaled Benkrid: Novel Area-Efficient FPGA Architectures for FIR Filtering With Symmetric Signal Extension. 709-722
• 
  Che-Hua Shih, Juinn-Dar Huang, Jing-Yang Jou: Automatic Verification Stimulus Generation for Interface Protocols Modeled With Non-Deterministic Extended FSM. 723-727
• 
  Mirko Loghi, Paolo Azzoni, Massimo Poncino: Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching. 728-732

Volume 17, Number 6, June 2009

• 
  Feng Lu, Kwang-Ting Cheng: SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants. 733-746
• 
  Pramod Kumar Meher: Systolic and Non-Systolic Scalable Modular Designs of Finite Field Multipliers for Reed-Solomon Codec. 747-757
• 
  Meng-Fan Chang, Shu-Meng Yang: Analysis and Reduction of Supply Noise Fluctuations Induced by Embedded Via-Programming ROM. 758-769
• 
  Rupak Samanta, Ganesh Venkataraman, Jiang Hu: Clock Buffer Polarity Assignment for Power Noise Reduction. 770-780
• 
  Rajesh Garg, Nikhil Jayakumar, Sunil P. Khatri, Gwan S. Choi: Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. 781-792
• 
  Dayu Yang, Foster F. Dai, Weining Ni, Yin Shi, Richard C. Jaeger: Delta-Sigma Modulation for Direct Digital Frequency Synthesis. 793-802
• 
  Rajarajan Senguttuvan, Soumendu Bhattacharya, Abhijit Chatterjee: Efficient EVM Testing of Wireless OFDM Transceivers Using Null Carriers. 803-814
• 
  Ozgur Sinanoglu, Philip Schremmer: Scan Chain Hold-Time Violations: Can They be Tolerated? 815-826
• 
  Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment. 827-837
• 
  Yuan-Chun Lin, Youn-Long Lin: A Two-Result-per-Cycle Deblocking Filter Architecture for QFHD H.264/AVC Decoder. 838-843
• 
  DiaaEldin Khalil, Debjit Sinha, Hai Zhou, Yehea I. Ismail: A Timing-Dependent Power Estimation Framework Considering Coupling. 843-847
• 
  Hiroshi Sasaki, Masaaki Kondo, Hiroshi Nakamura: Energy-Efficient Dynamic Instruction Scheduling Logic Through Instruction Grouping. 848-852

Volume 17, Number 7, July 2009

• 
  Jordi Cortadella, Alexander Taubin: Guest Editorial: Special Section on Asynchronous Circuits and Systems. 853-854
• 
  Victor Khomenko: Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings. 855-868
• 
  Sobeeh Almukhaizim, Feng Shi, Eric Love, Yiorgos Makris: Soft-Error Tolerance and Mitigation in Asynchronous Burst-Mode Circuits. 869-882
• 
  Tsung-Te Liu, Louis P. Alarcón, Matthew D. Pierson, Jan M. Rabaey: Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic. 883-892
• 
  Yvain Thonnart, Edith Beigné, Alexandre Valentian, Pascal Vivet: Power Reduction of Asynchronous Logic Circuits Using Activity Detection. 893-906
• 
  Jeremie Hamon, Laurent Fesquet, Benoit Miscopein, Marc Renaudin: Constrained Asynchronous Ring Structures for Robust Digital Oscillators. 907-919
• 
  C. H. van Berkel, T. A. van Roermund: Scalable Multi-Input-Multi-Output Queues With Application to Variation-Tolerant Architectures. 920-923
• 
  William F. McLaughlin, Amitava Mitra, Steven M. Nowick: Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication. 923-928
• 
  Hwisung Jung, Massoud Pedram: Uncertainty-Aware Dynamic Power Management in Partially Observable Domains. 929-942
• 
  Yocheved Dotan, Nadav Levison, Roi Avidan, David J. Lilja: History Index of Correct Computation for Fault-Tolerant Nano-Computing. 943-952
• 
  Jie S. Hu, Shuai Wang, Sotirios G. Ziavras: On the Exploitation of Narrow-Width Values for Improving Register File Reliability. 953-963
• 
  Anna Richelli, Luigi Colalongo, Luca Mensi, Alessio Cacciatori, Zsolt Miklós Kovács-Vajna: Charge Pump Architectures Based on Dynamic Gate Control of the Pass-Transistors. 964-967
• 
  Pierantonio Merlino, Antonio Abramo: A Fully Pipelined Architecture for the LOCO-I Compression Algorithm. 967-971

Volume 17, Number 8, August 2009

• 
  Shuo Wang, Lei Wang: Exploiting Memory Soft Redundancy for Joint Improvement of Error Tolerance and Access Efficiency. 973-982
• 
  Philippe Clauss, Federico Javier Fernández, Diego Garbervetsky, Sven Verdoolaege: Symbolic Polynomial Maximization Over Convex Sets and Its Application to Memory Requirement Estimation. 983-996
• 
  Mian Dong, Lin Zhong: Nanowire Crossbar Logic and Standard Cell-Based Integration. 997-1007
• 
  Po-Ching Lin, Ying-Dar Lin, Yuan-Cheng Lai, Yi-Jun Zheng, Tsern-Huei Lee: Realizing a Sub-Linear Time String-Matching Algorithm With a Hardware Accelerator Using Bloom Filters. 1008-1020
• 
  Jong-Suk Lee, Dong Sam Ha: FleXilicon Architecture and Its VLSI Implementation. 1021-1033
• 
  Jun-hee Yoo, Sungjoo Yoo, Kiyoung Choi: Topology/Floorplan/Pipeline Co-Design of Cascaded Crossbar Bus. 1034-1047
• 
  Jason Helge Anderson, Farid N. Najm: Low-Power Programmable FPGA Routing Circuitry. 1048-1060
• 
  Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub: Passivity Compensation Algorithm for Method-of-Characteristics-Based Multiconductor Transmission Line Interconnect Macromodels. 1061-1072
• 
  Renato Fernandes Hentschke, Jagannathan Narasimhan, Marcelo O. Johann, Ricardo Reis: Maze Routing Steiner Trees With Delay Versus Wire Length Tradeoff. 1073-1086
• 
  Ren-Jie Lee, Hung-Ming Chen: Fast Flip-Chip Pin-Out Designation Respin for Package-Board Codesign. 1087-1098
• 
  Kendall Ananyi, Hamad Alrimeih, Daler N. Rakhmatov: Flexible Hardware Processor for Elliptic Curve Cryptography Over NIST Prime Fields. 1099-1112
• 
  Hwisung Jung, Andy Hwang, Massoud Pedram: Predictive-Flow-Queue-Based Energy Optimization for Gigabit Ethernet Controllers. 1113-1126
• 
  Bo Zhai, Sanjay Pant, Leyla Nazhandali, Scott Hanson, Javin Olson, Anna Reeves, Michael Minuth, Ryan Helfand, Todd M. Austin, Dennis Sylvester, David Blaauw: Energy-Efficient Subthreshold Processor Design. 1127-1137
• 
  Hui Shao, Chi-Ying Tsui, Wing-Hung Ki: The Design of a Micro Power Management System for Applications Using Photovoltaic Cells With the Maximum Output Power Control. 1138-1142
• 
  Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang: Design and Implementation of a Field Programmable CRC Circuit Architecture. 1142-1147
• 
  Mohammad M. Mansour: A Parallel Pruned Bit-Reversal Interleaver. 1147-1151
• 
  Po-Lin Chen, Jhih-Wei Lin, Tsin-Yuan Chang: IEEE Standard 1500 Compatible Delay Test Framework. 1152-1156
• 
  Milos Petrovic, Aleksandra Smiljanic, Milos Blagojevic: Design of the Switching Controller for the High-Capacity Non-Blocking Internet Router. 1157-1161
• 
  Daniele Rossi, José Manuel Cazeaux, Martin Omaña, Cecilia Metra, Abhijit Chatterjee: Accurate Linear Model for SET Critical Charge Estimation. 1161-1166
• 
  Youngmin Kim, Dusan Petranovic, Dennis Sylvester: Simple and Accurate Models for Capacitance Considering Floating Metal Fill Insertion. 1166-1170

Volume 17, Number 9, September 2009

• 
  Lei Zhang, Yinhe Han, Qiang Xu, Xiaowei Li, Huawei Li: On Topology Reconfiguration for Defect-Tolerant NoC-Based Homogeneous Manycore Systems. 1173-1186
• 
  Shah M. Jahinuzzaman, Mohammad Sharifkhani, Manoj Sachdev: An Analytical Model for Soft Error Critical Charge of Nanometric SRAMs. 1187-1195
• 
  Peiyi Zhao, Jason McNeely, Pradeep Kumar Golconda, Soujanya Venigalla, Nan Wang, Magdy A. Bayoumi, Weidong Kuang, Luke Downey: Low-Power Clocked-Pseudo-NMOS Flip-Flop for Level Conversion in Dual Supply Systems. 1196-1202
• 
  Jie Gu, Hanyong Eom, John Keane, Chris H. Kim: Sleep Transistor Sizing and Adaptive Control for Supply Noise Minimization Considering Resonance. 1203-1211
• 
  Po-Chun Hsieh, Jing-Siang Jhuang, Pei-Yun Tsai, Tzi-Dar Chiueh: A Low-Power Delay Buffer Using Gated Driver Tree. 1212-1219
• 
  Saumya Chandra, Kanishka Lahiri, Anand Raghunathan, Sujit Dey: Variation-Tolerant Dynamic Power Management at the System-Level. 1220-1232
• 
  Magnus Själander, Per Larsson-Edefors: Multiplication Acceleration Through Twin Precision. 1233-1246
• 
  Julio A. de Oliveira Filho, Stephan Masekowsky, Thomas Schweizer, Wolfgang Rosenstiel: CGADL: An Architecture Description Language for Coarse-Grained Reconfigurable Arrays. 1247-1259
• 
  Jeong-Ho Woo, Ju-Ho Sohn, Hyejung Kim, Hoi-Jun Yoo: A 152-mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG. 1260-1266
• 
  Liang Zhang, J. M. Wilson, Rizwan Bashirullah, Lei Luo, Jian Xu, Paul D. Franzon: A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling. 1267-1274
• 
  Pei-Yin Chen, Chih-Yuan Lien, Chi-Pin Lu: VLSI Implementation of an Edge-Oriented Image Scaling Processor. 1275-1284
• 
  Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa: A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs. 1285-1296
• 
  Ming-Bo Lin, Yung-Yi Chang: A New Architecture of a Two-Stage Lossless Data Compression and Decompression Algorithm. 1297-1303
• 
  Florin Balasa, Hongwei Zhu, Ilie I. Luican: Signal Assignment to Hierarchical Memory Organizations for Embedded Multidimensional Signal Processing Systems. 1304-1317
• 
  Jason Cong, Karthik Gururaj, Guoling Han, Wei Jiang: Synthesis Algorithm for Application-Specific Homogeneous Processor Networks. 1318-1329
• 
  De-Shiuan Chiou, Shih-Hsin Chen, Shih-Chieh Chang: Sleep Transistor Sizing for Leakage Power Minimization Considering Charge Balancing. 1330-1334
• 
  Bradley R. Quinton, Steven J. E. Wilton: Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. 1334-1339
• 
  Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos: Design of Parasitic and Process-Variation Aware Nano-CMOS RF Circuits: A VCO Case Study. 1339-1342
• 
  Kyoungwoo Lee, Aviral Shrivastava, Ilya Issenin, Nikil D. Dutt, Nalini Venkatasubramanian: Partially Protected Caches to Reduce Failures Due to Soft Errors in Multimedia Applications. 1343-1347
• 
  Xianwu Xing, Ching-Chuen Jong: Multivoltage Multifrequency Low-Energy Synthesis for Functionally Pipelined Datapath. 1348-1352
• 
  Jason Thong, Nicola Nicolici: Time-Efficient Single Constant Multiplication Based on Overlapping Digit Patterns. 1353-1357
• 
  Sherief Reda, Gregory Smith, Larry Smith: Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. 1357-1362
• 
  Chenjie Yu, Peter Petrov: Low-Power Snoop Architecture for Synchronized Producer-Consumer Embedded Multiprocessing. 1362-1366

Volume 17, Number 10, October 2009

• 
  Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Seok-Hoon Kim, Lee-Sup Kim: A 186-Mvertices/s 161-mW Floating-Point Vertex Processor With Optimized Datapath and Vertex Caches. 1369-1382
• 
  Amir Zjajo, José Pineda de Gyvez: Analog Automatic Test Pattern Generation for Quasi-Static Structural Test. 1383-1391
• 
  Ozgur Sinanoglu, Sobeeh Almukhaizim: X-Align: Improving the Scan Cell Observability of Response Compactors. 1392-1404
• 
  Emre Salman, Renatas Jakushokas, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Methodology for Efficient Substrate Noise Analysis in Large-Scale Mixed-Signal Circuits. 1405-1418
• 
  Aydin O. Balkan, Gang Qu, Uzi Vishkin: Mesh-of-Trees and Alternative Interconnection Networks for Single-Chip Parallelism. 1419-1432
• 
  Victor Dumitriu, Gul N. Khan: Throughput-Oriented NoC Topology Generation and Analysis for High Performance SoCs. 1433-1446
• 
  Maryam Ashouei, Abhijit Chatterjee: Checksum-Based Probabilistic Transient-Error Compensation for Linear Digital Systems. 1447-1460
• 
  Moo-young Kim, Dongsuk Shin, Hyunsoo Chae, Chulwoo Kim: A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time. 1461-1469
• 
  Min Chen, Wei Zhao, Frank Liu, Yu Cao: Finite-Point-Based Transistor Model: A New Approach to Fast Circuit Simulation. 1470-1480
• 
  Mingjie Lin, Abbas El Gamal: A Low-Power Field-Programmable Gate Array Routing Fabric. 1481-1494
• 
  Duo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala: Architecture-Level Thermal Characterization for Multicore Microprocessors. 1495-1507
• 
  David Bol, Renaud Ambroise, Denis Flandre, Jean-Didier Legat: Interests and Limitations of Technology Scaling for Subthreshold Logic. 1508-1519
• 
  Sebastian Herbert, Diana Marculescu: Mitigating the Impact of Variability on Chip-Multiprocessor Power and Performance. 1520-1533
• 
  Tezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. 1534-1545
• 
  Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi: A High-Speed Word Level Finite Field Multiplier in BBF_2^m Using Redundant Representation. 1546-1550
• 
  G. Razavipour, Ali Afzali-Kusha, Massoud Pedram: Design and Analysis of Two Low-Power SRAM Cell Structures. 1551-1555
• 
  Alexandre Ney, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian: Analysis of Resistive-Open Defects in SRAM Sense Amplifiers. 1556-1559
• 
  Emre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin: Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling. 1559-1564

Volume 17, Number 11, November 2009

• 
  Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Yunheung Paek: A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures. 1565-1578
• 
  Cheng Jia, Linda Milor: A DLL Design for Testing I/O Setup and Hold Times. 1579-1592
• 
  Zhengtao Yu, Xun Liu: Implementing Multiphase Resonant Clocking on a Finite-Impulse Response Filter. 1593-1601
• 
  Jiangli Zhu, Xinmiao Zhang, Zhongfeng Wang: Backward Interpolation Architecture for Algebraic Soft-Decision Reed-Solomon Decoding. 1602-1615
• 
  Ming-Fu Sun, Ta-Yang Juan, Kan-Si Lin, Terng-Yin Hsu: Adaptive Frequency-Domain Channel Estimator in 4 , times , 4 MIMO-OFDM Modems. 1616-1625
• 
  Amlan Ganguly, Partha Pratim Pande, Benjamin Belzer: Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects. 1626-1639
• 
  Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: A Framework for Power-Gating Functional Units in Embedded Microprocessors. 1640-1649
• 
  Simone Corbetta, Massimo Morandi, Marco Novati, Marco D. Santambrogio, Donatella Sciuto, Paola Spoletini: Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration. 1650-1654
• 
  Davide Appello, Paolo Bernardi, Michelangelo Grosso, Ernesto Sánchez, Matteo Sonza Reorda: Effective Diagnostic Pattern Generation Strategy for Transition-Delay Faults in Full-Scan SOCs. 1654-1659
• 
  Lih-Yih Chiou, Shien-Chun Luo: Energy-Efficient Dual-Edge-Triggered Level Converting Flip Flops With Symmetry in Setup Times and Insensitivity to Output Parasitics. 1659-1663

Volume 17, Number 12, December 2009

• 
  Woosik Jeong, Ilkwon Kang, Kyowon Jin, Sungho Kang: A Fast Built-in Redundancy Analysis for Memories With Optimal Repair Rate Using a Line-Based Search Tree. 1665-1678
• 
  Keith A. Bowman, Alaa R. Alameldeen, Srikanth T. Srinivasan, Chris Wilkerson: Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors. 1679-1690
• 
  Byeong Kil Lee, Lizy K. John: Hardware Acceleration for Media/Transaction Applications in Network Processors. 1691-1697
• 
  Shu-Yu Jiang, Kuo-Hsing Cheng, Pei-Yi Jian: A 2.5-GHz Built-in Jitter Measurement System in a Serial-Link Transceiver. 1698-1708
• 
  Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton: Floating-Point FPGA: Architecture and Modeling. 1709-1718
• 
  Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini: Improved Pervasive Sensing With RFID: An Ultra-Low Power Baseband Processor for UHF Tags. 1719-1729
• 
  Sudarshan Bahukudumbi, Krishnendu Chakrabarty: Power Management Using Test-Pattern Ordering for Wafer-Level Test During Burn-In. 1730-1741
• 
  Qingjin Du, Jingcheng Zhuang, Tad A. Kwasniewski: A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. 1742-1748
• 
  Yiran Chen, Hai Li, Kaushik Roy, Cheng-Kok Koh: Gated Decap: Gate Leakage Control of On-Chip Decoupling Capacitors in Scaled Technologies. 1749-1752

last updated on Tue May 21 03:35:11 2013 by the dblp team
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