Volume 14, Number 1, January 2006
Volume 14, Number 2, February 2006
Orlando J. Hernandez
: A high-performance VLSI architecture for the histogram peak-climbing data clustering algorithm.
, Gang Qu
: A combined gate replacement and input vector control approach for leakage current reduction.
Volume 14, Number 3, March 2006
, Yong-Bin Kim
, T. Doyle
: A high-efficiency fully digital synchronous buck converter power delivery system based on a finite-state machine.
Volume 14, Number 4, April 2006
Volume 14, Number 5, May 2006
, Massoud Pedram
: An Analytical Model for Predicting the Remaining Battery Capacity of Lithium-Ion Batteries.
, Jonathan Rose
: Using Bus-Based Connections to Improve Field-Programmable Gate-Array Density for Implementing Datapath Circuits.
, J.-C. Yeo
, A.-Y. Wu
: Multi-Symbol-Sliced Dynamically Reconfigurable Reed-Solomon Decoder Design Based on Unified Finite-Field Processing Element.
, K. Roy
: A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies.
Volume 14, Number 6, June 2006
Volume 14, Number 7, July 2006
Pierre G. Paulin
, Chuck Pilkington
, Michel Langevin
, Essaid Bensoudane
, Damien Lyonnard
, Olivier Benny
, Bruno Lavigueur
, David Lo
, Giovanni Beltrame
, Vincent Gagné
, Gabriela Nicolescu
: Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia.
, Wei Qin
, Sharad Malik
: Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation.
, Gang Quan
: Energy minimization for real-time systems with (m, k)-guarantee.
Catherine H. Gebotys
: A table masking countermeasure for low-energy secure embedded systems.
: DSM interconnects: importance of inductance effects and corresponding range of length.
Volume 14, Number 8, August 2006
Volume 14, Number 9, September 2006
, Jun Ma
: High-Speed Interpolation Architecture for Soft-Decision Decoding of Reed-Solomon Codes.
, Amine Bermak
: An Efficient Digital VLSI Implementation of Gaussian Mixture Models-Based Classifier.
K. N. Vikram
, V. Vasudevan
: Mapping Data-Parallel Tasks Onto Partially Reconfigurable Hybrid Processor Architectures.
Volume 14, Number 10, October 2006
, C.-H. Chen
: Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation.
: Reduced Complexity Interpolation Architecture for Soft-Decision Reed–Solomon Decoding.
Volume 14, Number 11, November 2006
, Adit D. Singh
: A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI).
Volume 14, Number 12, December 2006
Mark M. Budnik
, Kaushik Roy
: A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.