Volume 13,
Number 1,
January 2005
- Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff:
The CSI multimedia architecture.
1-13
- Emil Talpes, Diana Marculescu:
Execution cache-based microarchitecture for power-efficient superscalar processors.
14-26
- Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies.
27-38
- George A. Constantinides, Peter Y. K. Cheung, Wayne Luk:
Optimum and heuristic synthesis of multiple word-length architectures.
39-57
- Dongming Peng, Mi Lu:
Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations.
58-74
- Yiran Chen, Kaushik Roy, Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
75-85
- Lok-Kee Ting, Roger Woods, C. F. N. Cowan:
Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers.
86-95
- Herman Schmit, Vikas Chandra:
Layout techniques for FPGA switch blocks.
96-105
- Dongming Peng, Mi Lu:
On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms.
106-125
- Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli:
A robust self-calibrating transmission scheme for on-chip networks.
126-139
- Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici:
Synchronization overhead in SOC compressed test.
140-152
- Ahmad A. Hiasat:
VLSI implementation of new arithmetic residue to binary decoders.
153-158
- Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu:
Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.
158-162
Volume 13,
Number 2,
February 2005
- Brian Moore, Martin Margala, Christopher J. Backhouse:
Design of wireless on-wafer submicron characterization system.
169-180
- Marko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen:
A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter.
181-190
- Francesco Centurelli, A. Golfarelli, J. Guinea, L. Masini, D. Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti:
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
191-200
- Liming Xiu, Zhihong You:
A "Flying-Adder" frequency synthesis architecture of reducing VCO stages.
201-210
- Vijay Raghunathan, Cristiano Pereira, Mani B. Srivastava, Rajesh K. Gupta:
Energy-aware wireless systems with adaptive power-fidelity tradeoffs.
211-225
- P. Chowdhury, C. Chakrabarti:
Static task-scheduling algorithms for battery-powered DVS systems.
226-237
- W. W. Bachmann, Sorin A. Huss:
Efficient algorithms for multilevel power estimation of VLSI circuits.
238-254
- Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang:
A micropower low-voltage multiplier with reduced spurious switching.
255-265
- Neil Burgess:
Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder.
266-277
- Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge:
A transaction-based unified architecture for simulation and emulation.
278-287
- Jai-Ming Lin, Yao-Wen Chang:
TCG: A transitive closure graph-based representation for general floorplans.
288-292
Volume 13,
Number 3,
March 2005
- Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry:
POMR: a power-aware interconnect optimization methodology.
297-307
- Vinita V. Deodhar, Jeffrey A. Davis:
Optimization of throughput performance for low-power VLSI interconnects.
308-318
- Jinjun Xiong, Lei He:
Extended global routing with RLC crosstalk constraints.
319-329
- Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez:
Accurate and efficient simulation of synchronous digital switching noise in systems on a chip.
330-338
- T. Chen:
On the impact of on-chip inductance on signal nets under the influence of power grid noise.
339-348
- Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
349-357
- John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, Lisa G. McIlrath:
Design of a 3-D fully depleted SOI computational RAM.
358-369
- Sanghyeon Baeg, Sung Soo Chung:
Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis.
370-383
- Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy:
Low-power scan design using first-level supply gating.
384-395
- Magdy A. El-Moursy, Eby G. Friedman:
Shielding effect of on-chip interconnect inductance.
396-400
- Mohamed A. Elgamel, Ashok Kumar, Magdy A. Bayoumi:
Efficient shield insertion for inductive noise reduction in nanometer technologies.
401-405
- Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu:
A temperature-insensitive self-recharging circuitry used in DRAMs.
405-408
Volume 13,
Number 4,
April 2005
- Xinmiao Zhang, Keshab K. Parhi:
Fast factorization architecture in soft-decision Reed-Solomon decoding.
413-426
- Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar:
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders.
427-438
- Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
439-447
- Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel:
Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication.
448-461
- M. E. Litvin, S. Mourad:
Self-reset logic for fast arithmetic applications.
462-475
- Chang Hoon Kim, Chun Pyo Hong, Soonhak Kwon:
A digit-serial multiplier for finite field GF(2/sup m/).
476-483
- Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson:
A reconfigurable, power-efficient adaptive Viterbi decoder.
484-488
- Keshab K. Parhi:
Design of multigigabit multiplexer-loop-based decision feedback equalizers.
489-493
- M. Tiwari, Yuming Zhu, Chaitali Chakrabarti:
Memory sub-banking scheme for high throughput MAP-based SISO decoders.
494-498
- Sri Parameswaran, Jörg Henkel:
Instruction code mapping for performance increase and energy reduction in embedded computer systems.
498-502
- Swarup Bhunia, Kaushik Roy:
A novel wavelet transform-based transient current analysis for fault detection and localization.
503-507
Volume 13,
Number 5,
May 2005
- Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha:
Memory binding for performance optimization of control-flow intensive behavioral descriptions.
513-524
- Nattawut Thepayasuwan, Alex Doboli:
Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed.
525-538
- Sungchan Kim, Chaeseok Im, Soonhoi Ha:
Schedule-aware performance estimation of communication architecture for efficient design space exploration.
539-552
- Fred Ma, John P. Knight, Calvin Plett:
Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms.
553-563
- Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power.
564-576
- Nikola Nedovic, Vojin G. Oklobdzija:
Dual-edge triggered storage elements and clocking strategy for low-power systems.
577-590
- Emil Talpes, Diana Marculescu:
Toward a multiple clock/voltage island design style for power-aware processors.
591-603
- Ted H. Szymanski, Honglin Wu, Amir Gourgy:
Power complexity of multiplexer-based optoelectronic crossbar switches.
604-617
- Amin Q. Safarian, Ahmad Yazdi, Payam Heydari:
Design and analysis of an ultrawide-band distributed CMOS mixer.
618-629
- Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti:
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
630-638
Volume 13,
Number 6,
June 2005
- Atanu Chattopadhyay, Zeljko Zilic:
GALDS: a complete framework for designing multiclock ASICs and SoCs.
641-654
- Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for system-on-chip networks: a unified framework.
655-667
- Yangdong Deng, W. P. Maly:
2.5-dimensional VLSI system integration.
668-677
- Qiang Xu, Nicola Nicolici:
Wrapper design for multifrequency IP cores.
678-685
- Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang:
A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits.
686-695
- Haris Lekatsas, Jörg Henkel, Wayne Wolf:
Approximate arithmetic coding for bus transition reduction in low power designs.
696-707
- James Chien-Mo Li:
Diagnosis of single stuck-at faults and multiple timing faults in scan chains.
708-718
- Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty:
Nine-coded compression technique for testing embedded cores in SoCs.
719-731
- Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang:
Design-for-testability and fault-tolerant techniques for FFT processors.
732-741
- Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu:
A built-in self-repair design for RAMs with 2-D redundancy.
742-745
- Anh Dinh, Xiao Hu:
A hardware-efficient technique to implement a trellis code modulation decoder.
745-750
- Rishi Chaturvedi, Jiang Hu:
An efficient merging scheme for prescribed skew clock routing.
750-754
- Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy:
Comparison of high-performance VLSI adders in the energy-delay space.
754-758
- S. W. Oldridge, Steven J. E. Wilton:
A novel FPGA architecture supporting wide, shallow memories.
758-762
- Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava:
Simultaneous V/sub t/ selection and assignment for leakage optimization.
762-765
- Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
Synthesis of Fredkin-Toffoli reversible networks.
765-769
Volume 13,
Number 7,
July 2005
- Gopalakrishnan Lakshminarayanan, B. Venkataramani:
Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks.
783-793
- Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi:
Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA.
794-807
- Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design.
808-818
- Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla:
Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data.
819-832
- P. Gui, Fouad E. Kiamilev, X. Q. Wang, M. J. MacFadden, X. L. Wang, N. Waite, M. W. Haney, C. Kuznia:
A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC.
833-842
- Ajit Sharma, P. Birrer, S. K. Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram:
Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver.
843-851
- Christopher S. Taillefer, Gordon W. Roberts:
Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time.
852-860
- Y.-S. Kwon, C.-M. Kyung:
ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture.
861-864
- H. Ando, Nestoras Tzartzanis, William W. Walker:
A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing.
865-868
- S. Hua, G. Qu:
Voltage Setup Problem for Embedded Systems With Multiple Voltages.
869-872
- Xinmiao Zhang, Keshab K. Parhi:
High-Speed Architectures for Parallel Long BCH Encoders.
872-877
- Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi:
A Case for Asymmetric-Cell Cache Memories.
877-881
Volume 13,
Number 8,
August 2005
- Hassan Hassan, Mohab Anis, Mohamed I. Elmasry:
MOS current mode circuits: analysis, design, and variability.
885-898
- Ajay Joshi, Jeffrey A. Davis:
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI).
899-910
- Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong:
A hardware Gaussian noise generator using the Wallace method.
911-920
- Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer:
Area-efficient high-throughput MAP decoder architectures.
921-933
- Azadeh Davoodi, Ankur Srivastava:
Power-driven simultaneous resource binding and floorplanning: a probabilistic approach.
934-942
- Michele Favalli:
A fuzzy model for path delay fault detection.
943-956
- Rupesh S. Shelar, Sachin S. Sapatnekar:
BDD decomposition for delay oriented pass transistor logic synthesis.
957-970
- Magdy A. El-Moursy, Eby G. Friedman:
Exponentially tapered H-tree clock distribution networks.
971-975
- Wu Jigang, Thambipillai Srikanthan, Heiko Schröder:
Efficient reconfigurable techniques for VLSI arrays with 6-port switches.
976-979
- Chunsheng Liu, Krishnendu Chakrabarty:
Design and analysis of compact dictionaries for diagnosis in scan-BIST.
979-984
- T. Egan, S. Mourad:
Design-for-testability for embedded delay-locked loops.
984-988
- Viktor Fischer, Milos Drutarovský, Pawel Chodowiec, F. Gramain:
InvMixColumn decomposition and multilevel resource sharing in AES implementations.
989-992
- Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic.
992-996
- Maria K. Michael, Spyros Tragoudas:
Function-based compact test pattern generation for path delay faults.
996-1001
- Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa:
A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*.
1002-1012
Volume 13,
Number 9,
September 2005
- Fei Sun, Tong Zhang:
Parallel high-throughput limited search trellis decoder VLSI design.
1013-1022
- Daehong Kim, Dongwan Shin, Kiyoung Choi:
Pipelining with common operands for power-efficient linear systems.
1023-1034
- Yan Lin, Fei Li, Lei He:
Circuits and architectures for field programmable gate array with configurable supply voltage.
1035-1047
- Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung:
Customizable elliptic curve cryptosystems.
1048-1059
- Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li:
Equivalent circuit model of on-wafer CMOS interconnects for RFICs.
1060-1071
- Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester:
Switch-factor based loop RLC modeling for efficient timing analysis.
1072-1078
- Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis:
Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time.
1079-1086
- Irith Pomeranz, Sudhakar M. Reddy:
Autoscan: a scan design without external scan inputs or outputs.
1087-1095
- Ashkan Ashrafi, Reza R. Adhami:
Comments on "A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula".
1096-1098
- X. P. Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo:
Design of a low power wide-band high resolution programmable frequency divider.
1098-1103
- Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh:
Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.
1103-1107
Volume 13,
Number 10,
October 2005
- Noureddine Chabini, Wayne Wolf:
Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints.
1113-1126
- Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene:
Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs.
1127-1135
- Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu:
Compiler-guided leakage optimization for banked scratch-pad memories.
1136-1146
- Nam Sung Kim, David Blaauw, Trevor N. Mudge:
Quantitative analysis and optimization techniques for on-chip cache leakage power.
1147-1156
- Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin:
Soft errors issues in low-power caches.
1157-1166
- Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake:
Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications.
1167-1178
- Zachary K. Baker, Viktor K. Prasanna:
A computationally efficient engine for flexible intrusion detection.
1179-1189
- Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson:
An energy-aware active smart card.
1190-1199
- Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, Srinivas Devadas:
Extracting secret keys from integrated circuits.
1200-1205
- Y. Abulafia, Avner Kornfeld:
Estimation of FMAX and ISB in microprocessors.
1205-1209
Volume 13,
Number 11,
November 2005
- Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy:
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
1213-1224
- Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy:
Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses.
1225-1238
- Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner:
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling.
1239-1252
- Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, Kenneth Maggio, Poras T. Balsara:
SoC with an integrated DSP and a 2.4-GHz RF transmitter.
1253-1265
- Antonio G. M. Strollo, Davide De Caro, Ettore Napoli, Nicola Petra:
A novel high-speed sense-amplifier-based flip-flop.
1266-1274
- Qiang Xu, Nicola Nicolici:
Modular and rapid testing of SOCs with unwrapped logic blocks.
1275-1285
- Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy:
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
1286-1295
- Bhaskar Chatterjee, Manoj Sachdev:
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology.
1296-1304
- Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna:
Energy- and time-efficient matrix multiplication on FPGAs.
1305-1319
- Peter Hallschmid, Steven J. E. Wilton:
Routing architecture optimizations for high-density embedded programmable IP cores.
1320-1324
- Weiping Liao, Joseph M. Basile, Lei He:
Microarchitecture-level leakage reduction with data retention.
1324-1328
Volume 13,
Number 12,
December 2005
- Shrirang K. Karandikar, Sachin S. Sapatnekar:
Fast comparisons of circuit implementations.
1329-1339
- Chuan Lin, Hai Zhou:
Wire retiming as fixpoint computation.
1340-1348
- Sandy Irani, Gaurav Singh, Sandeep K. Shukla, Rajesh K. Gupta:
An overview of the competitive and adversarial approaches to designing dynamic power management strategies.
1349-1361
- Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar:
Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits.
1362-1375
- Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester:
Bus encoding for total power reduction using a leakage-aware buffer configuration.
1376-1383
- Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect.
1384-1393
- Andreas Dandalis, Viktor K. Prasanna:
Configuration compression for FPGA-based embedded systems.
1394-1398
- Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh:
A multiparameter implantable microstimulator SOC.
1399-1402
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