Volume 6, Number 1, January 2001
Smita Bakshi, Daniel Gajski: Performance-constrained hierarchical pipelining for behaviors, loops, and operations. 1-25- Krishnendu Chakrabarty: Optimal test access architectures for system-on-a-chip. 26-49
- Rita Yu Chen, Mary Jane Irwin, Raminder Singh Bajwa: Architecture-level power estimation and design experiments. 50-66
- Pao-Ann Hsiung: POSE: a parallel object-oriented synthesis environment. 67-92
- Ing-Jer Huang: Co-synthesis of pipelined structures and instruction reordering constraints for instruction set processors. 93-121
- Evaggelinos P. Mariatos, Alexios N. Birbas, Michael K. Birbas: A mapping algorithm for computer-assisted exploration in the design of embedded systems. 122-147
Volume 6, Number 2, April 2001
- Preeti Ranjan Panda, Francky Catthoor, Nikil D. Dutt, Koen Danckaert, Erik Brockmeyer, Chidamber Kulkarni, Arnout Vandecappelle, Per Gunnar Kjeldsberg: Data and memory optimization techniques for embedded systems. 149-206
- U. Nagaraj Shenoy, Alok N. Choudhary, Prithviraj Banerjee: An algorithm for synthesis of large time-constrained heterogeneous adaptive systems. 207-225
- Chauchin Su, Yue-Tsang Chen, Shyh-Jye Jou: Intrinsic response for analog module testing using an analog testability bus. 226-243
- Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen: Verifying sequential equivalence using ATPG techniques. 244-275
Volume 6, Number 3, July 2001
- Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens: Processor modeling and code selection for retargetable compilation. 277-307
- Dimitrios Kagaris, Spyros Tragoudas: Von Neumann hybrid cellular automata for generating deterministic test sequences. 308-321
- Swanwa Liao, Mario A. Lopez, Dinesh P. Mehta: Constrained polygon transformations for incremental floorplanning. 322-342
- Chris C. N. Chu, D. F. Wong: Closed form solutions to simultaneous buffer insertion/sizing and wire sizing. 343-371
- Xiaobo Hu, Danny Z. Chen, Rajeshkumar S. Sambandam: Efficient list-approximation techniques for floorplan area minimization. 372-400
- Mehrdad Nourani, Joan Carletta, Christos A. Papachristou: Integrated test of interacting controllers and datapaths. 401-422
- Ishwar Parulkar, Sandeep K. Gupta, Melvin A. Breuer: Introducing redundant computations in RTL data paths for reducing BIST resources. 423-445
Volume 6, Number 4, October 2001
- Parthasarathi Dasgupta, Susmita Sur-Kolay: Slicible rectangular graphs and their optimal floorplans. 447-470
- Ismed Hartanto, Srikanth Venkataraman, W. Kent Fuchs, Elizabeth M. Rudnick, Janak H. Patel, Sreejit Chakravarty: Diagnostic simulation of stuck-at faults in sequential circuits using compact lists. 471-489
- M. Narasimhan, J. Ramanujam: A fast approach to computing exact solutions to the resource-constrained scheduling problem. 490-500
- Ramesh Karri, Balakrishnan Iyer: Introspection: A register transfer level technique for cocurrent error detection and diagnosis in data dominated designs. 505-515
- François R. Boyer, El Mostapha Aboulhamid, Yvon Savaria, Michel Boyer: Optimal design of synchronous circuits using software pipelining techniques. 516-532
- Jeroen Voeten: On the fundamental limitations of transformational design. 533-552
- Wen-Tsong Shiue, Sathishkumar Udayanarayanan, Chaitali Chakrabarti: Data memory design and exploration for low-power embedded systems. 553-568
- Pranav Ashar, Aarti Gupta, Sharad Malik: Using complete-1-distinguishability for FSM equivalence checking. 569-590
- Partha S. Roop, Arcot Sowmya, S. Ramesh: Forced simulation: A technique for automating component reuse in embedded systems. 602-628
- Paulo F. Flores, Horácio C. Neto, João P. Marques Silva: An exact solution to the minimum size test pattern problem. 629-644
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last updated on 2013-06-19T201401 by the dblp team