Volume 13, Number 1, January 2008

• 
  Nikil Dutt: Editorial.
• 
  Michael S. Hsiao, Robert B. Jones: Introduction to special section on high-level design, validation, and test.
• 
  Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer: Boosting interpolation with dynamic localized abstraction and redundancy removal.
• 
  Marc Boule, Zeljko Zilic: Automata-based assertion-checker synthesis of PSL properties.
• 
  Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir: C-testable bit parallel multipliers over GF(2^m).
• 
  Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz: A tool for automatic detection of deadlock in wormhole networks on chip.
• 
  Hai Zhou: A new efficient retiming algorithm derived by formal manipulation.
• 
  Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes: Probabilistic transfer matrices in symbolic reliability analysis of logic circuits.
• 
  Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang: A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.
• 
  F. Ryan Johnson, JoAnn M. Paul: Interrupt modeling for efficient high-level scheduler design space exploration.
• 
  Ümit Y. Ogras, Radu Marculescu: Analysis and optimization of prediction-based flow control in networks-on-chip.
• 
  Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen: Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes.
• 
  Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Massoud Pedram: Wavelet-based dynamic power management for nonstationary service requests.
• 
  Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang: Synthesis of a novel timing-error detection architecture.
• 
  Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf: ReChannel: Describing and simulating reconfigurable hardware in systemC.
• 
  Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov: Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors.
• 
  Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng: SoCDAL: System-on-chip design AcceLerator.
• 
  Nicholas H. Zamora, Xiaoping Hu, Ümit Y. Ogras, Radu Marculescu: Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective.
• 
  Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula: A fuel-cell-battery hybrid for portable embedded systems.
• 
  Wei-Chung Chao, Wai-Kei Mak: Low-power gated and buffered clock network construction.
• 
  Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou: Optimizing wirelength and routability by searching alternative packings in floorplanning.
• 
  Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai: Chip placement in a reticle for multiple-project wafer fabrication.

Volume 13, Number 2, April 2008

• 
  Nikil Dutt: Editorial.
• 
  Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri: SAT-based ATPG using multilevel compatible don't-cares.
• 
  Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang: A noniterative equivalent waveform model for timing analysis in presence of crosstalk.
• 
  Jin-Tai Yan: Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction.
• 
  Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado: An open-source binary utility generator.
• 
  James Moscola, John W. Lockwood, Young H. Cho: Reconfigurable content-based router using hardware-accelerated language parser.
• 
  Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle: Radio frequency identification prototyping.
• 
  Yu Hu, Yan Lin, Lei He, Tim Tuan: Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming.
• 
  Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev: A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration.
• 
  Xiangrong Zhou, Peter Petrov: Heterogeneously tagged caches for low-power embedded systems with virtual memory support.
• 
  Fang Liu, Sule Ozev, Plamen K. Nikolov: Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling.
• 
  Lei Cheng, Deming Chen, Martin D. F. Wong: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction.
• 
  Anna Bernasconi, Valentina Ciriani, Roberto Cordone: The optimization of kEP-SOPs: Computational complexity, approximability and experiments.
• 
  R. Iris Bahar, Krishnendu Chakrabarty: Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies.

Volume 13, Number 3, July 2008

• 
  Nikil D. Dutt: Editorial.
• 
  Alex K. Jones, Robert Walker: Introduction to the special section on demonstrable software systems and hardware platforms II.
• 
  Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek: A retargetable parallel-programming framework for MPSoC.
• 
  Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal: Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.
• 
  Ronny Krashinsky, Christopher Batten, Krste Asanovic: Implementing the scale vector-thread processor.
• 
  Prabhat Mishra, Nikil Dutt: Specification-driven directed test generation for validation of pipelined processors.
• 
  Yongsoo Joo, Youngjin Cho, Donghwa Shin, Jaehyun Park, Naehyuck Chang: An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory.
• 
  Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood: Designing secure systems on reconfigurable hardware.
• 
  Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement.
• 
  Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti: Postplacement voltage assignment under performance constraints.
• 
  Nicola Bombieri, Franco Fummi, Graziano Pravadelli: Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow.
• 
  Hiroaki Inoue, Junji Sakai, Masato Edahiro: Processor virtualization for secure mobile terminals.
• 
  Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor: Combining system scenarios and configurable memories to tolerate unpredictability.
• 
  Ozcan Ozturk, Mahmut T. Kandemir: ILP-Based energy minimization techniques for banked memories.
• 
  Sabyasachi Das, Sunil P. Khatri: Resource sharing among mutually exclusive sum-of-product blocks for area reduction.
• 
  I-Lun Tseng, Adam Postula: Partitioning parameterized 45-degree polygons with constraint programming.
• 
  Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty: Power-aware SoC test planning for effective utilization of port-scalable testers.
• 
  Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek: Evolution of synthetic RTL benchmark circuits with predefined testability.

Volume 13, Number 4, September 2008

• 
  Massoud Pedram: Editorial.
• 
  Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu, Ge Yu: Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs.
• 
  Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal: A high-level clustering algorithm targeting dual V_dd FPGAs.
• 
  Javier Resano, Juan Antonio Clemente, Carlos González, Daniel Mozos, Francky Catthoor: Efficiently scheduling runtime reconfigurations.
• 
  Siddharth Garg, Diana Marculescu: System-level throughput analysis for process variation aware multiple voltage-frequency island designs.
• 
  Ozcan Ozturk, Mahmut T. Kandemir, Guangyu Chen: Access pattern-based code compression for memory-constrained systems.
• 
  Nastaran Baradaran, Pedro C. Diniz: A compiler approach to managing storage and memory bandwidth in configurable architectures.
• 
  Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti: Auxiliary state machines + context-triggered properties in verification.
• 
  S. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar: Simulation-based verification using Temporally Attributed Boolean Logic.
• 
  Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li: Layout-aware scan chain reorder for launch-off-shift transition test coverage.
• 
  Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer: Timing-aware power-optimal ordering of signals.
• 
  Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu: Effective decap insertion in area-array SoC floorplan design.
• 
  Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack: Constraint-driven floorplan repair.
• 
  Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger: Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules.

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