Volume 12, Number 1, January 2007

• 
  Anup Gangwar, M. Balakrishnan, Anshul Kumar: Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.
• 
  Nicholas H. Zamora, Xiaoping Hu, Radu Marculescu: System-level performance/power analysis for platform-based design of multimedia applications.
• 
  Chiu-Wing Sham, Evangeline F. Y. Young: Area reduction by deadspace utilization on interconnect optimized floorplan.
• 
  Lei Li, Zhanglei Wang, Krishnendu Chakrabarty: Scan-BIST based on cluster analysis and the encoding of repeating sequences.
• 
  Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy: Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints.
• 
  Xinping Zhu, Sharad Malik: A hierarchical modeling framework for on-chip communication architectures of multiprocessing SoCs.
• 
  Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Swarup Kumar Das: Hierarchical partitioning of VLSI floorplans by staircases.
• 
  Jong-eun Lee, Kiyoung Choi, Nikil D. Dutt: Instruction set synthesis with efficient instruction encoding for configurable processors.

Volume 12, Number 2, April 2007

• 
  Nikil Dutt: Editorial.
• 
  Chao Wang, Zijiang Yang, Franjo Ivancic, Aarti Gupta: Disjunctive image computation for software verification.
• 
  Bren Mochocki, Xiaobo Sharon Hu, Gang Quan: Transition-overhead-aware voltage scheduling for fixed-priority real-time systems.
• 
  Hongliang Chang, Sachin S. Sapatnekar: Prediction of leakage power under process uncertainties.
• 
  Sumit Mohanty, Viktor K. Prasanna: A model-based extensible framework for efficient application design using FPGA.
• 
  Weiyu Tang, Arun Kejariwal, Alexander V. Veidenbaum, Alexandru Nicolau: A predictive decode filter cache for reducing power consumption in embedded processors.
• 
  Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nikil Dutt: DRDU: A data reuse analysis technique for efficient scratch-pad memory management.
• 
  Mohammad Hosseinabady, Pejman Lotfi-Kamran, Zainalabedin Navabi: Low test application time resource binding for behavioral synthesis.
• 
  Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar: A critical-path-aware partial gating approach for test power reduction.
• 
  Irith Pomeranz, Sudhakar M. Reddy: Forming N-detection test sets without test generation.
• 
  Hongbing Fan, Jiping Liu, Yu-Liang Wu, Chak-Chung Cheung: The exact channel density and compound design for generic universal switch blocks.

Volume 12, Number 3, August 2007

• 
  Sung Kyu Lim, Massoud Pedram: Introduction to special issue on demonstrable software systems and hardware platforms.
• 
  Chia-Jui Hsu, Ming-Yung Ko, Shuvra S. Bhattacharyya, Suren Ramasubbu, José Luis Pino: Efficient simulation of critical synchronous dataflow graphs.
• 
  Fernando Herrera, Eugenio Villar: A framework for heterogeneous specification and design of electronic embedded systems in SystemC.
• 
  Hyung Gyu Lee, Naehyuck Chang, Ümit Y. Ogras, Radu Marculescu: On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches.
• 
  Soonhoi Ha, Sungchan Kim, Choonseung Lee, Youngmin Yi, Seongnam Kwon, Young-Pyo Joo: PeaCE: A hardware-software codesign environment for multimedia embedded systems.
• 
  David Atienza, Pablo Garcia Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida: HW-SW emulation framework for temperature-aware design in MPSoCs.
• 
  Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan: Efficient power modeling and software thermal sensing for runtime temperature monitoring.
• 
  Po-Kuan Huang, Soheil Ghiasi: Efficient and scalable compiler-directed energy optimization for realtime applications.
• 
  Yiyu Shi, Paul Mesa, Hao Yu, Lei He: Circuit-simulated obstacle-aware Steiner routing.
• 
  Lakshmi N. Chakrapani, Pinar Korkmaz, Bilge E. S. Akgul, Krishna V. Palem: Probabilistic system-on-a-chip architectures.
• 
  Ang-Chih Hsieh, Tzu-Teng Lin, Tsuang-Wei Chang, TingTing Hwang: A functionality-directed clustering technique for low-power MTCMOS design - computation of simultaneously discharging current.
• 
  Tathagato Rai Dastidar, P. P. Chakrabarti: A verification system for transient response of analog circuits.
• 
  Kai-Hui Chang, Igor L. Markov, Valeria Bertacco: Postplacement rewiring by exhaustive search for functional symmetries.
• 
  Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shukla, Axel Jantsch: EWD: A metamodeling driven customizable multi-MoC system modeling framework.
• 
  Greg Stitt, Frank Vahid: Binary synthesis.
• 
  Michalis D. Galanis, Gregory Dimitroulakos, Spyros Tragoudas, Costas E. Goutis: Speedups in embedded systems with a high-performance coprocessor datapath.
• 
  Suchismita Roy, P. P. Chakrabarti, Pallab Dasgupta: Event propagation for accurate circuit delay calculation using SAT.

Volume 12, Number 4, September 2007

• 
  Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang: Temporal floorplanning using the three-dimensional transitive closure subGraph.
• 
  Jinfeng Liu, Pai H. Chou: Idle energy minimization by mode sequence optimization.
• 
  Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou: Ultra-fast and efficient algorithm for energy optimization by gradient-based stochastic voltage and task scheduling.
• 
  Peter Vanbroekhoven, Gerda Janssens, Maurice Bruynooghe, Francky Catthoor: A practical dynamic single assignment transformation.
• 
  Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai: Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors.
• 
  Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller: Techniques for the synthesis of reversible Toffoli networks.
• 
  Youcef Bouchebaba, Bruno Girodias, Gabriela Nicolescu, El Mostapha Aboulhamid, Bruno Lavigueur, Pierre G. Paulin: MPSoC memory optimization using program transformation.
• 
  Dipankar Das, P. P. Chakrabarti, Rajeev Kumar: Functional verification of task partitioning for multiprocessor embedded systems.
• 
  Shih-Hsu Huang, Yow-Tyng Nieh: Clock skew scheduling with race conditions considered.
• 
  Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner: Exploring time/resource trade-offs by solving dual scheduling problems with the ant colony optimization.
• 
  Swaroop Ghosh, Swarup Bhunia, Kaushik Roy: Low-Power and testable circuit synthesis using Shannon decomposition.
• 
  Christopher Ostler, Karam S. Chatha, Vijay Ramamurthi, Krishnan Srinivasan: ILP and heuristic techniques for system-level design on network processor architectures.
• 
  Sivaram Gopalakrishnan, Priyank Kalla: Optimization of polynomial datapaths using finite ring algebra.
• 
  Qubo Hu, Per Gunnar Kjeldsberg, Arnout Vandecappelle, Martin Palkovic, Francky Catthoor: Incremental hierarchical memory size estimation for steering of loop transformations.
• 
  Yi-Ping You, Chung-Wen Huang, Jenq Kuen Lee: Compilation for compact power-gating controls.
• 
  Gang Chen, Xiaoyu Song, Feng Liu, QingPing Tan, Fei He: A note on "a mapping algorithm for computer-assisted exploration in the design of embedded systems".

last updated on Sat May 18 06:48:01 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page