dblp: Transactions on High-Performance Embedded Architectures and Compilers IV

Magnus Jahre, Lasse Natvig: A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors. 1-20

Frederik Vandeputte, Lieven Eeckhout: Characterizing Time-Varying Program Behavior Using Phase Complexity Surfaces. 21-41

Timothy M. Jones, Michael F. P. O'Boyle, Jaume Abella, Antonio González: Compiler Directed Issue Queue Energy Reduction. 42-62

Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes: A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. 63-83

Omer Khan, Sandip Kundu: Microvisor: A Runtime Architecture for Thermal Management in Chip Multiprocessors. 84-110

Arnaldo Azevedo, Ben H. H. Juurlink, Cor Meenderinck, Andrei Terechko, Jan Hoogerbrugge, Mauricio Alvarez, Alex Ramírez, Mateo Valero: A Highly Scalable Parallel Implementation of H.264. 111-134

Sai Prashanth Muralidhara, Mahmut T. Kandemir: Communication Based Proactive Link Power Management. 135-154

Frederik Vandeputte, Lieven Eeckhout: Finding Extreme Behaviors in Microprocessor Workloads. 155-174

Michael B. Henry, Leyla Nazhandali: Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput FFT Architecture. 175-194

Mohammad Ansari, Mikel Luján, Christos Kotselidis, Kim Jarvis, Chris C. Kirkham, Ian Watson: Transaction Reordering to Reduce Aborts in Software Transactional Memory. 195-214

Yasutaka Wada, Akihiro Hayashi, Takeshi Masuura, Jun Shirako, Hirofumi Nakano, Hiroaki Shikano, Keiji Kimura, Hironori Kasahara: A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor Architecture. 215-233

Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan: A Modular Simulator Framework for Network-on-Chip Based Manycore Chips Using UNISIM. 234-253

Adam Welc, Bratin Saha: Software Transactional Memory Validation - Time and Space Considerations. 254-273

Nan Wu, Qianming Yang, Mei Wen, Yi He, Ju Ren, Maolin Guan, Chunyuan Zhang: Tiled Multi-Core Stream Architecture. 274-293

Nan Yuan, Lei Yu, Dongrui Fan: An Efficient and Flexible Task Management for Many Cores. 294-310

Valeriu Beiu, Basheer A. M. Madappuram, Peter M. Kelly, Liam McDaid: On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -. 311-333

Daniel Llorente, Kimon Karras, Thomas Wild, Andreas Herkersdorf: Advanced Packet Segmentation and Buffering Algorithms in Network Processors. 334-353

William G. Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer: Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. 354-369

Markus Rullmann, Renate Merker: A Cost Model for Partial Dynamic Reconfiguration. 370-390

William Plishker, Nimish Sane, Mary Kiemb, Shuvra S. Bhattacharyya: Heterogeneous Design in Functional DIF. 391-408

Stanley Jaddoe, Mark Thompson, Andy D. Pimentel: Signature-Based Calibration of Analytical Performance Models for System-Level Design Space Exploration. 409-425

Transactions on High-Performance Embedded Architectures and Compilers, Volume 4, 2011

Regular Papers

4th International Conference on High-Performance and Embedded Architectures and Compilers - HiPEAC (Selected Papers)

Workshop on Software and Hardware Challenges of Many-core Platforms - SHCMP (Selected Papers)

8th IEEE International Symposium on Systems, Architectures, Modeling and Simulation - SAMOS VIII (Selected Papers)