IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 4

Volume 4, Number 1, January 1985

• Ting-Hua Chen, Melvin A. Breuer:
  Automatic Design for Testability Via Testability Measures. 3-11
  
• Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada:
  CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design. 12-22
  
• Susanne E. Hambrusch:
  Channel Routing Algorithms for Overlap Models. 23-30
  
• Thomas G. Szymanski:
  Dogleg Channel Routing is NP-Complete. 31-41
  
• A. Poncet:
  Finite-Element Simulation of Local Oxidation of Silicon. 41-53
  
• Jonathan B. Rosenberg:
  Geographical Data Structures Compared: A Study of Data Structures Supporting Region Queries. 53-67
  
• Takao Nishizeki, Nobuji Saito, Kiminobu Suzuki:
  A Linear-Time Routing Algorithm for Convex Grids. 68-76
  
• Andrzej J. Strojwas, Stephen W. Director:
  A Pattern Recognition Based Method for IC Failure Analysis. 76-92
  
• Alfred E. Dunlop, Brian W. Kernighan:
  A Procedure for Placement of Standard-Cell VLSI Circuits. 92-98
  
• G. Bischoff, J. P. Krusius:
  Technology Independent Device Modeling for Simulation of Integrated Circuits for FET Technologies. 99-110
  
• A. M. Mazzone:
  Three-Dimensional Monte Carlo Simulations--Part II: Recoil Phenomena. 110-117
  

Volume 4, Number 2, April 1985

• A. M. Patel, N. L. Soong, R. K. Korn:
  Hierarchical VLSI Routing - An Approximate Routing Procedure. 121-126
  
• R. F. Vogel:
  Analytical MOSFET Model with Easily Extracted Parameters. 127-134
  
• Emil F. Girczyc, Raymond J. A. Buhr, John P. Knight:
  Applicability of a Subset of Ada as an Algorithmic Hardware Description Language for Graph-Based Hardware Compilation. 134-142
  
• N. N. Chan, Robert W. Dutton:
  Lump Partitioning of IC Bipolar Transistor Models for High-Frequency Applications. 143-149
  
• Martine D. F. Schlag, Ellen J. Yoffa, Peter S. Hauge, Chak-Kuen Wong:
  A Method for Improving Cascode-Switch Macro Wirability. 150-155
  
• Wojciech Maly, Zygmunt Pizlo:
  Tolerance Assignment for IC Selection Tests. 156-162
  

Volume 4, Number 3, July 1985

• Wojciech Maly:
  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits. 166-177
  
• A. F. Franz, G. A. Franz:
  BAMBI -- A Design Model for Power MOSFET's. 177-189
  
• Wayne Wei-Ming Dai, Tetsuo Asano, Ernest S. Kuh:
  Routing Region Definition and Ordering Scheme for Building-Block Layout. 189-197
  
• Maciej J. Ciesielski:
  Two-Dimensional Routing for the Silc Silicon Compiler. 198-203
  
• Hideaki Kobayashi, Charles E. Drozd:
  Efficient Algorithms for Routing Interchangeable Terminals. 204-207
  
• James Reed, Alberto L. Sangiovanni-Vincentelli, Mauro Santomauro:
  A New Symbolic Channel Router: YACR2. 208-219
  
• Omar Wing, Shuo Huang, Rui Wang:
  Gate Matrix Layout. 220-231
  
• Fujio Yamamoto, Sakae Takahashi:
  Vectorized LU Decomposition Algorithms for Large-Scale Circuit Simulation. 232-239
  
• William J. Dally, Randal E. Bryant:
  A Hardware Architecture for Switch-Level Simulation. 239-250
  
• Tonysheng Lin, Stephen Y. H. Su:
  The S-Algorithm: A Promising Solution for Systematic Functional Test Generation. 250-263
  
• Niraj K. Jha, Jacob A. Abraham:
  Design of Testable CMOS Logic Circuits Under Arbitrary Delays. 264-269
  
• Giovanni De Micheli, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
  Optimal State Assignment for Finite State Machines. 269-285
  
• Jan M. Rabaey, Stephen P. Pope, Robert W. Brodersen:
  An Integrated Automated Layout Generation System for DSP Circuits. 285-296
  
• Edgar Sánchez-Sinencio, Jaime Ramírez-Angulo:
  AROMA: An Area Optimized CAD Program for Cascade SC Filter Design. 296-303
  
• Hugo De Man, Ivo Bolsens, E. Vanden Meersch, Johan Van Cleynenbreugel:
  DIALOG: An Expert Debugging System for MOSVLSI Design. 303-311
  
• Prithviraj Banerjee, Jacob A. Abraham:
  A Multivalued Algebra For Modeling Physical Failures in MOS VLSI Circuits. 312-321
  
• Min-Wen Chiang, J. C. Junior, Chuck Kao:
  A Simulation Method to Completely Model the Various Transistor I-V Operational Modes of Long Channel Depletion MOSFET's. 322-328
  
• Masayuki Terai:
  A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays. 329-336
  
• John K. Ousterhout:
  A Switch-Level Timing Verifier for Digital MOS VLSI. 336-349
  
• Di Ma:
  A Physical and SPICE-Compatible Model for the MOS Depletion Device. 349-356
  

Volume 4, Number 4, October 1985

• M. D. Giles, J. F. Gibbons:
  Calculation of Channeling Effects During Ion Implantation Using the Boltzmann Transport Equation. 362-368
  
• A. M. Mazzone:
  Monte Carlo Methods in Defects Migration -- Spontaneous Annealing of Damage Induced by Ion Implantation. 369-373
  
• J. Albers:
  Monte Carlo Calculation of One- and Two-Dimensional Particle and Damage Distributions for Ion-Implanted Dopants in Silicon. 374-383
  
• Peter Pichler, Werner Jüngling, Siegfried Selberherr, Edgar Guerrero, Hans W. Pötzl:
  Simulation of Critical IC-Fabrication Steps. 384-397
  
• Thye-Lai Tung, Dimitri A. Antoniadis:
  A Boundary Integral Equation Approach to Oxidation Modeling. 398-403
  
• Albert Seidl, Milos Svoboda:
  Numerical Conformal Mapping for Treatment of Geometry Problems in Process Simulation. 404-407
  
• Hal R. Yeager, Robert W. Dutton:
  An Approach to Solving Multiparticle Diffusion Exhibiting Nonlinear Stiff Coupling. 408-420
  
• Jürgen Lorenz, Joachim Pelka, Heiner Ryssel, Albert Sachs, Albert Seidl, Milos Svoboda:
  COMPOSITE -- A Complete Modeling Program of Silicon Technology. 421-430
  
• Craig C. Douglas:
  A Multilevel Solver for Boundary Value Problems. 431-435
  
• Randolph E. Bank, William M. Coughran Jr., Wolfgang Fichtner, Eric Grosse, Donald J. Rose, R. Kent Smith:
  Transient Simulation of Silicon Devices and Circuits. 436-451
  
• Kiyoyuki Yokoyama, Masaaki Tomizawa, Akira Yoshii, Tsuneta Sudo:
  Semiconductor Device Simulation at NTT. 452-461
  
• Conor S. Rafferty, Mark R. Pinto, Robert W. Dutton:
  Iterative Methods in Semiconductor Device Simulation. 462-471
  
• Steven E. Laux:
  Techniques for Small-Signal Analysis of Semiconductor Devices. 472-481
  
• Toru Toyabe, H. Masuda, Y. Aoki, H. Shukuri, T. Hagiwara:
  Three-Dimensional Device Simulator CADDETH with Highly Convergent Matrix Solution Algorithms. 482-488
  
• Joseph W. Jerome:
  The Role of Semiconductor Device Diameter and Energy-Band Bending in Convergence of Picard Iteration for Gummel's Map. 489-495
  
• E. Palm, F. Van de Wiele:
  Current Lines and Accurate Contact Current Evaluation in 2-D Numerical Simulation of Semiconductor Devices. 496-503
  
• Charles L. Wilson, James L. Blue:
  Accurate Current Calculation in Two-Dimensional MOSFET Models. 504-512
  
• H. S. Bennett, D. E. Fuoss:
  Improved Physics for Simulating Submicron Bipolar Devices. 513-519
  
• Steven E. Laux, Bertrand M. Grossman:
  A General Control-Volume Formulation for Modeling Impact Ionization in Semiconductor Transport. 520-526
  
• A. S. Shieh:
  On the Solution of Coupled System of PDE by a Multigrid Method. 527-530
  
• James P. Lavine, Win-Chyi Chang, Constantine N. Anagnostopoulos, Bruce C. Burkey, E. T. Nelson:
  Monte Carlo Simulation of the Photoelectron Crosstalk in Silicon Imaging Devices. 531-535
  
• C. Moglestue:
  A Monte Carlo Particle Study of the Intrinsic Noise Figure in GaAs MESFET's. 536-540
  
• Umberto Ravaioli, Paolo Lugli, Mohamed A. Osman, David K. Ferry:
  Advantages of Collocation Methods Over Finite Differences in One-Dimensional Monte Carlo Simulations of Submicron Devices. 541-545
  
• Jeffrey L. Gray, Mark S. Lundstrom:
  A Numerical Solution of Poisson's Equation with Application to C-V Analysis of III-V Heterojunction Capacitors. 546-553
  
• R. I. Sokel, D. B. MacMillen:
  Practical Integration of Process, Device, and Circuit Simulation. 554-560
  
• Enrico Sangiorgi, Mark R. Pinto, Stanley E. Swirhun, Robert W. Dutton:
  Two-Dimensional Numerical Analysis of Latchup in a VLSI CMOS Technology. 561-574
  
• Bernd Meinerzhagen, Heinz K. Dirks, Walter L. Engl:
  Quasi-Simultaneous Solution Method: A New Highly Efficient Strategy for Numerical MOST Simulations. 575-582
  
• M.-D. D. Huang:
  The Constant-Flow Patch Test -- A Unique Guideline for the Evaluation of Discretization Schemes for the Current Continuity Equations. 583-608
  
• Dale E. Hocevar, Ping Yang, Timothy N. Trick, Berton D. Epler:
  Transient Sensitivity Computation for MOSFET Circuits. 609-620
  
• S. Inohira, T. Shinmi, M. Nagata, Toru Toyabe, K. Iida:
  A Statistical Model Including Parameter Matching for Analog Integrated Circuits Simulation. 621-628
  
• Hong-June Park, Choong-Ki Kim:
  An Empirical Model for the Threshold Voltage of Enhancement NMOSFET's. 629-635
  
• Chung-Yu Wu, Jen-Sheng Hwang, Chih Chang, Ching-Chu Chang:
  An Efficient Timing Model for CMOS Combinational Logic Gates. 636-650
  
• San-Chin Fang, Yannis P. Tsividis, Omar Wing:
  Time- and Frequency-Domain Analysis of Linear Switched-Capacitor Networks Using State Charge Variables. 651-661
  
• Makiko Kakizaki, Tsutomu Sugawara:
  A Modified Newton Method for the Steady-State Analysis. 662-667
  
• Karem A. Sakallah, Stephen W. Director:
  SAMSON2: An Event Driven VLSI Circuit Simulator. 668-684
  
• Eduard Cerny, Jan Gecsei:
  Simulation of MOS Circuits by Decision Diagrams. 685-693
  
• P. Conway, Ciaran G. Cahill, W. A. Lane, S. U. Lidholm:
  Extraction of MOSFET Parameters Using the Simplex Direct Search Optimization Method. 694-698
  

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