Volume 23, Number 1, January 2004
Robert P. Dick
, Niraj K. Jha
: COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems.
, Axel Jantsch
: System modeling and transformational design refinement in ForSyDe [formal system design].
, Jens Lienig
: Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits.
Leendert M. Huisman
: Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).
: Constrained test generation for embedded synchronous sequential circuits with serial-input access.
Volume 23, Number 2, February 2004
Geun Rae Cho
, Tom Chen
: Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.
: Pitfalls of hierarchical fault simulation.
: I/O placement for FPGAs with multiple I/O standards.
Volume 23, Number 3, March 2004
, Sung Kyu Lim
: Edge separability-based circuit clustering with application to multilevel circuit partitioning.
, Lei He
: Full-chip routing optimization with RLC crosstalk budgeting.
Volume 23, Number 4, April 2004
Andrew B. Kahng
, Xu Xu
: Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.
Volume 23, Number 5, May 2004
: Efficient Steiner tree construction based on spanning graphs.
Volume 23, Number 6, June 2004
: Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures.
: Rapid method to account for process variation in full-chip capacitance extraction.
, Yao-Wen Chang
: TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.
Volume 23, Number 7, July 2004
Volume 23, Number 8, August 2004
Volume 23, Number 9, September 2004
, Sujit Dey
: High-level crosstalk defect Simulation methodology for system-on-chip interconnects.
Volume 23, Number 10, October 2004
: Noise-rejection model based on charge-transfer equation for digital CMOS circuits.
: Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.
, Ramesh Karri
: Fault secure datapath synthesis using hybrid time and hardware redundancy.
Volume 23, Number 11, November 2004
Volume 23, Number 12, December 2004
, Amjad Hajjar
: Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics.
, Sung Kyu Lim
: Retiming-based timing analysis with an application to mincut-based global placement.