Volume 23, Number 1, January 2004
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Robert P. Dick ,
Niraj K. Jha :
COWLS: hardware-software cosynthesis of wireless low-power distributed embedded client-server systems.
2-16
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Ingo Sander ,
Axel Jantsch :
System modeling and transformational design refinement in ForSyDe [formal system design].
17-32
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Göran Jerke ,
Jens Lienig :
Hierarchical current-density verification in arbitrarily shaped metallization patterns of analog circuits.
80-90
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Leendert M. Huisman :
Diagnosing arbitrary defects in logic designs using single location at a time (SLAT).
91-101
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Irith Pomeranz :
Constrained test generation for embedded synchronous sequential circuits with serial-input access.
164-172
Volume 23, Number 2, February 2004
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Geun Rae Cho ,
Tom Chen :
Synthesis of single/dual-rail mixed PTL/static logic for low-power applications.
229-242
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Sandip Kundu :
Pitfalls of hierarchical fault simulation.
312-314
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Wai-Kei Mak :
I/O placement for FPGAs with multiple I/O standards.
315-321
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Volume 23, Number 3, March 2004
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Jason Cong ,
Sung Kyu Lim :
Edge separability-based circuit clustering with application to multilevel circuit partitioning.
346-357
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journals/tcad/JingHXBCG04 export record as
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Jinjun Xiong ,
Lei He :
Full-chip routing optimization with RLC crosstalk budgeting.
366-377
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Volume 23, Number 4, April 2004
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Andrew B. Kahng ,
Xu Xu :
Local unidirectional bias for cutsize-delay tradeoff in performance-driven bipartitioning.
464-471
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journals/tcad/ThalhammerW04a
Volume 23, Number 5, May 2004
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Hai Zhou :
Efficient Steiner tree construction based on spanning graphs.
704-710
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journals/tcad/TehranipourAN04
Volume 23, Number 6, June 2004
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Shinji Odanaka :
Multidimensional discretization of the stationary quantum drift-diffusion model for ultrasmall MOSFET structures.
837-842
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Andrew Labun :
Rapid method to account for process variation in full-chip capacitance extraction.
941-951
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Jai-Ming Lin ,
Yao-Wen Chang :
TCG-S: orthogonal coupling of P/sup */-admissible representations for general floorplans.
968-980
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Volume 23, Number 7, July 2004
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journals/tcad/RosingerAN04
Volume 23, Number 8, August 2004
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Volume 23, Number 9, September 2004
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Xiaoliang Bai ,
Sujit Dey :
High-level crosstalk defect Simulation methodology for system-on-chip interconnects.
1355-1361
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journals/tcad/TakeuchiYSSH04
Volume 23, Number 10, October 2004
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Alexander Korshak :
Noise-rejection model based on charge-transfer equation for digital CMOS circuits.
1460-1468
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journals/tcad/Pomeranz04a Irith Pomeranz :
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.
1465-1478
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Kaijie Wu ,
Ramesh Karri :
Fault secure datapath synthesis using hybrid time and hardware redundancy.
1476-1485
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Volume 23, Number 11, November 2004
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journals/tcad/WalkeySCMM04
Volume 23, Number 12, December 2004
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Tom Chen ,
Amjad Hajjar :
Statistical timing analysis of coupled interconnects using quadratic delay-change characteristics.
1677-1683
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Jason Cong ,
Sung Kyu Lim :
Retiming-based timing analysis with an application to mincut-based global placement.
1684-1692
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