Volume 50, Number 1, January 2001

• 
  V. Carl Hamacher, Hong Jiang: Hierarchical Ring Network Configuration and Performance Modeling. 1-12
• 
  Paolo Montuschi, Tomás Lang: Boosting Very-High Radix Division with Prescaling and Selection by Rounding. 13-27
• 
  Sumit Ghosh: P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors. 28-50
• 
  Chih-wen Hsueh, Kwei-Jay Lin: Scheduling Real-Time Systems with End-to-End Timing Constraints Using the Distributed Pinwheel Model. 51-66
• 
  Lucian Codrescu, D. Scott Wills, James D. Meindl: Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular Applications. 67-82

• 
  Berk Sunar, Çetin Kaya Koç: An Efficient Optimal Normal Basis Type II Multiplier. 83-87
• 
  Adele A. Rescigno: Optimally Balanced Spanning Tree of the Star Network. 88-91

Volume 50, Number 2, February 2001

• 
  Charu C. Aggarwal, Joel L. Wolf, Philip S. Yu: The Maximum Factor Queue Length Batching Scheme for Video-on-Demand Systems. 97-110
• 
  Hakan Aydin, Rami G. Melhem, Daniel Mossé, Pedro Mejía-Alvarez: Optimal Reward-Based Scheduling for Periodic Real-Time Tasks. 111-130
• 
  Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio, Jyotsna Sabarinathan: Java Runtime Systems: Characterization and Architectural Implications. 131-146
• 
  Dragan Jankovic, Radomir S. Stankovic, Rolf Drechsler: Decision Diagram Method for Calculation of Pruned Walsh Transform. 147-157
• 
  Eric E. Johnson, Jiheng Ha, Baqar Zaidi: Lossless Trace Compression. 158-173

• 
  Gérard D. Cohen, Iiro S. Honkala, Antoine Lobstein, Gilles Zémor: On Codes Identifying Vertices in the Two-Dimensional Square Lattice with Diagonals. 174-176
• 
  Prabir Dasgupta, Santanu Chattopadhyay, Parimal Pal Chaudhuri, Indranil Sengupta: Cellular Automata-Based Recursive Pseudoexhaustive Test Pattern Generator. 177-185
• 
  Koppolu Sasidhar, Abhijit Chatterjee: Hierarchical Diagnosis of Identical Units in a System. 186-191

Volume 50, Number 3, March 2001

• 
  Mikhail J. Atallah: On Estimating the Large Entries of a Convolution. 193-196
• 
  Hung-Ying Tyan, Jennifer C. Hou, Bin Wang, Ching-Chih Han: On Supporting Temporal Quality of Service in WDMA-Based Star-Coupled Optical Networks. 197-214
• 
  Junhyung Um, Taewhan Kim: An Optimal Allocation of Carry-Save-Adders in Arithmetic Circuits. 215-233
• 
  Josep Llosa, Eduard Ayguadé, Antonio González, Mateo Valero, Jason Eckhardt: Lifetime-Sensitive Modulo Scheduling in a Production Environment. 234-249
• 
  Steve Haynal, Forrest Brewer: Automata-Based Symbolic Scheduling for Looping DFGs. 250-267
• 
  Victor V. Zyuban, Peter M. Kogge: Inherently Lower-Power High-Performance Superscalar Architectures. 268-285

Volume 50, Number 4, April 2001

• 
  Jean-Luc Gaudiot: Editor's Note. 289-291
• 
  Kenneth M. Wilson, Kunle Olukotun: High Bandwidth On-Chip Cache Design. 292-307
• 
  Guillem Bernat, Alan Burns, Albert Llamosí: Weakly Hard Real-Time Systems. 308-321
• 
  Wee Teck Ng, Peter M. Chen: The Design and Verification of the Rio File Cache. 322-337
• 
  Glenn Reinman, Brad Calder, Todd M. Austin: Optimizations Enabled by a Decoupled Front-End Architecture. 338-355
• 
  Yi-Bing Lin: Eliminating Overflow for Large-Scale Mobility Databases in Cellular Telephone Networks. 356-370
• 
  Hee Yong Youn, Choong Gun Oh, Hyunseung Choo, Jin-Wook Chung, Dongman Lee: An Efficient Algorithm-Based Fault Tolerance Design Using the Weighted Data-Check Relationship. 371-383

Volume 50, Number 5, May 2001

• 
  Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee: Bit-Parallel Systolic Multipliers for GF(2m) Fields Defined by All-One and Equally Spaced Polynomials. 385-393
• 
  Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi: A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis. 394-398
• 
  Stephanie Mahévas, Gerardo Rubino: Bound Computation of Dependability and Performance Measures. 399-413
• 
  Ching-Chih Han, Kang G. Shin, Chao-Ju Hou: Synchronous Bandwidth Allocation for Real-Time Communications with the Timed-Token MAC Protocol. 414-431
• 
  Enric Pastor, Jordi Cortadella, Oriol Roig: Symbolic Analysis of Bounded Petri Nets. 432-448
• 
  Anna Antola, Fabrizio Ferrandi, Vincenzo Piuri, Mariagiovanna Sami: Semiconcurrent Error Detection in Data Paths. 449-465
• 
  Bruce L. Jacob, Trevor N. Mudge: Uniprocessor Virtual Memory without TLBs. 482-499
• 
  Yu-Liang Liu, Yue-Li Wang, D. J. Guan: An Optimal Fault-Tolerant Routing Algorithm for Double-Loop Networks. 500-505
• 
  Özgür Erçetin, Leandros Tassiulas: Push-Based Information Delivery in Two Stage Satellite-Terrestrial Wireless Systems. 506-518

• 
  Keqin Li, Victor Y. Pan: Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System. 519-525

• 
  Kyunghee Choi, Gihyun Jung: Comment on 'On-Line Scheduling Policies for a Class of IRIS Real-Time Tasks'. 526-528

Volume 50, Number 6, June 2001

• 
  Wei Hsu, Vasanth Bala: Guest Editors' Introduction. 527-528
• 
  Kemal Ebcioglu, Erik R. Altman, Michael Gschwind, Sumedh W. Sathaye: Dynamic Binary Translation and Optimization. 529-548
• 
  Thomas Kistler, Michael Franz: Continuous Program Optimization: Design and Evaluation. 549-566
• 
  Matthew C. Merten, Andrew R. Trick, Ronald D. Barnes, Erik M. Nystrom, Christopher N. George, John C. Gyllenhaal, Wen-mei W. Hwu: An Architectural Framework for Runtime Optimization. 567-589
• 
  Sanjay J. Patel, Steven Lumetta: rePLay: A Hardware Framework for Dynamic Optimization. 590-608

• 
  Konstantina Karagianni, Vassilis Paliouras, George Diamantakos, Thanos Stouraitis: Operation-Saving VLSI Architectures for 3D Geometrical Transformations. 609-622

Volume 50, Number 7, July 2001

• 
  Hamid Sarbazi-Azad, Mohamed Ould-Khaoua, Lewis M. Mackenzie: Analytical Modeling of Wormhole-Routed k-Ary n-Cubes in the Presence of Hot-Spot Traffic. 623-634
• 
  Chih-Fang Wang, Sartaj Sahni: Matrix Multiplication on the OTIS-Mesh Optoelectronic Computer. 635-646
• 
  Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani: A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. 647-659
• 
  Tei-Wei Kuo, Ming-Chung Liang, LihChyun Shu: Abort-Oriented Concurrency Control for Real-Time Databases. 660-673
• 
  Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Testing Schemes for FIR Filter Structures. 674-688
• 
  Monica Bianchini, Stefano Fanelli, Marco Gori: Optimal Algorithms for Well-Conditioned Nonlinear Systems of Equations. 689-698
• 
  Yibei Ling, Jie Mi, Xiaola Lin: A Variational Calculus Approach to Optimal Checkpoint Placement. 699-708
• 
  Sangyeun Cho, Pen-Chung Yew, Gyungho Lee: A High-Bandwidth Memory Pipeline for Wide Issue Processors. 709-723
• 
  John F. Meyer: Performability of an Algorithm for Connection Admission Control. 724-733
• 
  Tong Zhang, Keshab K. Parhi: Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. 734-749
• 
  Lu Ruan, Ding-Zhu Du, Xiao-Dong Hu, Xiaohua Jia, Deying Li, Zheng Sun: Converter Placement Supporting Broadcast in WDM Optical Networks. 750-758
• 
  Thomas Blum, Christof Paar: High-Radix Montgomery Modular Exponentiation on Reconfigurable Hardware. 759-764
• 
  Correction to Editor's Note. 765

Volume 50, Number 8, August 2001

• 
  Ali R. Hurson, Bruce R. Childers: Message from the Guest Editors. 767-768
• 
  G. X. Tyson, M. Smelyanskyi, Edward S. Davidson: Evaluating the Use of Register Queues in Software Pipelined Loops. 769-783
• 
  Waleed Meleis, Alexandre E. Eichenberger, Ivan D. Baev: Scheduling Superblocks with Bound-Based Branch Trade-Offs. 784-797
• 
  Mahmut T. Kandemir, J. Ramanujam: Data Relation Vectors: A New Abstraction for Data Optimizations. 798-810
• 
  Sangman Moh, Chansu Yu, Ben Lee, Hee Yong Youn, Dongsoo Han, Dongman Lee: Four-Ary Tree-Based Barrier Synchronization for 2D Meshes without Nonmember Involvement. 811-823
• 
  Jaejin Lee, David A. Padua: Hiding Relaxed Memory Consistency with a Compiler. 824-833
• 
  Krishna M. Kavi, Roberto Giorgi, Joseph Arul: Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation. 834-846
• 
  Sang Jeong Lee, Pen-Chung Yew: On Table Bandwidth and Its Update Delay for Value Prediction on Wide-Issue ILP Processors. 847-852
• 
  Luís M. B. Lopes, Vasco Thudichum Vasconcelos, Fernando M. A. Silva: Fine-Grained Multithreading with Process Calculi. 852-862

Volume 50, Number 9, September 2001

• 
  Editor's Note. 863-864
• 
  Loren Schwiebert: Deadlock-Free Oblivious Wormhole Routing with Cyclic Dependencies. 865-876
• 
  Gang Han, Robert H. Klenke, James H. Aylor: Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems. 877-890
• 
  Bradley D. Brown, Howard C. Card: Stochastic Neural Computation I: Computational Elements. 891-905
• 
  Bradley D. Brown, Howard C. Card: Stochastic Neural Computation II: Soft Competitive Learning. 906-920
• 
  Tao Li, Lizy Kurian John: ADir_pNB: A Cost-Effective Way to Implement Full Map Directory-Based Cache Coherence Protocols. 921-934
• 
  Tsutomu Sasao, Jon T. Butler: Worst and Best Irredundant Sum-of-Products Expressions. 935-948
• 
  K. H. Yeung, Tak-Shing Yum: Dynamic Multiple Parity (DMP) Disk Array for Serial Transaction Processing. 949-959
• 
  Sun-Yuan Hsieh, Gen-Huey Chen, Chin-Wen Ho: Longest Fault-Free Paths in Star Graphs with Edge Faults. 960-971
• 
  Jun Kiniwa, Toshio Hamada, Daisuke Mizoguchi: Lookahead Scheduling Requests for Multisize Page Caching. 972-983
• 
  Anna Bernasconi, Bruno Codenotti, Jeffrey M. Vanderkam: A Characterization of Bent Functions in Terms of Strongly Regular Graphs. 984-985
• 
  Sungwook Yu, Earl E. Swartzlander Jr.: DCT Implementation with Distributed Arithmetic. 985-991
• 
  Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-fat Chan: A New Control Circuit for Asynchronous Micropipelines. 992-997
• 
  C. Liu, W.-B. Gong, C. M. Krishna: Rational Interpolation Examples in Performance Analysis. 997-1003

Volume 50, Number 10, October 2001

• 
  Koppolu Sasidhar, Abhijit Chatterjee, Yervant Zorian: Boundary Scan-Based Relay Wave Propagation Test of Arrays of Identical Structures. 1007-1019
• 
  Yuanyuan Yang, Jianchao Wang: Pipelined All-to-All Broadcast in All-Port Meshes and Tori. 1020-1032
• 
  David López, Josep Llosa, Mateo Valero, Eduard Ayguadé: Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. 1033-1051
• 
  Olivier Beaumont, Vincent Boudet, Antoine Petitet, Fabrice Rastello, Yves Robert: A Proposal for a Heterogeneous Cluster ScaLAPACK (Dense Linear Solvers). 1052-1070
• 
  M. Anwarul Hasan: Power Analysis Attacks and Algorithmic Approaches to Their Countermeasures for Koblitz Curve Cryptosystems. 1071-1083
• 
  Joan-Manuel Parcerisa, Antonio González: Improving Latency Tolerance of Multithreading through Decoupling. 1084-1094

• 
  Stefano Chessa, Piero Maestrini: Correct and Almost Complete Diagnosis of Processor Grids. 1095-1102

Volume 50, Number 11, November 2001

• 
  Haldun Hadimioglu, David R. Kaeli, Fabrizio Lombardi: Introduction to the Special Section on High Performance Memory Systems. 1103-1104
• 
  Maurice V. Wilkes: High Performance Memory Systems. 1105
• 
  Caroline Benveniste, Peter A. Franaszek, John T. Robinson: Cache-Memory Interfaces in Compressed Memory Systems. 1106-1116
• 
  Lixin Zhang, Zhen Fang, Michael A. Parker, Binu K. Mathew, Lambert Schaelicke, John B. Carter, Wilson C. Hsieh, Sally A. McKee: The Impulse Memory Controller. 1117-1132
• 
  Vinodh Cuppu, Bruce L. Jacob, Brian Davis, Trevor N. Mudge: High-Performance DRAMs in Workstation Environments. 1133-1153
• 
  Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Hardware and Software Techniques for Controlling DRAM Power Modes. 1154-1173
• 
  Kevin M. Lepak, Gordon B. Bell, Mikko H. Lipasti: Silent Stores and Store Value Locality. 1174-1190
• 
  Rui Min, Yiming Hu: Improving Performance of Large Physically Indexed Caches by Decoupling Memory Addresses from Cache Addresses. 1191-1201
• 
  Wei-Fen Lin, Steven K. Reinhardt, Doug Burger: Designing a Modern Memory Hierarchy with Hardware Prefetching. 1202-1218
• 
  Bülent Abali, Mohammad Banikazemi, Xiaowei Shen, Hubertus Franke, Dan E. Poff, T. Basil Smith: Hardware Compressed Main Memory: Operating System Support and Performance Evaluation. 1219-1233
• 
  Rajeev Barua, Walter Lee, Saman P. Amarasinghe, Anant Agarwal: Compiler Support for Scalable and Efficient Memory Systems. 1234-1247
• 
  Yan Solihin, Jaejin Lee, Josep Torrellas: Automatic Code Mapping on an Intelligent Memory Architecture. 1248-1266

• 
  Dhananjay S. Phatak, Tom Goff, Israel Koren: Constant-Time Addition and Simultaneous Format Conversion Based on Redundant Binary Representations. 1267-1278
• 
  Annie A. M. Cuyt, R. B. Lenin: Multivariate Rational Approximants for Multiclass Closed Queuing Networks. 1279-1288

• 
  Jawahar Jain, Ingo Wegener, Masahiro Fujita: A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs. 1289-1290
• 
  Mao-Hsu Yen, Sao-Jie Chen, Sanko Lan: A Three-Stage One-Sided Rearrangeable Polygonal Switching Network. 1291-1294

Volume 50, Number 12, December 2001

• 
  Yanhong A. Liu, Gustavo Gomez: Automatic Accurate Cost-Bound Analysis for High-Level Languages. 1295-1309
• 
  Minsoo Ryu, Jungkeun Park, Seongsoo Hong: Timing Constraint Remapping to Achieve Time Equi-Continuity in Distributed Real-Time Systems. 1310-1320
• 
  Mahmut T. Kandemir, J. Ramanujam, Alok N. Choudhary, Prithviraj Banerjee: A Layout-Conscious Iteration Space Transformation Technique. 1321-1336
• 
  Ivan Mura, Andrea Bondavalli: Markov Regenerative Stochastic Petri Nets to Model and Evaluate Phased Mission Systems Dependability. 1337-1351
• 
  Donghee Lee, Jongmoo Choi, Jong-Hun Kim, Sam H. Noh, Sang Lyul Min, Yookun Cho, Chong-Sang Kim: LRFU: A Spectrum of Policies that Subsumes the Least Recently Used and Least Frequently Used Policies. 1352-1361
• 
  José González, Antonio González: Control-Flow Speculation through Value Prediction. 1362-1376

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