Volume 45, Number 1, January 1996 Cellular Automata
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Error Correction and Detection
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Logic Design
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Privacy and Security
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Testing and Design for Testability
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Brief Contributions
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https://dblp.org/rec/journals/tc/RaiD96 Suresh Rai ,
Weian Deng :
Hyperneural Network-An Efficient Model for Test Generation in Digital Circuits. 115-121
Volume 45, Number 2, February 1996 Fault Tolerance
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Interconnection Network Topology
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Routing and Broadcasting Algorithms
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Theory and Algorithms
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Brief Contributions
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Volume 45, Number 3, March 1996 Built-In Self-Test
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Compiler Techniques
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https://dblp.org/rec/journals/tc/ChangL96 Meng-chou Chang ,
Feipei Lai :
Efficient Exploitation of Instruction-Level Parallelism for Superscalar Processors by the Conjugate Register File Scheme. 278-293
Subject Area
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https://dblp.org/rec/journals/tc/DawidM96 Herbert Dawid ,
Heinrich Meyr :
The Differential CORDIC Algorithm: Constant Scale Factor Redundant Implementation without Correcting Iterations. 307-318 share record
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https://dblp.org/rec/journals/tc/Kantabutra96 Vitit Kantabutra :
On Hardware for Computing Exponential and Trigonometric Functions. 328-339 share record
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Memory Management
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Brief Contributions
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https://dblp.org/rec/journals/tc/KunduSGT96 share record
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https://dblp.org/rec/journals/tc/Knor96 Martin Knor :
A Note on Radially Moore Digraphs. 381-383
Correction to Previous Paper
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Volume 45, Number 4, April 1996 Algorithm-Based Fault Tolerance and Result-Checking
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Consensus and Agreement
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Concurrent Error Detection
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Brief Contributions
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https://dblp.org/rec/journals/tc/Tragoudas96 Spyros Tragoudas :
Min-Cut Partitioning on Underlying Tree and Graph Structures. 470-474 export record
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https://dblp.org/rec/journals/tc/Vaidya96 Nitin H. Vaidya :
Comparison of Duplex and Triplex Memory Reliability. 503-507 share record
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Corrections
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Volume 45, Number 5, May 1996 Generalized Spectral Analysis
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https://dblp.org/rec/journals/tc/Corinthios96 Michael J. Corinthios :
A Weighted Z Spectrum, Parallel Algorithm, and Processors for Mathematical Model Estimation. 513-528
Interconnection Networks
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https://dblp.org/rec/journals/tc/Rajasekaran96 Sanguthevar Rajasekaran :
Mesh Connected Computers with Fixed and Reconfigurable Buses: Packet Routing and Sorting. 529-539 share record
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Memory and Memory Mangement
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Modeling and Performance Evaluation
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https://dblp.org/rec/journals/tc/KimS96 Jong Kim ,
Kang G. Shin :
Execution Time Analysis of Communicating Tasks in Distributed Systems. 572-579 share record
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Processor Architecture
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Brief Contributions
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Comments
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https://dblp.org/rec/journals/tc/Parhami96 Behrooz Parhami :
Comments on "High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits". 637-638 export record
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Volume 45, Number 6, June 1996 Fault Tolerant Communication
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Routing Algorithms and Switching Schemes
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Task Assignment
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Brief Contributions
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https://dblp.org/rec/journals/tc/LaiL96 K. Lai ,
Parag K. Lala :
Multiple Fault Detection in Fan-Out Free Circuits Using Minimal Single Fault Test Set. 763-765 export record
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journals/tc/Pearlmutter96 share record
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https://dblp.org/rec/journals/tc/Pearlmutter96 Barak A. Pearlmutter :
Doing the Twist: Diagonal Meshes Are Isomorphic to Twisted Toroidal Meshes. 766-767
Comments
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Volume 45, Number 7, July 1996 Cellular Automata
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Processor Design
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Real-Time Scheduling
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Theory and Algorithms
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Brief Contributions
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https://dblp.org/rec/journals/tc/Paar96 Christof Paar :
A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields. 856-861
Comments
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https://dblp.org/rec/journals/tc/Wei96 Bin Wei :
Comments on "A Multiaccess Frame Buffer Architecture". 862
Volume 45, Number 8, August 1996 Fault Tolerance
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Testing Algorithms, Methods and Tools
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https://dblp.org/rec/journals/tc/Majumdar96 Amitava Majumdar :
On Evaluating and Optimizing Weights for Weighted Random Pattern Testing. 904-916 share record
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Brief Contributions
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https://dblp.org/rec/journals/tc/Chakravarty96 Sreejit Chakravarty :
A Study of Theoretical Issues in the Synthesis of Delay Fault Testability Circuits. 985-991
Volume 45, Number 9, September 1996 Complexity Theory
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Encoding and Decoding
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https://dblp.org/rec/journals/tc/Lo96 Jien-Chung Lo :
A Hyper Optimal Encoding Scheme for Self-Checking Circuits. 1022-1030
Logic Design
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Brief Contributions
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https://dblp.org/rec/journals/tc/ZhangVD96 share record
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Volume 45, Number 10, October 1996 Computer Architecture
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Diagnosis and Testing
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Memory and Memory Menagement
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https://dblp.org/rec/journals/tc/Wang96 Zeng-ou Wang :
A Bidirectional Associative Memory Based on Optimal Linear Associative Memory. 1171-1179 share record
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Brief Contributions
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https://dblp.org/rec/journals/tc/Sahni96 Sartaj Sahni :
Scheduling Master-Slave Multiprocessor Systems. 1195-1199 share record
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