Volume 39, Number 1, January 1990

• 
  Jason Gait: A Checkpointing Page Store for Write-Once Optical Disk. 2-9
• 
  Ming-Syan Chen, Kang G. Shin, Dilip D. Kandlur: Addressing, Routing, and Broadcasting in Hexagonal Mesh Multiprocessors. 10-18
• 
  Myungwhan Choi, C. M. Krishna: An Adaptive Algorithm to Ensure Differential Service in aToken-Ring Network. 19-33
• 
  Pro Rong Chang, George Lee: A Decomposition Approach for Balancing Large-Scale Acyclic Data Flow Graphs. 34-46
• 
  Douglas M. Blough, Gerald M. Masson: Performance Analysis of a Generalized Concurrent Error Detection Procedure. 47-62
• 
  Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan: Design and Analysis of a Gracefully Degrading Interleaved Memory System. 63-71
• 
  Yoheved Dotan, Benjamin Arazi: Concurrent Logic Programming as a Hardware Description Tool. 72-88
• 
  Behrooz Parhami: Generalized Signed-Digit Number Systems: A Unifying Framework for Redundant Number Representations. 89-98
• 
  Kang G. Shin, Ming-Syan Chen: On the Number of Acceptable Task Assignments in Distributed Computing Systems. 99-110
• 
  Dik Lun Lee, Frederick H. Lochovsky: HYTREM - A Hybrid Text-Retrieval Machine for Large Databases. 111-123

• 
  Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Thio Fujisawa: Crossing Minimization in Linear Embeddings of Graphs. 124-127
• 
  David M. Mandelbaum: A Systematic Method for Division with High Average Bit Skipping. 127-130
• 
  Y. N. Srikant: Parallel Parsing of Arithmetic Expressions. 130-132
• 
  Philip Heidelberger, Alan Norton, John T. Robinson: Parallel Quicksort Using Fetch-and-Add. 133-138
• 
  Mark G. Karpovsky, Prawat Nagvajara: Optimal Robust Compression of Test Responses. 138-141
• 
  Youngju Won, Sartaj Sahni, Yacoub M. El-Ziq: A Hardware Accelerator for Maze Routing. 141-145
• 
  Jorge L. Aravena: Recursive Moving Window DFT Algorithm. 145-148
• 
  Martin L. Brady, Majid Sarrafzadeh: Stretching a Knock-Knee Layout for Multilayer Wiring. 148-151
• 
  L. Magnus Ewerbring, Franklin T. Luk: Computing the Singular Value Decomposition on the Connection Machine. 152-155
• 
  James Jacob, Nripendra N. Biswas: Further Comments on "Detection of Faults in Programmable Logic Arrays". 155-157

Volume 39, Number 2, February 1990

• 
  Krishna Kant, A. Ravichandran: Synthesizing Robust Data STructures - An Introduction. 161-173
• 
  Walid A. Najjar, Jean-Luc Gaudiot: Network Resilience: A Measure of Network Fault Tolerance. 174-181
• 
  Tein-Hsiang Lin, Kang G. Shin: Location of a Faulty Module in a Computing System. 182-194
• 
  Sampath Rangarajan, Donald S. Fussell, Miroslaw Malek: Built-In Testing of Integrated Circuit Wafers. 195-205
• 
  David M. Nicol, Paul F. Reynolds Jr.: Optimal Dynamic Remapping of Data Parallel Computations. 206-219
• 
  René David, Antoine Fuentes: Fault Diagnosis of RAM's from Random Testing Experiments. 220-229
• 
  V. Krishnamoorthy, Krishnaiyan Thulasiraman, M. N. S. Swamy: Incremental Distance and Diameter Sequences of a Graph: New Measures of Network Performance. 230-237
• 
  Merrill E. Isenman, Dennis Shasha: Performance and Architectural Issues for String Matching. 238-250
• 
  Binay Sugla, David A. Carlson: Extreme Area-Time Tradeoffs in VLSI. 251-257

• 
  Charles C. Wang, Dingyi Pei: A VLSI DEsign for Computing Exponentiations in GF(2^m) and Its Application to Generate Pseudorandom Number Sequences. 258-266
• 
  Ferng-Ching Lin, Kung Chen: On the Design of a Unidirectional Systolic Array for Key Enumeration. 266-267
• 
  A. Majumdar, C. S. Raghavendra, Melvin A. Breuer: Fault Tolerance in Linear Systolic Arrays Using Time Redundancy. 269-276
• 
  Robert Cypher, Jorge L. C. Sanz, L. Snyder: Algorithms for Image Component Labeling on SIMD Mesh-Connected Computers. 276-281
• 
  Yigal Brandman, Alon Orlitsky, John L. Hennessy: A Spectral Lower Bound Techniqye for the Size of Decision Trees and Two Level AND/OR Circuits. 282-287
• 
  René David: Comments on "Signature Analysis for Multiple Output Circuits". 287-288, (see: IEEE Transactions on Computers 35(9): 830-837 (1986))

Volume 39, Number 3, March 1990

• 
  Ahmed E. Kamal, V. Carl Hamacher: Utilizing Bandwidth Sharing in the Slotted Ring. 289-299
• 
  Arvind, Rishiyur S. Nikhil: Executing a Program on the MIT Tagged-Token Dataflow Architecture. 300-318
• 
  Hyunsoo Yoon, Kyungsook Y. Lee, Ming T. Liu: Performance Analysis of Multibuffered Packet-Switching Networks in Multiprocessor Systems. 319-327
• 
  Mahadev Satyanarayanan, Ellen H. Siegel: Parallel Communication in a Large Distributed Environment. 329-348
• 
  Gurindar S. Sohi: Instruction Issue Logic for High-Performance Interruptible, Multiple Functional Unit, Pipelines Computers. 349-359
• 
  Stanislaw J. Piestrak: Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. 360-374
• 
  Carsten Vogt: A Buffer-Based Method for storage Allocation in an Object-Oriented System. 375-383

• 
  Michael J. Quinn: Analysis and Implementation of Branch-and Bound Algorithms on a Hypercube Multicomputer. 384-387
• 
  Jien-Chung Lo, Suchai Thanawastien: On the Design of Combinational Totally Self-Checking I-out-of3 Code Checkers. 387-393
• 
  Wei-Ming Lin, Viktor K. Prasanna: A Note on the Linear Transformation Method for Systolic Array Design. 393-399
• 
  Sanjeev Saxena, P. C. P. Bhatt, V. C. Prasad: Efficient VLSI Parallel Algorithm for Delaunay Triangulation on Orthogonal Tree Network in Two and Three Dimensions. 400-404, (Correction: IEEE Transactions on Computers 40(1): 122 (1991))
• 
  Bong-Rad Choi, Kyu Ho Park, Myunghwan Kim: An Improved Hardware Implementation of the Fault-Tolerant Clock Synchronization Algorithm for Large Multiprocessor Systems. 404-407
• 
  Antonis M. Paschalis, Costas Efstathiou, Constantine Halatsis: An Efficient TSC 1-out-of-3 Code Checker. 407-411
• 
  Sung Je Hong: The Design of a Testable Parallel Multiplier. 411-416

Volume 39, Number 4, April 1990

• 
  Régis Leveugle, Gabriele Saucier: Optimized Synthesis of Concurrently Checked Controllers. 419-425
• 
  V. S. S. Nair, Jacob A. Abraham: Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays. 426-435
• 
  Vijay Balasubramanian, Prithviraj Banerjee: Compiler-Assisted Synthesis of Algorithm-Based Checking in Multiprocessors. 436-446
• 
  Mahadev Satyanarayanan, James J. Kistler, Puneet Kumar, Maria E. Okasaki, Ellen H. Siegel, David C. Steere: Coda: A Highly Available File System for a Distributed Workstation Environment. 447-459
• 
  Kun-Lung Wu, W. Kent Fuchs: Recoverable Distributed Shared Virtual Memory. 460-469
• 
  Dong Sam Ha, Vijay P. Kumar: On the Design of High-Yield Reconfigurable PLA's. 470-479
• 
  Vwani P. Roychowdhury, Jehoshua Bruck, Thomas Kailath: Efficient Algorithms for Reconfiguration in VLSI/WSI Arrays. 480-489
• 
  Shantanu Dutt, John P. Hayes: On Designing and Reconfiguring k-Fault-Tolerant Tree Architectures. 490-503
• 
  Jean Arlat, Karama Kanoun, Jean-Claude Laprie: Dependability Modeling and Evaluation of Software Fault-Tolerant Systems. 504-513
• 
  Parameswaran Ramanathan, Dilip D. Kandlur, Kang G. Shin: Hardware-Assisted Software Clock Synchronization for Homogeneous Distributed Systems. 514-524
• 
  Ravishankar K. Iyer, Luke T. Young, P. V. Krishna Iyer: Automatic Recognition of Intermittent Failures: An Experimental Study of Field Data. 525-537

• 
  Rajesh Gupta, Rajiv Gupta, Melvin A. Breuer: The BALLAST Methodology for Structured Partial Scan Design. 538-544
• 
  Kwang-Ting Cheng, Vishwani D. Agrawal: A Partial Scan Method for Sequential Circuits with Feedback. 544-549
• 
  Yuval Tamir, Marc Tremblay: High-Performance Fault-Tolerant VLSI Systems Using Micro Rollback. 548-554
• 
  Nirmal R. Saxena, Edward J. McCluskey: Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums. 554-559
• 
  Ming-Feng Chang, Weiping Shi, W. Kent Fuchs: Optimal Diagnosis Procedures for k-out-of-n Structures. 559-564
• 
  Mengly Chean, José A. B. Fortes: The Full-Use-of-Suitable-Spares (FUSS) Approach to Hardware Reconfiguration for Fault-Tolerant Processor Arrays. 564-571
• 
  Meera Balakrishnan, C. S. Raghavendra: On Reliability Modeling of Closed Fault-Tolerant Computer Systems. 571-575
• 
  James H. Barton, Edward W. Czeck, Zary Segall, Daniel P. Siewiorek: Fault Injection Experiments Using FIAT. 575-582
• 
  Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. 582-586
• 
  Dhiraj K. Pradhan, Sandeep K. Gupta, Mark G. Karpovsky: Aliasing Probability for Multiple Input Signature Analyzer. 586-591
• 
  Larry A. Dunning, Gur Dial, Murali R. Varanasi: Unidirectional Byte Error Detecting Codes for Computer Memory Systems. 592-595

Volume 39, Number 5, May 1990

• 
  Meiliu Lu, Du Zhang, Tadao Murata: Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets. 597-604
• 
  Franco P. Preparata, Jean Vuillemin: Practical Cellular Dividers. 605-614
• 
  Dipak Ghosal, Laxmi N. Bhuyan: Performance Evaluation of a Dataflow Architecture. 615-627
• 
  Thomas L. Casavant, Jon G. Kuhl: A Communicating Finite Automata Approach to Modeling Distributed Computation and Its Application to Distributed Decision-Making. 628-639
• 
  Cheng-Wen Wu, Peter R. Cappello: Easily Testable Iterative Logic Arrays. 640-652
• 
  P. C. Mathias, Lalit M. Patnaik: Systolic Evaluation of Polynomial Expressions. 653-665
• 
  Belle W. Y. Wei, Clark D. Thompson: Area-Time Optimal Adder Design. 666-675
• 
  Hon Fung Li, David K. Probst: Optimal VLSI Dictionary Machines Without Compress Instructions. 676-693

• 
  Wei-Kuan Shih, Sun Wu, Yue-Sun Kuo: Unifying Maximum Cut and Minimum Cut of a Planar Graph. 694-697
• 
  Spira Matic: Emulation of Hypercube Architecture on Nearest-Neighbor Mesh-Connected Processing Elements. 698-700
• 
  Daniel J. Rosenkrantz: Half-Hot State Assignments for Finite State Machines. 700-702
• 
  Mostafa H. Abd-El-Barr, Zvonko G. Vranesic: Cost Reduction in the CCD Realization of MVMT Function. 702-706
• 
  William Gale, Sumit Das, Clement T. Yu: Improvements to an Algorithm for Equipartitioning. 706-710
• 
  Steven J. Friedman, Kenneth J. Supowit: Finding the Optimal Variable Ordering for Binary Decision Diagrams. 710-713
• 
  Richard Beigel, John Gill: Sorting n Objects with a K-Sorter. 714-716
• 
  Heuey Ling: An Approach to Implementing Multiplication with Small Tables. 717-718
• 
  Paolo Ancilotti, Beatrice Lazzerini, Cosimo Antonio Prete, Maurizio Sacchi: A Distributed Commit Protocol for a Multicomputer System. 718-724

Volume 39, Number 6, June 1990

• 
  Milos D. Ercegovac, Tomás Lang: Redundant and On-Line CORDIC: Application to Matrix Triangularization and SVD. 725-740
• 
  Shiow-Chen Shyu, Victor O. K. Li: Performance Analysis of Static Locking in Distributed Database Systems. 741-751
• 
  Sandip Kundu, Sudhakar M. Reddy: On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. 752-761
• 
  Hideo Fujiwara: Computational Complexity of Controllability/Observability Problems for Combinational Circuits. 762-767
• 
  Mamoru Sasaki, Takahiro Inoue, Yuji Shirai, Fumio Ueno: Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations. 768-774
• 
  William J. Dally: Performance Analysis of k-Ary n-Cube Interconnection Networks. 775-785
• 
  Sivarama P. Dandamudi, Derek L. Eager: Hierarchical Interconnection Networks for Multicomputer Systems. 786-797
• 
  Arthur F. Champernowne, Louis B. Bushard, John T. Rusterholz, John R. Schomburg: Latch-to-Latch Timing Rules. 798-808
• 
  Robert Michael Owens, Mary Jane Irwin: Being Stingy with Multipliers. 809-818
• 
  John N. Daigle, Robert B. Kuehl, Joseph D. Langford: Queuing Analysis of an Optical Disk Jukebox Based Office System. 819-828

• 
  Abdou Youssef, Bruce W. Arden: Equivalence Between Functionality and Topology of Log N-Stage Banyan Networks. 829-832
• 
  Krishna R. Pattipati, Samir A. Shah: On the Computational Aspects of Performability Models of Fault-Tolerant Computer Systems. 832-836
• 
  Bruce L. Montgomery, B. V. K. Vijaya Kumar: Systematic Random Error Correcting and All Undirectional Error Detecting Codes. 836-840
• 
  Edmundo de Souza e Silva, Richard R. Muntz: A Note on the Computational Cost of the Linearizer Algorithm for Queueing Networks. 840-842
• 
  Jon T. Butler, Kriss A. Schueller: On the Equivalence of Cost Functions in the Design of Circuits by Costtable. 842-844
• 
  Xumin Nie, David A. Plaisted: Experimental Results on Subgoal Reordering. 845-848
• 
  Chin-Wen Ho, Richard C. T. Lee: A Parallel Algorithm for Solving Sparse Triangular Systems. 848-852

Volume 39, Number 7, July 1990

• 
  Flavio Bonomi: On Job Assignment for a Parallel System of Processor Sharing Queues. 858-869
• 
  Kang G. Shin: Minimal Order Loop-Free Routing Strategy. 870-881
• 
  Ference Belik: An Efficient Deadlock Avoidance Rechnique. 882-888
• 
  Hideharu Amano, Taisuke Boku, Tomohiro Kudoh: (SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations. 889-905
• 
  Krishna Kant: Performance Analysis of Real-Time Software Supporting Fault-Tolerant Operation. 906-918
• 
  Zhixi Fang, Peiyi Tang, Pen-Chung Yew, Chuan-Qi Zhu: Dynamic Processor Self-Scheduling for General Parallel Nested Loops. 919-929
• 
  Lindsay Kleeman: The Jitter Model for Metastability and Its Application to Redundant Synchronizers. 930-942

• 
  Che-Liang Yang: Constructing Optimal Procedures for Testing Series Systems. 943-945
• 
  John P. Fishburn: Clock Skew Optimization. 945-951
• 
  Wang-Chan Wong, Tatsuya Suda, Lubomir Bic: Performance Analysis of a Message-Oriented Knowledge-Base. 951-957
• 
  Jia-Shung Wang, Richard C. T. Lee: An Efficient Channel Routing Algorithm to Yield an Optimal Solution. 957-962
• 
  Shing-Tsaan Huang: Notes on Shuffle/Exchange Type Permutation Sets. 962-965
• 
  Kyungsook Y. Lee, Hyunsoo Yoon: The B-Network: A Multistage Interconnection Network with Backward Links. 966-969
• 
  Nirmal R. Saxena, Edward J. McCluskey: Analysis of Checksums, Extended-Precision Checksums, and Cyclic Redundancy Checks. 969-975
• 
  Ibrahim H. Önyüksel, Keki B. Irani: Markovian Queueing Network Models for Performance Analysis of a Single-Bus Multiprocessor System. 975-980

Volume 39, Number 8, August 1990

• 
  Pak K. Chan, Martine D. F. Schlag: Analysis and Design of CMOS Manchester Adders with Variable Carry-Skip. 983-992
• 
  Tony M. Carter, James E. Robertson: The Set Theory of Arithmetic Decomposition. 993-1005
• 
  Homayoon Sam, Arupratan Gupta: A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations. 1006-1015
• 
  Milos D. Ercegovac, Tomás Lang: Radix-4 Square Root Without Initial PLA. 1016-1024
• 
  Reza Hashemian: Square Rooting Algorithms for Integer and Floatingg-Point Numbers. 1025-1029
• 
  Israel Koren, Ofra Zinaty: Evaluating Elementary Functions in a Numerical Coprocessor Based on Rational Approximations. 1030-1037
• 
  Hai-Xiang Lin, Henk J. Sips: On-Line CORDIC Algorithms. 1038-1052
• 
  Chien-Chun Su, Hao-Yung Lo: An Algorithm for Scaling and Single Residue Error Correction in Residue Number Systems. 1053-1064
• 
  Neil M. Wigley, Graham A. Jullien: On Modulus Replication for Residue Arithmetic Computations of Complex Inner Products. 1065-1076
• 
  Mark G. Arnold, Thomas A. Bailey, John R. Cowles, Jerry J. Cupal: Redundant Logarithmic Arithmetic. 1077-1086
• 
  Jean Vuillemin: Exact Real Computer Arithmetic with Continued Fractions. 1087-1105
• 
  Peter Kornerup, David W. Matula: An Algorithm for Redundant Binary Bit-Pipelined Rational Arithmetic. 1106-1115

Volume 39, Number 9, September 1990

• 
  Insup Lee, Susan B. Davidson: A Performance Analysis of Times Synchronous Communication Primitives. 1117-1131
• 
  Prithviraj Banerjee, Joseph T. Rahmeh, Craig B. Stunkel, V. S. S. Nair, Kaushik Roy, Vijay Balasubramanian, Jacob A. Abraham: Algorithm-Based Fault Tolerance on a Hypercube Multiprocessor. 1132-1145
• 
  Ming-Syan Chen, Kang G. Shin: Subcube Allocation and Task Migration in Hypercube Multiprocessors. 1146-1155
• 
  Jen-Yao Chung, Jane W.-S. Liu, Kwei-Jay Lin: Scheduling Periodic Jobs That Allow Imprecise Results. 1156-1174
• 
  Lui Sha, Ragunathan Rajkumar, John P. Lehoczky: Priority Inheritance Protocols: An Approach to Real-Time Synchronization. 1175-1185
• 
  Wei Zhao, John A. Stankovic, Krithi Ramamritham: A Window Protocol for Transmission of Time-Constrained Messages. 1186-1203

• 
  Milos D. Ercegovac, Tomás Lang: Simple Radix-4 Division with Opterands Scaling. 1204-1208
• 
  Sakti Pramanik, Myoung-Ho Kim: Parallel Processing of Large Node B-Trees. 1208-1212

Volume 39, Number 10, October 1990

• 
  Jörg-Rüdiger Sack, Subhash Suri: An Optimal Algorithm for Detecting Weak Visibility of a Polygon. 1213-1219
• 
  Luigi Ciminiera, Paolo Montuschi: Higher Radix Square Rooting. 1220-1231
• 
  Flavio Bonomi, Anurag Kumar: Adaptive Optimal Load Balancing in a Nonhomogeneous Multiserver System with a Central Job Scheduler. 1232-1250
• 
  Gianfranco Ciardo, Raymond A. Marie, Bruno Sericola, Kishor S. Trivedi: Performability Analysis Using Semi-Markov Reard Processes. 1251-1264
• 
  Scot W. Hornick, Sanjeev R. Maddila, Ernst P. Mücke, Harald Rosenberger, Steven Skiena, Ioannis G. Tollis: Searching on a Tape. 1265-1272
• 
  Peter D. Hortensius, Robert D. McLeod, Howard C. Card: Cellular Automata-Based Signature analysis for Built-in Self-Test. 1273-1283

• 
  René David, Kenneth Wagner: Analysis of Detection Probability and Some Applications. 1284-1291
• 
  Andrea Bobbio, Kishor S. Trivedi: Computing Cumulative Measures of Stiff Markov Chains Using Aggregation. 1291-1298
• 
  Joo-Kang Lee, Jon T. Butler: A Characterization of t/s-Diagnosability an Sequential t-Diagnosability in Designs. 1298-1304
• 
  A. L. Narasimha Reddy, Prithviraj Banerjee: Algorithms-Based Fault Detection for Signal Processing Applications. 1304-1308

Volume 39, Number 11, November 1990

• 
  Edmundo de Souza e Silva, H. Richard Gail: Analyzing Scheduled Maintenance Policies for Repairable Computer Systems. 1309-1324
• 
  David M. Lewis: An Architecture for Addition and Subtraction of Long Word Length Numbers in the Logarithmic Number System. 1325-1336
• 
  David M. Nicol, Joel H. Saltz: An Anlysis of Scatter Decomposition. 1337-1345
• 
  Joe Kilian, Shlomo Kipnis, Charles E. Leiserson: The Organization of Permutation Architectures with Bused Interconnections. 1346-1358
• 
  Chaitali Chakrabarti, Joseph JáJá: Systolic Architectures for the Computation of the Discrete Hartley and the Discrete Cosine Transforms Based on Prime Factor Decomposition. 1359-1368
• 
  Sreejit Chakravarty, Harry B. Hunt III: On Computing Signal Probability and Detection Probability of Stuck-at Faults. 1369-1377

• 
  Abhijit Chatterjee, Jacob A. Abraham: The Testability of Generalized Counters Under Multiple Faulty Cells. 1378-1385
• 
  Milos D. Ercegovac, Tomás Lang: Fast Multiplication Without Carry-Propagate Addition. 1385-1390
• 
  Bradley C. Kusxmaul: Fast, Deterministic Routing, on Hypercubes, Using Small Buffers. 1390-1393
• 
  Alain J. Martin, Jan L. A. van de Snepscheut: An Interconnection Network for Distributed Recursive Computations. 1393-1395
• 
  Majid Sarrafzadeh: Area Minimization in a Three-Sided Switchbox by Sliding the Modules. 1395-1403
• 
  Jay W. Schwartz, Jack K. Wolf: A Systematic (12, 8) Code for Correcting Single Errors and Detecting Adjacent Errors. 1403-1404

Volume 39, Number 12, December 1990

• 
  Ming-Syan Chen, Kang G. Shin: Adaptive Fault-Tolerant Routing in Hypercube Multicomputers. 1406-1416
• 
  Christopher J. Zarowski, Howard C. Card: On Addition and Multiplication with Hensel Codes. 1417-1423
• 
  Tony M. Carter, James E. Robertson: Radix-16 Signed-Digit Division. 1424-1433
• 
  Barry S. Fagin, Alvin M. Despain: The Performance of Parallel Prolog Programs. 1434-1445
• 
  Rami G. Melhem, Ghil-Young Hwang: Embedding Rectangular Grids into Square Grids with Dilation Two. 1446-1455
• 
  Kwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A Simulation-Based Method for Generating Tests for Sequential Circuits. 1456-1463

• 
  Krzysztof Sapiecha, R. Jarocki: Modular Architecture for High Performance Implementatin of the FFT Algorithm. 1464-1468
• 
  Chang-Biau Yang, Richard C. T. Lee, Wen-Tsuen Chen: Parallel Graph Algorithms Based Upon Broadcast Communications. 1468-1472
• 
  Arun K. Somani: Sequential Fault Occurrence and Reconfiguration in System Level Diagnosis. 1472-1475
• 
  Steven D. Kugelmass, Kenneth Steiglitz: An Upper Bound on Expected Clock Skew in Synchronous Systems. 1475-1477
• 
  Fabrizio Lombardi, Wei-Kang Huang: Fault Detection and Design Complextity in C-Testable VLSI Arrays. 1477-1481
• 
  Nripendra N. Biswas, Sampalli Srinivas: A Reconfigurable Tree Architecture with Multistage Interconnection Network. 1481-1485
• 
  Wei-Kang Huang, Fabrizio Lombardi: On the Constant Diagnosability of Baseline Interconnection Networks. 1485-1488

last updated on Sat May 25 06:42:29 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page