Volume 32, Number 1, January 1983

• 
  Zary Segall, Ajay Singh, Richard T. Snodgrass, Anita K. Jones, Daniel P. Siewiorek: An Integrated Instrumentation Environment for Multiprocessors. 4-14
• 
  Hansjörg Fromm, Uwe Hercksen, Ulrich Herzog, Karl-Heinz John, Rainer Klar, Wolfgang Kleinöder: Experiences with Performance Measurement and Modeling of a Processor Array. 15-31
• 
  Dennis Parkinson, Heather M. Liddell: The Measurement of Performance on a Highly Parallel System. 32-37
• 
  Phil C. C. Yeh, Janak H. Patel, Edward S. Davidson: Shared Cache for Multiple-Stream Computer Systems. 38-47
• 
  Faye A. Briggs, Michel Dubois: Effectiveness of Private Caches in Multiprocessor Systems with Parallel-Pipelined Memories. 48-59
• 
  Marco Ajmone Marsan, Gianfranco Balbo, Gianni Conte, Francesco Gregoretti: Modeling Bus Contention and Memory Interference in a Multiprocessor System. 60-72
• 
  Philip Heidelberger, Kishor S. Trivedi: Analytic Queueing Models for Programs with Internal Concurrency. 73-82
• 
  Daniel A. Reed, Herbert D. Schwetman: Cost-Performance Bounds for Multimicrocomputer Networks. 83-95

• 
  Isi Mitrani, Peter J. B. King: Multiserver-Systems Subject to Breakdowns: An Empirical Study. 96-98

Volume 32, Number 2, February 1983

• 
  Gordon K. Lin, Premachandran R. Menon: Totally Preset Checking Experiments for Sequential Machines. 101-108
• 
  Tomás Lozano-Pérez: Spatial Planning: A Configuration Space Approach. 108-120
• 
  Gregor von Bochmann, Michel Raynal: Structured Specification of Communicating Systems. 120-133
• 
  Yaron I. Gold, William R. Franta, Shlomo Moran: A Distributed Channel-Access Protocol for Fully-Connected Networks with Mobile Nodes. 133-147
• 
  Gilles H. Garcia, William J. Kubitz: Minimum Mean Running Time Function Generation Using Read-Only Memory. 147-156
• 
  Michael J. Flynn, Lee W. Hoevel: Execution Architecture: The DELtran Experiment. 156-175
• 
  Allan Gottlieb, Ralph Grishman, Clyde P. Kruskal, Kevin P. McAuliffe, Larry Rudolph, Marc Snir: The NYU Ultracomputer - Designing an MIMD Shared Memory Parallel Computer. 175-189
• 
  Zeev Barzilai, Don Coppersmith, Arnold L. Rosenberg: Exhaustive Generation of Bit Patterns with Applications to VLSI Self-Testing. 190-194

• 
  Franco P. Preparata: A Mesh-Connected Area-Time Optimal VLSI Multiplier of Large Integers. 194-198
• 
  Alfred K. Susskind: Testing by Verifying Walsh Coefficients. 198-201
• 
  John P. Robinson: Addendum to "Optimum Golomb Rulers". 201
• 
  D. J. Evans, R. C. Dunbar: The Parallel Solution of Triangular Systems of Equations. 201-204
• 
  Alexander R. Bazelow, Jaan Raamot: On the Microprocessor Solution of Ordinary Differential Equations Using Integer Arithmetic. 204-207

Volume 32, Number 3, March 1983

• 
  Raghunath Raghavan, Sartaj Sahni: Single Row Routing. 209-220
• 
  C. V. Ramamoorthy, Benjamin W. Wah: The Isomorphism of Simple File Allocation. 221-232
• 
  Laurence J. Laning, Michael S. Leonard: File Allocation in a Distributed Computer Communication Network. 232-244
• 
  Carol A. Niznik: A Quantization Approximation for Modeling Computer Network Nodal Queueing Delay. 245-253
• 
  Manoj Kumar, Daniel S. Hirschberg: An Efficient Implementation of Batcher's Odd-Even Merge Algorithm and Its Application in Parallel Sorting Schemes. 254-264
• 
  Christopher P. Arnold, Michael I. Parr, Michael B. Dewe: An Efficient Parallel Algorithm for the Solution of Large Sparse Linear Matrix Equations. 265-273
• 
  Nikolaos Gaitanis, Constantine Halatsis: A New Design Method for m-Out-of-n TSC Checkers. 273-283
• 
  Donald F. Wann, Mark A. Franklin: Asynchronous and Clocked Control Structures for VSLI Based Interconnection Networks. 284-293
• 
  Jean Vuillemin: A Combinatorial Limit to the Computing Power of VLSI Circuits. 294-300

• 
  Trieu-Kien Truong, K. Y. Liu, Irving S. Reed: A Parallel-Pipeline Architecutre of the Fast Polynomial Transform for Computing a Two-Dimensional Cyclic Convolution. 301-306
• 
  Eliezer Dekel, Sartaj Sahni: Binary Trees and Parallel Scheduling Algorithms. 307-315
• 
  Kuang-Wei Chiang, Zvonko G. Vranesic: A Tree Representation of Combinational Networks. 315-319
• 
  Dhiraj K. Pradhan: Sequential Network Design Using Extra Inputs for Fault Detection. 319-323
• 
  Asok Bhattacharyya: On a Novel Approach of Fault Detection in an Easily Testable Sequential Machine with Extra Inputs and Extra Outputs. 323-325
• 
  Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala: Error-Correcting Codes in Binary-Coded Radix-r Arithmetik. 326-328

Volume 32, Number 4, April 1983

• 
  E. V. Krishnamurthy: On the Conversion of Hensel Codes to Farey Rationals. 331-337
• 
  Antoine Froment: Error Free Computation: A Direct Method to Convert Finite-Segment p-Adic Numbers into Rational Numbers. 337-343
• 
  Nai-Kuan Tsao: A Simple Approach to the Error Analysis of Division-Free Numerical Algorithms. 343-351
• 
  Osaaki Watanuki, Milos D. Ercegovac: Error Analysis of Certain Floating-Point On-Line Algorithms. 352-358
• 
  Shauchi Ong, Daniel E. Atkins: A Basis for the Quantitative Comparison of Computer Number Systems. 359-369
• 
  Marty S. Cohen, Thomas E. Hull, V. Carl Hamacher: CADAC: A Controlled-Precision Decimal Arithmetic Unit. 370-377
• 
  Peter Kornerup, David W. Matula: Finite Precision Rational Arithmetic: An Arithmetic Unit. 378-388, (Correction: IEEE Transactions on Computers 33(7): 682 (1984))
• 
  W. Kenneth Jenkins: The Design of Error Checkers for Self-Checking Residue Number Arithmetic. 388-396

• 
  E. V. Krishnamurthy, Venu K. Murthy: Fast Iterative Division of p-adic Numbers. 396-398
• 
  C. H. Huang: A Fully Parallel Mixed-Radix Conversion Algorithm for Resedue Number Applications. 398-402
• 
  Mary Jane Irwin, Robert Michael Owens: Fully Digit On-Line Networks. 402-406
• 
  Robert Michael Owens: Techniques to Reduce the Inherent Limitations of Fully Digit On-Line Arithmetic. 406-411
• 
  Daniel W. Lozier: The Use of Floating-Point and Interval Arithmetic in the Computation of Error Bounds. 411-417
• 
  Janak H. Patel, Leona Y. Fung: Concurrent Error Detection in Multiply and Divide Arrays. 417-422

Volume 32, Number 5, May 1983

• 
  Joseph E. Requa, James R. McGraw: The Piecewise Data Flow Architecture: Architectural Concepts. 425-438
• 
  K. S. Ramanatha, Nripendra N. Biswas: An On-Line Algorithm for the Location of Cross Point Faults in Programmable Logic Arrays. 438-444
• 
  David Steinberg: Invariant Properties of the Shuffle-Exchange and a Simplified Cost-Effective Version of the Omega Network. 444-450
• 
  Alexandre Brandwajn: Models of DASD Subsystems with Multiple Access Paths: A Throughput-Driven Approach. 451-463
• 
  K. V. S. S. Prasad Rao, Dhruba Basu: Design of Totally Self-Checking Circuits with an Unrestricted Stuck-At Fault-Set Using Redundancy in Space and Time Domains. 464-475

• 
  James Leslie Keedy: An Instruction Set for Evaluating Expressions. 476-478
• 
  Marco Mezzalama, Paolo Prinetto: A Hierarchical Description Model for Microcode. 478-487
• 
  Philipp W. Besslich: A Method for the Generation and Processing of Dyadic Indexed Data. 487-494
• 
  Nikolaos Gaitanis, Constantin Halatsis: Near-Perfect Codes for Binary-Coded Radix-r Arithmetic Units. 494-497
• 
  G. R. Blakley: A Computer Algorithm for Calculating the Product AB Modulo M. 497-500
• 
  Fred J. Taylor: An Overflow-Free Residue Multiplier. 501-504
• 
  Vijaya Ramachandran: Single Residue Error Correction in Residue Number Systems. 504-507
• 
  Constantine Halatsis, Nikolaos Gaitanis, Maria Sigala: Fast and Efficient Totally Self-Checking Checkers for m-out-of-(2m ±1) Codes. 507-511
• 
  Teruhiko Yamada, Takashi Nanya: Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines". 511-512
• 
  Denise Amar: On the Connectivity of Some Telecommunications Networks. 512-519

Volume 32, Number 6, June 1983

• 
  Louis B. Bushard: A Minimum Table Size Result for Higher Radix Nonrestoring Division. 521-526
• 
  Earl E. Swartzlander Jr., D. V. Satish Chandra, H. Troy Nagle Jr., Scott A. Starks: Sign/Logarithm Arithmetic for FFT Implementation. 526-534
• 
  Larry A. Dunning, Murali R. Varanasi: Code Constructions for Error Control in Byte Organized Memory Systems. 535-542
• 
  Kostas N. Oikonomou, Richard Y. Kain: Abstractions for Node Level Passive Fault Detection in Distributed Systems. 543-550
• 
  K. S. Ramanatha, Nripendra N. Biswas: A Design for Testability of Undetectable Crosspoint Faults in Programmable Logic Arrays. 551-557
• 
  Robert J. Sheraga, John L. Gieser: Experiments in Automatic Microcode Generation. 557-569
• 
  Dhruva Nath, S. N. Maheshwari, P. C. P. Bhatt: Efficient VLSI Networks for Parallel Processing Based on Orthogonal Trees. 569-581

• 
  Ellis Horowitz, Alessandro Zorat: Divide-and-Conquer for Parallel Processing. 582-585
• 
  David A. Carlson: Time-Space Tradeoffs on Back-to-Back FFT Algorithms. 585-589
• 
  Zenon D. Ulman: Sign Detection and Implicit-Explicit Conversion of Numbers in Residue Arithmetic. 590-594
• 
  A. R. Virupakshia, V. C. V. Pratapa Reddy: A Simple Random Test Procedure for Detecion of Single Intermittent Fault in Combinational Circuits. 594-597
• 
  Robert G. Cantarella: The Reliability of Periodically Repaired n - l/n Parallel Redundant Systems. 597-598

Volume 32, Number 7, July 1983

• 
  José C. Barros, Brian W. Johnson: Equivalence of the Arbiter, the Synchronizer, the Latch, and the Inertial Delay. 603-614
• 
  Chin-Long Chen: Error-Correcting Codes with Byte Error-Detection Capability. 615-621
• 
  Michael C. McFarland, Alice C. Parker: An Abstract Model of Behavior for Hardware Descriptions. 621-637
• 
  Dharma P. Agrawal: Graph Theoretical Analysis and Design of Multistage Interconnection Networks. 637-648
• 
  Gerald M. Masson, S. Brent Morris: Expected Capacity of (m over 2)-Networks. 649-657
• 
  Christoph von Conta: Torus and Other Networks as Communication Networks With Up to Some Hundred Points. 657-666
• 
  Jean-Loup Baer, Hung-Chang Du, Richard E. Ladner: Binary Search in a Multiprocessing Environment. 667-677
• 
  Leon E. Winslow, Yuan-Chieh Chow: The Analysis and Design of Some New Sorting Machines. 677-683
• 
  Gérard M. Baudet, Franco P. Preparata, Jean Vuillemin: Area-Time Optimal VLSI Circuits for Convolution. 684-688

• 
  K. O. Siomalas, B. A. Bowen: Performance of Cross-Bar Multiprocessor Systems. 689-695
• 
  Alexander Miczo: A Self-Test Hardwired Control Section. 695-696

Volume 32, Number 8, August 1983

• 
  Bernard Chazelle: The Bottom-Left Bin-Packing Heuristic: An Efficient Implementation. 697-707
• 
  Tomás Lang, Mateo Valero, Miguel Angel Fiol: Reduction of Connections for Multibus Organization. 707-716
• 
  Shuji Tasaka: Stability and Performance of the R-ALOHA Packet Broadcast System. 717-726
• 
  John J. Metzner: A Parity Structure for Large Remotely Located Replicated Data Files. 727-730
• 
  Neil Weste, David J. Burr, Bryan D. Ackland: Dynamic Time Warp Pattern Matching Using an Integrated Multiprocessing Array. 731-744

• 
  Nuno Bandeira, Ken Vaccaro, James A. Howard: A Two's Complement Array Multiplier Using True Values of the Operands. 745-747
• 
  Ranjan Chaudhuri, Son Pham, Oscar N. Garcia: Solution of an Open Problem on Probabilistic Grammars. 748-750
• 
  Gian Carlo Bongiovanni: Two VLSI Structures for the Discrete Fourier Transform. 750-754
• 
  Sharad C. Seth, Lester Lipsky: A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. 754-760
• 
  Werner Bux: Analysis of a Local-Area Bus System with Controlled Access. 760-763
• 
  Wesley W. Chu, Wilhelm Haller, Kin K. Leung: Reservation Channel Access Protocol for High Speed Local Networks with Star Configurations. 763-766
• 
  P. V. Afshari, Steven C. Bruell, Richard Y. Kain: On the Load Balancing Bus Accessing Scheme. 766-770
• 
  Curtis Abbott: A Symbolic Simulator for Microprogram Development. 770-774
• 
  A. F. Bashir, V. Susarla, K. Vairavan: A Statistical Study of the Performance of a Task Scheduling Algorithm. 774-777
• 
  Anton T. Dahbura, Gerald M. Masson: Greedy Diagnosis of Hybrid Fault Situations. 777-782
• 
  Makoto Imase, Masaki Itoh: A Design for Directed Graphs with Minimum Diameter. 782-784

Volume 32, Number 9, September 1983

• 
  Witold S. Wojciechowski, Anthony S. Wojcik: Automated Design of Multiple-Valued Logic Circuits by Automatic Theorem Proving Techniques. 785-798
• 
  Timothy C. K. Chou, Jacob A. Abraham: Load Redistribution Under Failure in Distributed Systems. 799-808
• 
  Thomas F. Schwab, Stephen S. Yau: An Algebraic Model of Fault-Masking Logic Circuits. 809-825
• 
  Quentin F. Stout: Mesh-Connected Computers with Broadcasting. 826-830
• 
  James E. Smith, Paklin Lam: A Theory of Totally Self-Checking System Design. 831-844
• 
  Inder S. Gopal, Don Coppersmith, C. K. Wong: Optimal Wiring of Movable Terminals. 845-858

• 
  Makoto Kobayashi: Dynamic Profile of Instruction Sequences for the IBM System/370. 859-861
• 
  Leslie G. Valiant: Optimality of a Two-Phase Strategy for Routing in Interconnection Networks. 861-863
• 
  Chamarty D. V. P. Rao, Nripendra N. Biswas: On the Minimization of Wordwidth in the Control Memory of a Microprogrammed Digital Computer. 863-868
• 
  Martin de Prycker: Representing the Effect of Instruction Prefetch in a Microprocessor Performance Model. 868-872
• 
  Murali R. Varanasi, T. R. N. Rao, Son Pham: Memory Package Error Detection and Correction. 872-874
• 
  Trieu-Kien Truong, Irving S. Reed, C.-S. Yeh, Howard M. Shao: A Parallel Architecture for Digital Filtering Using Fermat Number Transforms. 874-877
• 
  R. Gnanasekaran: On a Bit-Serial Input and Bit-Serial Output Multiplier. 878-880

Volume 32, Number 10, October 1983

• 
  Eric M. Aupperle: Merit's Evolution - Statistically Speaking. 881-902
• 
  Arnold L. Rosenberg: The Diogenes Approach to Testable Fault-Tolerant Arrays of Processors. 902-910
• 
  A. Pedar, V. V. S. Sarma: Architecture Optimization of Aerospace Computing Systems. 911-922
• 
  Sadahiro Isoda, Yoshizumi Kobayashi, Toru Ishida: Global Compaction of Horizontal Microprogams Based on the Generalized Data Dependency Graph. 922-933
• 
  Roger W. Hockney: Characterizing Computers and Optimizing the FACR(l) Poisson-Solver on Parallel Unicomputers. 933-941
• 
  Clyde P. Kruskal: Searching, Merging, and Sorting in Parallel Computation. 942-946
• 
  Daniel Brand: Redundancy and Don't Cares in Logic Synthesis. 947-952

• 
  Anton T. Dahbura, Gerald M. Masson: Greedy Diagnosis as the Basis of an Intermittent-Fault/Transient-Upset Tolerant System Design. 953-957
• 
  El Mostapha Aboulhamid, Eduard Cerny: A Class of Test Generators for Built-In Testing. 957-959
• 
  Jacob Savir: A New Empirical Test for the Quality of Random Integer Generators. 960-961
• 
  Christos A. Papachristou: Direct Implementation of Discrete and Residue-Based Functions Via Optimal Encoding: A Programmable Array Logic Approach. 961-968
• 
  Akito Sakurai, Saburo Muroga: Parallel Binary Adders with a Minimum Number of Connections. 969-976

Volume 32, Number 11, November 1983

• 
  Yuval Tamir, Carlo H. Séquin: Strategies for Managing the Register File in RISC. 977-989
• 
  Hari K. Nagpal, Graham A. Jullien, William C. Miller: Processor Architectures for Two-Dimensional Convolvers Using a Single Multiplexed Computational Element with Finite Field Arithmetic. 989-1001
• 
  Werner E. Kluge: Cooperating Reduction Machines. 1002-1012
• 
  Dale D. Miller, John N. Polky: A Residue Number System Implementation of the LMS Algorithm Using Optical Waveguide Circuits. 1013-1028
• 
  Gabriel M. Silberman: Delayed-Staging Hierarchy Optimization. 1029-1037
• 
  Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara: An Easily Testable Design of Programmable Logic Arrays for Multiple Faults. 1038-1046
• 
  Clark D. Thompson: Fourier Transforms in VLSI. 1047-1057

• 
  D. Michael Miller, Jon C. Muzio: Spectral Fault Signatures for Internally Unate Combinational Networks. 1058-1062
• 
  Simon S. Lam: A Simple Derivation of the MVA and LBANC Algorithms from the Convolution Algorithm. 1062-1064
• 
  Wm. Randolph Franklin: Efficient Iterated Rotation of an Object. 1064-1067
• 
  Per-Erik Danielsson: A Variable-Lengt Shift-Register. 1067-1069
• 
  Subhash C. Kak: A Structural Redundancy in d-Sequences. 1069-1071
• 
  Meng-Hee Teng: Comments on "The Prime Memory Systems for Array Access". 1072

Volume 32, Number 12, December 1983

• 
  Vijay Pitchumani, Edward P. Stabler: An Inductive Assertion Method for Register Transfer Level Design Verification. 1073-1080
• 
  Laxmi N. Bhuyan, Dharma P. Agrawal: Design and Performance of Generalized Interconnection Networks. 1081-1090
• 
  Clyde P. Kruskal, Marc Snir: The Performance of Multistage Interconnection Networks for Multiprocessors. 1091-1098
• 
  Krishnan Padmanabhan, Duncan H. Lawrie: A Class of Redundant Path Multistage Interconnection Networks. 1099-1108
• 
  Mandayam A. Srinivas: Optimal Parallel Scheduling of Gaussian Elimination DAG's. 1109-1117
• 
  Robert Geist, Kishor S. Trivedi: Ultrahigh Reliability Prediction for Fault-Tolerant Computer Systems. 1118-1127
• 
  Paul Chow, Zvonko G. Vranesic, Jui Lin Yen: A Pipelined Distributed Arithmetic PFFT Processor. 1128-1136
• 
  Hideo Fujiwara, Takeshi Shimono: On the Acceleration of Test Generation Algorithms. 1137-1144
• 
  Donald T. Tang, Lin S. Woo: Exhaustive Test Pattern Generation with Constant Weight Vectors. 1145-1150
• 
  Özalp Babaoglu, Domenico Ferrari: Two-Level Replacement Decisions in Paging Stores. 1151-1159
• 
  Philip S. Liu, Tzay Y. Young: VLSI Array Design Under Constraint of Limited I/O Bandwidth. 1160-1170
• 
  Clark D. Thompson: The VLSI Complexity of Sorting. 1171-1184

• 
  David W. Twigg: Transposition of Matrix Stored on Sequential File. 1185-1188
• 
  Steven M. Kramer, Deepinder P. Sidhu: Security Information Flow in Multidimensional Arrays. 1188-1191
• 
  Ralph Grishman, Bogong Su: A Preliminary Evaluatin of Trace Scheduling for Global Microcode Compaction. 1191-1194
• 
  Mark G. Karpovsky: Universal Tests for Detection of Input/Output Stuck-At and Bridging Faults. 1194-1198
• 
  Jacob Savir: Good Controllability and Observability Do Not Guarantee Good Testability. 1198-1200
• 
  C. E. Veni Madhavan, S. Krishna: Comments on "Optimal Design of Distributed Information Systems". 1200-1201
• 
  Kevin W. Bowyer, C. Frank Starmer: Optimizing Contiguous-Element Region Selection for Virtual Memory Systems. 1201-1203
• 
  Francis Y. L. Chin, Cao An Wang: Optimal Algorithms for the Intersection and the Minimum Distance Problems Between Planar Polygons. 1203-1207
• 
  Thomas J. Chaney: Measured Flip-Flop Responses to Marginal Triggering. 1207-1209
• 
  Ralph Kallman: A Faster 8-Bit Carry Circuit. 1209-1211
• 
  Bernard M. E. Moret, Michael G. Thomason, Rafael C. Gonzalez: Symmetric and Threshold Boolean Functions Are Exhaustive. 1211-1212

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