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ORCIDACM Transactions on Architecture and Code Optimization, Volume 10
Volume 10, Number 1, April 2013
- Yunji Chen
, Tianshi Chen, Ling Li, Ruiyang Wu, Dao-Fu Liu, Weiwu Hu:
Deterministic Replay Using Global Clock. 1:1-1:28 - Daniel Lustig, Abhishek Bhattacharjee, Margaret Martonosi:
TLB Improvements for Chip Multiprocessors: Inter-Core Cooperative Prefetchers and Shared Last-Level TLBs. 2:1-2:38 - Rong Chen, Haibo Chen:
Tiled-MapReduce: Efficient and Flexible MapReduce Processing on Multicore with Tiling. 3:1-3:30 - Michela Becchi, Patrick Crowley:
A-DFA: A Time- and Space-Efficient DFA Compression Algorithm for Fast Regular Expression Evaluation. 4:1-4:26 - Sheng Li, Jung Ho Ahn, Richard D. Strong, Jay B. Brockman, Dean M. Tullsen, Norman P. Jouppi:
The McPAT Framework for Multicore and Manycore Architectures: Simultaneously Modeling Power, Area, and Timing. 5:1-5:29
Volume 10, Number 2, May 2013
- Angeliki Kritikakou, Francky Catthoor, George Athanasiou, Vasilios I. Kelefouras, Costas E. Goutis:
Near-Optimal Microprocessor and Accelerators Codesign with Latency and Throughput Constraints. 6:1-6:25 - Lei Jiang, Yu Du, Bo Zhao, Youtao Zhang, Bruce R. Childers, Jun Yang:
Hardware-Assisted Cooperative Integration of Wear-Leveling and Salvaging for Phase Change Memory. 7:1-7:25 - Kyuseung Han, Junwhan Ahn, Kiyoung Choi:
Power-Efficient Predication Techniques for Acceleration of Control Flow Execution on CGRA. 8:1-8:25 - Chao Wang, Xi Li, Junneng Zhang, Xuehai Zhou, Xiaoning Nie:
MP-Tomasulo: A Dependency-Aware Automatic Parallel Execution Engine for Sequential Programs. 9:1-9:26
Volume 10, Number 3, September 2013
- TACO Reviewers 2012. 9:1-9:2
- Eran Shifer, Shlomo Weiss:
Low-latency adaptive mode transitions and hierarchical power management in asymmetric clustered cores. 10:1-10:25 - Yosi Ben-Asher, Nadav Rotem:
Hybrid type legalization for a sparse SIMD instruction set. 11:1-11:14 - Yuanwu Lei, Yong Dou, Lei Guo, Jinbo Xu, Jie Zhou, Yazhuo Dong, Hongjian Li:
VLIW coprocessor for IEEE-754 quadruple-precision elementary functions. 12:1-12:22 - Motohiro Kawahito, Hideaki Komatsu, Takao Moriyama, Hiroshi Inoue, Toshio Nakatani:
Idiom recognition framework using topological embedding. 13:1-13:34 - Ghassan Shobaki, Maxim Shawabkeh, Najm Eldeen Abu Rmaileh:
Preallocation instruction scheduling with register pressure minimization using a combinatorial optimization approach. 14:1-14:31 - Dongrui She, Yifan He, Henk Corporaal:
An energy-efficient method of supporting flexible special instructions in an embedded processor with compact ISA. 15:1-15:25 - V. Krishna Nandivada, Rajkishore Barik:
Improved bitwidth-aware variable packing. 16:1-16:22 - Jung Ho Ahn, Young Hoon Son, John Kim:
Scalable high-radix router microarchitecture using a network switch organization. 17:1-17:25 - Libo Huang, Zhiying Wang, Nong Xiao, Yongwen Wang, Qiang Dou:
Adaptive communication mechanism for accelerating MPI functions in NoC-based multicore processors. 18:1-18:25 - Avinash Malik, David Gregg:
Orchestrating stream graphs using model checking. 19:1-19:25 - Zheng Wang, Michael F. P. O'Boyle:
Using machine learning to partition streaming programs. 20:1-20:25 - Ali Bakhoda, John Kim, Tor M. Aamodt:
Designing on-chip networks for throughput accelerators. 21:1-21:35
Volume 10, Number 4, December 2013
- Michael R. Jantz, Prasad A. Kulkarni:
Exploring single and multilevel JIT compilation policy for modern machines. 22:1-22:29 - Xiangyu Dong, Norman P. Jouppi, Yuan Xie:
A circuit-architecture co-optimization framework for exploring nonvolatile memory hierarchies. 23:1-23:22 - Jishen Zhao, Guangyu Sun, Gabriel H. Loh, Yuan Xie:
Optimizing GPU energy efficiency with 3D die-stacking graphics memory and reconfigurable memory interface. 24:1-24:25 - Chien-Chi Chen, Sheng-De Wang:
An efficient multicharacter transition string-matching engine based on the aho-corasick algorithm. 25:1-25:22 - Yangchun Luo, Wei-Chung Hsu, Antonia Zhai:
The design and implementation of heterogeneous multicore systems for energy-efficient speculative thread execution. 26:1-26:29 - Dyer Rolán, Basilio B. Fraguela, Ramon Doallo:
Virtually split cache: An efficient mechanism to distribute instructions and data. 27:1-27:24 - Samantika Subramaniam, Simon C. Steely Jr., William Hasenplaugh, Aamer Jaleel, Carl J. Beckmann, Tryggve Fossum, Joel S. Emer:
Using in-flight chains to build a scalable cache coherence protocol. 28:1-28:24 - Daniel Sánchez, Yiannakis Sazeides, Juan M. Cebrian, José M. García, Juan L. Aragón:
Modeling the impact of permanent faults in caches. 29:1-29:23 - Sanghoon Lee, James Tuck:
Automatic parallelization of fine-grained metafunctions on a chip multiprocessor. 30:1-30:26 - Christophe Dubach, Timothy M. Jones, Edwin V. Bonilla:
Dynamic microarchitectural adaptation using machine learning. 31:1-31:28 - Long Chen, Yanan Cao, Zhao Zhang:
E3CC: A memory error protection scheme with novel address mapping for subranked and low-power memories. 32:1-32:22 - Yingying Tian, Samira Manabi Khan, Daniel A. Jiménez:
Temporal-based multilevel correlating inclusive cache replacement. 33:1-33:24 - Qixiao Liu, Miquel Moretó, Víctor Jiménez, Jaume Abella, Francisco J. Cazorla, Mateo Valero:
Hardware support for accurate per-task energy metering in multicore systems. 34:1-34:27 - Sanyam Mehta, Gautham Beeraka, Pen-Chung Yew:
Tile size selection revisited. 35:1-35:27 - Bogdan Prisacari, Germán Rodríguez, Cyriel Minkenberg, Torsten Hoefler:
Fast pattern-specific routing for fat tree networks. 36:1-36:25 - Maximilien Breughe, Lieven Eeckhout:
Selecting representative benchmark inputs for exploring microprocessor design spaces. 37:1-37:24 - Christoph Kerschbaumer, Eric Hennigan, Per Larsen, Stefan Brunthaler, Michael Franz:
Information flow tracking meets just-in-time compilation. 38:1-38:25 - Rupesh Nasre:
Time- and space-efficient flow-sensitive points-to analysis. 39:1-39:27 - Wenjia Ruan, Yujie Liu, Michael F. Spear:
Boosting timestamp-based transactional memory by exploiting hardware cycle counters. 40:1-40:21 - Tanima Dey, Wei Wang, Jack W. Davidson, Mary Lou Soffa:
ReSense: Mapping dynamic workloads of colocated multithreaded applications using resource sensitivity. 41:1-41:25 - Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal:
Techniques to improve performance in requester-wins hardware transactional memory. 42:1-42:25 - Myeongjae Jeon, Conglong Li, Alan L. Cox, Scott Rixner:
Reducing DRAM row activations with eager read/write clustering. 43:1-43:25 - Zhijia Zhao, Michael Bebenita, Dave Herman, Jianhua Sun, Xipeng Shen:
HPar: A practical parallel parser for HTML-taming HTML complexities for parallel parsing. 44:1-44:25 - Ehsan Totoni, Mert Dikmen, María Jesús Garzarán:
Easy, fast, and energy-efficient object detection on heterogeneous on-chip architectures. 45:1-45:25 - Viacheslav V. Fedorov, Sheng Qiu, A. L. Narasimha Reddy, Paul V. Gratz:
ARI: Adaptive LLC-memory traffic management. 46:1-46:19 - Cecilia González-Alvarez, Jennifer B. Sartor, Carlos Álvarez, Daniel Jiménez-González, Lieven Eeckhout:
Accelerating an application domain with specialized functional units. 47:1-47:25 - Xiaolin Wang, Lingmei Weng, Zhenlin Wang, Yingwei Luo:
Revisiting memory management on virtualized environments. 48:1-48:20 - Chuntao Jiang, Zhibin Yu, Hai Jin, Cheng-Zhong Xu, Lieven Eeckhout, Wim Heirman, Trevor E. Carlson, Xiaofei Liao:
PCantorSim: Accelerating parallel architecture simulation through fractal-based sampling. 49:1-49:24 - Srdan Stipic, Vesna Smiljkovic, Osman S. Unsal, Adrián Cristal, Mateo Valero:
Profile-guided transaction coalescing - lowering transactional overheads by merging transactions. 50:1-50:18 - Zhe Wang, Shuchang Shan, Ting Cao, Junli Gu, Yi Xu, Shuai Mu, Yuan Xie, Daniel A. Jiménez:
WADE: Writeback-aware dynamic cache management for NVM-based main memory system. 51:1-51:21 - Yong Li, Yaojun Zhang, Hai Li, Yiran Chen, Alex K. Jones:
C1C: A configurable, compiler-guided STT-RAM L1 cache. 52:1-52:22 - Naznin Fauzia, Venmugil Elango, Mahesh Ravishankar, J. Ramanujam, Fabrice Rastello, Atanas Rountev, Louis-Noël Pouchet, P. Sadayappan:
Beyond reuse distance analysis: Dynamic analysis for characterization of data locality potential. 53:1-53:29 - Alen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors:
Designing a practical data filter cache to improve both energy efficiency and performance. 54:1-54:25 - Andrei Hagiescu, Bing Liu, R. Ramanathan, Sucheendra K. Palaniappan, Zheng Cui, Bipasa Chattopadhyay, P. S. Thiagarajan, Weng-Fai Wong:
GPU code generation for ODE-based applications with phased shared-data access patterns. 55:1-55:19 - Junghee Lee, Chrysostomos Nicopoulos, Hyung Gyu Lee, Jongman Kim:
TornadoNoC: A lightweight and scalable on-chip network architecture for the many-core era. 56:1-56:30 - Christos Strydis, Robert M. Seepers, Pedro Peris-Lopez, Dimitrios Siskos, Ioannis Sourdis:
A system architecture, processor, and communication protocol for secure implants. 57:1-57:23 - Wonsub Kim, Yoonseo Choi, Haewoo Park:
Fast modulo scheduler utilizing patternized routes for coarse-grained reconfigurable architectures. 58:1-58:24 - Dorit Nuzman, Revital Eres, Sergei Dyshel, Marcel Zalmanovici, José G. Castaños:
JIT technology with C/C++: Feedback-directed dynamic recompilation for statically compiled languages. 59:1-59:25 - Thejas Ramashekar, Uday Bondhugula:
Automatic data allocation and buffer management for multi-GPU machines. 60:1-60:26 - Hans Vandierendonck, George Tzenakis, Dimitrios S. Nikolopoulos:
Analysis of dependence tracking algorithms for task dataflow execution. 61:1-61:24 - Yeonghun Jeong, Seongseok Seo, Jongeun Lee:
Evaluator-executor transformation for efficient pipelining of loops with conditionals. 62:1-62:23 - Rajkishore Barik, Jisheng Zhao, Vivek Sarkar:
A decoupled non-SSA global register allocation using bipartite liveness graphs. 63:1-63:24 - Peter Gavin, David B. Whalley, Magnus Själander:
Reducing instruction fetch energy in multi-issue processors. 64:1-64:24
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