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ORCIDMicroelectronics Journal, Volume 70
Volume 70, December 2017
- Yun Yin, Yanqiang Gao, Zhihua Wang, Baoyong Chi:
A 0.1-5.0 GHz SDR transmitter with current-mode power-mixer and self-calibration scheme in 65 nm CMOS. 1-11 - Hussain Mohammed Dipu Kabir
, S. M. Salahuddin:
A frequency multiplier using three ambipolar graphene transistors. 12-15 - Naresh Kumar Reddy Becchu, Vasantha Moodabettu Harishchandra, Nithin Kumar Yernad Balachandra:
System level fault-tolerance core mapping and FPGA-based verification of NoC. 16-26 - Naveen Kadayinti, Dinesh Kumar Sharma:
Sense amplifier comparator with offset correction for decision feedback equalization based receivers. 27-33 - Edson Leonardo dos Santos, Marco Antonio Rios, Luis Schuartz, Bernardo Leite, Luis Lolis, Eduardo Gonçalves de Lima, André Augusto Mariano:
A fully integrated CMOS power amplifier with discrete gain control for efficiency enhancement. 34-42 - Young-Ho Jung, Seong-Kwan Hong, Oh-Kyong Kwon:
A high-efficient and fast-transient buck-boost converter using adaptive direct path skipping and on-duty modulation. 43-51 - Lianxi Liu, Yi Zhang, Yu Song, Zhangming Zhu, Yintang Yang:
A current-reuse dual-channel bio-signal amplifier for WBAN nodes. 52-62 - Ching-Che Chung, Chi-Yu Hou:
An all-digital delay-locked loop for 3-D ICs die-to-die clock deskew applications. 63-71 - Mohamed B. Elamien, Soliman A. Mahmoud:
Analysis and design of a highly linear CMOS OTA for portable biomedical applications in 90 nm CMOS. 72-80 - Ruixue Ding, Hongzhi Liang, Shubin Liu, Zhangming Zhu:
Analysis and optimal distribution scheme for SAR-VCO ADCs. 81-88 - Behnam Samadpoor Rikan, Hamed Abbasizadeh, Young-Jun Park, Hye-Yeong Kang, SangYun Kim, YoungGun Pu, Minjae Lee, Keum-Cheol Hwang, Youngoo Yang, Kang-Yoon Lee:
A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy. 89-96 - Zhenrong Li, Xintong Liu, Yiqi Zhuang:
A 12-27 GHz SiGe BiCMOS VGA with phase shift variation compensation. 97-106 - Deng-Shian Wang, Yu-Hsun Su, Chua-Chin Wang:
A readout circuit with cell output slew rate compensation for 5T single-ended 28 nm CMOS SRAM. 107-116
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