Xiaokuo Yang, Li Cai, Xiaohui Zhao, Nansheng Zhang: Design and simulation of sequential circuits in quantum-dot cellular automata: Falling edge-triggered flip-flop and counter study.
56-63
George Jie Yuan, Ka Leong Tsang: The design and optimization methodology of a low-distortion sub-µW sample-and-hold stage for weak bio-currents.
121-128
Tohru Suwa, Hamid Hadim: Optimal placement of heat generating components at various levels of electronics packaging.
129-134
Javier Sosa, Juan A. Montiel-Nelson, Saeid Nooshabadi: Application of genetic algorithm in computing the tradeoffs between power consumption versus delay in digital integrated circuit design.
135-141
L. Mahdavian, M. Monajjemi: Alcohol sensors based on SWNT as chemical sensors: Monte Carlo and Langevin dynamics simulation.
142-149
Tiw Pei Wen, Ajay Kumar Singh: A comprehensive analytical study of an undoped symmetrical double-gate MOSFET after considering quantum confinement parameter.
162-170
Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic.
195-211
Petru Cascaval, Doina Cascaval: March SR3C: A Test for a reduced model of all static simple three-cell coupling faults in random-access memories.
212-218
Y. M. Hwang, W. L. Lu, C. T. Pan: Development and fabrication of an LTCC multilayer coil inducer in a vibration-based electromagnetic meso-generator.
338-346
P. Karthigaikumar, K. Baskaran: An ASIC implementation of low power and high throughput blowfish crypto algorithm.
347-355
D.-A. Wang, K.-H. Chang: Electromagnetic energy harvesting from flow induced vibration.
356-364
Jiafeng Xie, Jianjun He, Guanzheng Tan: FPGA realization of FIR filters for high-speed and medium-speed by using modified distributed arithmetic architectures.
365-370
Tian Xia, Di Mu: High speed interconnect data dependent jitter analysis.
371-379
Fahad Ali Usmani, Mohammad Hasan: Carbon nanotube field effect transistors for high performance analog applications: An optimum design approach.
395-402
Shuo Yang, Jun Cheng, Pei Wang: Variable-amplitude dither-based digital background calibration algorithm for linear and high-order nonlinear error in pipelined ADCs.
403-410
Bo Ye: A wide-range all digital DLL for multiphase clock generation.
411-416
Hwann-Kaeo Chiou, Tsung-Yu Yang: Post-linearization with image rejection for high IIP3 and image-rejection ratio of a 17 GHz CMOS low noise amplifier.
494-501
Firat Kaçar, Abdullah Yesil: Novel grounded parallel inductance simulators realization using a minimum number of active and passive components.
632-638
Ko-Chi Kuo, Chi-Wen Chou: Low power and high speed multiplier design with row bypassing and parallel architecture.
639-650
Tae Wook Kim: 900 MHz CDMA/1.8 GHz PCS/450 MHz CDMA RF receiver ICs with a new mixer linearization method and optimization of integrated inductor for single balance mixer LO buffer.
851-859