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IEEE Micro, Volume 44
Volume 44, Number 1, January - February 2024
- Hsien-Hsin S. Lee:
Computing With COOL Chips. 4-5 - Ryusuke Egawa, Yasutaka Wada:
Special Issue on COOL Chips. 6-7 - Reon Oshio, Sugahara Takuya, Atsushi Sawada, Mutsumi Kimura, Renyuan Zhang, Yasuhiko Nakashima:
A Compressed Spiking Neural Network Onto a Memcapacitive In-Memory Computing Array. 8-16 - Donghyeon Han, Junha Ryu, Sangyeob Kim, Sangjin Kim, Jongjun Park, Hoi-Jun Yoo:
A Low-Power Artificial-Intelligence-Based 3-D Rendering Processor With Hybrid Deep Neural Network Computing. 17-27 - Sangyeob Kim, Soyeon Kim, Seongyon Hong, Sangjin Kim, Jiwon Choi, Donghyeon Han, Hoi-Jun Yoo:
COOL-NPU: Complementary Online Learning Neural Processing Unit. 28-37 - Tatsuya Kubo, Shinya Takamaeda-Yamazaki:
Cachet: Low-Overhead Integrity Verification on Metadata Cache in Secure Nonvolatile Memory Systems. 38-48 - Jianqing Liu, Na Gong:
Privacy by Memory Design: Visions and Open Problems. 49-58 - Cyrius Nugier, Vincent Migliore:
Acceleration of a Classic McEliece Postquantum Cryptosystem With Cache Processing. 59-68 - Joshua J. Yi:
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part VIII: Patent Families. 70-74 - Shane Greenstein:
After the Gold Rush. 76-78
Volume 44, Number 2, March - April 2024
- Hsien-Hsin S. Lee:
Beyond Wires: The Future of Interconnects. 4-5 - Scott Levy, Whit Schonbein:
Special Issue on Hot Interconnects 30. 6-7 - Yuke Li, Arjun Kashyap, Yanfei Guo, Xiaoyi Lu:
Compression Analysis for BlueField-2/-3 Data Processing Units: Lossy and Lossless Perspectives. 8-19 - Rafael Oliveira, Ada Gavrilovska:
Comprex: In-Network Compression for Accelerating IoT Analytics at Scale. 20-30 - Liuyao Dai, Hao Qi, Weicong Chen, Xiaoyi Lu:
High-Speed Data Communication With Advanced Networks in Large Language Model Training. 31-40 - Dennis Abts, John Kim:
Enabling Artificial Intelligence Supercomputers With Domain-Specific Networks. 41-49 - Debendra Das Sharma, Swadesh Choudhary:
Pipelined and Partitionable Forward Error Correction and Cyclic Redundancy Check Circuitry Implementation for PCI Express 6.0 and Compute Express Link 3.0. 50-59 - Huseyin Ekin Sumbul, Jae-sun Seo, Daniel H. Morris, Edith Beigné:
A Fully Digital and Row-Pipelined Compute-in-Memory Neural Network Accelerator With System-on-Chip-Level Benchmarking for Augmented/Virtual Reality Applications. 61-70 - Joshua J. Yi:
Analysis of Historical Patenting Behavior and Patent Characteristics of Computer Architecture Companies - Part IX: Patent Families. 72-77 - Shane Greenstein:
Party Like It's 1999? 78-80
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