IEEE Micro, Volume 25, 2005

Volume 25, Number 1, January-February 2005

• Pradip Bose:
  The "power" of communication. 5
  

• Richard H. Stern:
  FTC cracks down on spyware and PC hijacking, but not true lies. 7
  

• James P. G. Sterbenz, Dimitrios Stiliadis:
  Guest Editors' Introduction: Hot Interconnects 12. 8-9
  
• Venkata Krishnan, David Mayhew:
  Localized Congestion Control in Advanced Switching Interconnects. 10-18
  
• Jiuxing Liu, Amith R. Mamidala, Abhinav Vishnu, Dhabaleswar K. Panda:
  Evaluating InfiniBand Performance with PCI Express. 20-29
  
• Thomas H. Dunigan Jr., Jeffrey S. Vetter, James B. White III, Patrick H. Worley:
  Performance Evaluation of the Cray X1 Distributed Shared-Memory Architecture. 30-40
  
• Avinash Karanth Kodi, Ahmed Louri:
  Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. 41-49
  
• Fang Yu, Randy H. Katz, T. V. Lakshman:
  Efficient Multimatch Packet Classification and Lookup with TCAM. 50-59
  
• Bharath Madhusudan, John W. Lockwood:
  A Hardware-Accelerated System for Real-Time Worm Detection. 60-69
  
• Srikanth Arekapudi, Shang-Tse Chuang, Isaac Keslassy, Nick McKeown:
  Using Hardware to Configure a Load-Balanced Switch. 70-78
  
• Ayose Falcón, Jared Stark, Alex Ramírez, Konrad K. Lai, Mateo Valero:
  Better Branch Prediction Through Prophet/Critic Hybrids. 80-89
  
• Kyle J. Nesbit, James E. Smith:
  Data Cache Prefetching Using a Global History Buffer. 90-97
  

• Richard Mateosian:
  Too much information. 98-99
  

• Shane Greenstein:
  Not a mellifluous march to maturity. 102-104
  

Volume 25, Number 2, March-April 2005

• Pradip Bose:
  Variation-tolerant design. 5
  

• Richard Mateosian:
  Thinking about history and design. 6-7
  

• William J. Dally, Keith Diefendorff:
  Hot Chips 16: Power, Parallelism, and Memory Performance. 8-9
  
• Cameron McNairy, Rohit Bhatia:
  Montecito: A Dual-Core, Dual-Thread Itanium Processor. 10-20
  
• Poonacha Kongetira, Kathirgamar Aingaran, Kunle Olukotun:
  Niagara: A 32-Way Multithreaded Sparc Processor. 21-29
  
• Rajesh Kota, Rich Oehler:
  Horus: Large-Scale Symmetric Multiprocessing for Opteron Systems. 30-40
  
• John Montrym, Henry P. Moreton:
  The GeForce 6800. 41-51
  
• Hans Eberle, Sheueling Chang Shantz, Vipul Gupta, Nils Gura, Leonard Rarick, Lawrence Spracklen:
  Accelerating Next-Generation Public-Key Cryptosystems on General-Purpose CPUs. 52-59
  
• Jorg Keller, Andreas Gravinghoff:
  Thread-Based Virtual Duplex Systems in Embedded Environments. 60-69
  

• Shane Greenstein:
  Communications consolidation after an era of no restraints. 70-72
  

Volume 25, Number 3, May-June 2005

• Pradip Bose:
  Integrated microarchitectures. 5-6
  

• Richard H. Stern:
  The antitrust ghost in the standard-setting machine. 7-9
  

• Shane Greenstein:
  The anatomy of foresight traps. 10-12
  

• Richard Mateosian:
  Dealing with globalization. 13-15
  

• Michael J. Flynn, Patrick Hung:
  Microprocessor Design Issues: Thoughts on the Road Ahead. 16-31
  
• Shailender Chaudhry, Paul Caprioli, Sherman Yip, Marc Tremblay:
  High-Performance Throughput Computing. 32-45
  
• Adrián Cristal, Oliverio J. Santana, Francisco J. Cazorla, Marco Galluzzi, Tanausú Ramírez, Miquel Pericàs, Mateo Valero:
  Kilo-Instruction Processors: Overcoming the Memory Wall. 48-57
  
• Tilak Agerwala, Siddhartha Chatterjee:
  Computer Architecture: Challenges and Opportunities for the Next Decade. 58-69
  
• Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers:
  Lifetime Reliability: Toward an Architectural Solution. 70-80
  
• Mancia Anguita, J. Manuel Martinez-Lechado:
  MP3 Optimization Exploiting Processor Architecture and using Better Algorithms. 81-92
  

• Philip G. Emma:
  Inventions and the creative process. 93-96
  

Volume 25, Number 4, July-August 2005

• Pradip Bose:
  Presilicon modeling: challenges in the late CMOS era. 5-6
  

• Philip G. Emma:
  What is patentable? 7-9
  

• Zhichun Zhu, Xiaodong Zhang:
  Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption. 10-19
  
• Yen-Jen Chang, Feipei Lai:
  Dynamic Zero-Sensitivity Scheme for Low-Power Cache Memories. 20-32
  
• Jon Beecroft, David Addison, David Hewson, Moray McLaren, Duncan Roweth, Fabrizio Petrini, Jarek Nieplocha:
  QsNetII: Defining High-Performance Network Design. 34-47
  
• Mohammad J. Akhbarizadeh, Mehrdad Nourani, Cyrus D. Cantrell:
  Prefix Segregation Scheme for a TCAM-Based IP Forwarding Engine. 48-63
  
• Weidong Wu, Jian Shi, Ling Zuo, Bingxin Shi:
  Power-Efficient TCAMS for Bursty Access Patterns. 64-72
  

• Richard H. Stern:
  Standardization skullduggery update: UMTS standard. 73-76
  

• Shane Greenstein:
  Explorers and expanders, both early and late. 77-79
  

• Richard Mateosian:
  Going through the database. 79-80
  

Volume 25, Number 5, September-October 2005

• Pradip Bose:
  High performance at affordable power. 5
  

• Kunio Uchiyama, Pradip Bose:
  Guest Editors' Introduction: Energy-Efficient Design. 6-9
  
• Osamu Takahashi, Scott R. Cottier, Sang H. Dhong, Brian K. Flachs, Joel Silberman:
  Power-Conscious Design of the Cell Processor's Synergistic Processor Element. 10-18
  
• Seiji Maeda, Shigehiro Asano, Tomofumi Shimada, Koichi Awazu, Haruyuki Tago:
  A Real-Time Software Platform for the Cell Processor. 20-29
  
• Toru Asano, Joel Silberman, Sang H. Dhong, Osamu Takahashi, Michael White, Scott R. Cottier, Takaaki Nakazato, Atsushi Kawasumi, Hiroshi Yoshihara:
  Low-Power Design Approach of 11FO4 256-Kbyte Embedded SRAM for the Synergistic Processor Element of a Cell Processor. 30-38
  
• Canturk Isci, Alper Buyuktosunoglu, Margaret Martonosi:
  Long-Term Workload Phases: Duration Predictions and Applications to DVFS. 39-51
  
• Qiang Wu, Philo Juang, Margaret Martonosi, Li-Shiuan Peh, Douglas W. Clark:
  Formal Control Techniques for Power-Performance Management. 52-62
  
• Diana Marculescu, Emil Talpes:
  Energy Awareness and Uncertainty in Microarchitecture-Level Design. 64-76
  

• Jeffery B. Fromm, Robert A. Skitol:
  Update on the antitrust ghost in the standard-setting machine. 77-79
  

• Philip G. Emma:
  Patents: To file or not to file? 79-81
  

• Shane Greenstein:
  Outsourcing and climbing a value chain. 83-84
  

Volume 25, Number 6, November-December 2005

• Pradip Bose:
  Designing microprocessors with robust functionality and performance. 5
  

• Shane Greenstein:
  Wireless access and electrical markets: Becoming similar? 6-7
  

• Sarita V. Adve, Pia Sanda:
  Guest Editors' Introduction: Reliability-Aware Microarchitecture. 8-9
  
• Shekhar Y. Borkar:
  Designing Reliable Systems from Unreliable Components: The Challenges of Transistor Variability and Degradation. 10-16
  
• Ravishankar K. Iyer, Nithin Nakka, Zbigniew Kalbarczyk, Subhasish Mitra:
  Recent Advances and New Avenues in Hardware-Level Reliability Support. 18-29
  
• Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer:
  An Experimental Study of Soft Errors in Microprocessors. 30-39
  
• Zhijian Lu, John Lach, Mircea R. Stan, Kevin Skadron:
  Improved Thermal Management with Reliability Banking. 40-49
  
• Brian T. Gold, Jangwoo Kim, Jared C. Smolens, Eric S. Chung, Vasileios Liaskovitis, Eriko Nurvitadhi, Babak Falsafi, James C. Hoe, Andreas Nowatzyk:
  TRUSS: A Reliable, Scalable Server Architecture. 51-59
  
• M. Wasiur Rashid, Edwin J. Tan, Michael C. Huang, David H. Albonesi:
  Power-Efficient Error Tolerance in Chip Multiprocessors. 60-70
  
• Daniel L. Stasiak, Rajat Chaudhry, Dennis Cox, Stephen D. Posluszny, James D. Warnock, Steve Weitzel, Dieter F. Wendel, Michael Wang:
  Cell Processor Low-Power Design Methodology. 71-78
  

• Philip G. Emma:
  Writing the claims for a patent. 79-81
  

• Richard Mateosian:
  Year-end cleanup. 82-84
  

• Richard Stern:
  Transnational electronic systems and patent infringement. 85-88
  

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