Volume 24, Number 1, January/February

• 
  Pradip Bose: Editor in Chief's Message: New Challenges and Burning Issues. 5

• 
  Richard H. Stern: Challenging Search Engines and Pop-Ups Under Copyright Law: Part 2. 7

• 
  J. Bryan Lyles: Guest Editor's Introduction: Hot Interconnects 11 - Solving Network Bottlenecks. 8-9
• 
  Justin Gus Hurwitz, Wu-chun Feng: End-to-End Performance of 10-Gigabit Ethernet on Commodity Systems. 10-22
• 
  Greg J. Regnier, Dave B. Minturn, Gary L. McAlpine, Vikram A. Saletore, Annie Foong: ETA: Experience with an Intel Xeon Processor as a Packet Processing Engine. 24-31
• 
  Andrew Lines: Asynchronous Interconnect for Synchronous SoC Design. 32-41
• 
  Jiuxing Liu, B. Chandrasekaran, Weikuan Yu, Jiesheng Wu, Darius Buntinas, Sushmitha P. Kini, Dhabaleswar K. Panda, Pete Wyckoff: Microbenchmark Performance Comparison of High-Speed Cluster Interconnects. 42-51
• 
  Sarang Dharmapurikar, Praveen Krishnamurthy, Todd S. Sproull, John W. Lockwood: Deep Packet Inspection using Parallel Bloom Filters. 52-61
• 
  David V. Schuehler, James Moscola, John W. Lockwood: Architecture for a Hardware-Based, TCP/IP Content-Processing System. 62-69

• 
  Richard Mateosian: Single Sourcing Mount Fuji. 74-75

• 
  Shane M. Greenstein: Why Inventors are not Famous. 76-78

• 
  Charles R. Moore: Managing the Transition from Complexity to Elegance: Design Convergence. 80

Volume 24, Number 2, March/April 2004

• 
  Pradip Bose: EIC's Message: Chip-level microarchitecture trends. 5-

• 
  Richard H. Stern: Challenging search engines and pop-ups under copyright law--Part 3. 6, 70-72

• 
  Michael J. Flynn, Pradeep K. Dubey: Guest Editors' Introduction: Hot Chips 15--Scaling the Silicon Mountain. 7-9
• 
  Stefan Rusu, Harry Muljono, Brian S. Cherkauer: Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. 10-18
• 
  Sanjiv Kapil, Harlan McGhan, Jesse Lawrendra: A Chip Multithreaded Processor for Network-Facing Workloads. 20-30
• 
  Deepu Talla, Ching-Yu Hung, Raj Talluri, Frank Brill, David Smith, David Brier, Bruce Xiong, Derek Huynh: Anatomy of a Portable Digital Mediaprocessor. 32-39
• 
  Ronald N. Kalla, Balaram Sinharoy, Joel M. Tendler: IBM Power5 Chip: A Dual-Core Multithreaded Processor. 40-47
• 
  Uri Cummings: PivotPoint: Clockless Crossbar Switch for High-Performance Embedded Systems. 48-59
• 
  V. C. Ravikumar, Rabi N. Mahapatra: TCAM Architecture for IP Lookup Using Prefix Properties. 60-69

• 
  Shane Greenstein: The paradox of commodities. 73-75

• 
  Micro News. 76-77

• 
  Chuck Moore: Getting it right. 79-80

Volume 24, Number 3, May/June 2004

• 
  Pradip Bose: EIC's Message: General-purpose versus application-specific processors. 5-

• 
  Richard H. Stern: Collecting patent infringement damages on unpatented products. 6-7

• 
  Alexander V. Veidenbaum: Guest Editor's Introduction: Application-Specific Processors. 8-9
• 
  Michael L. Chu, Kevin Fan, Rajiv A. Ravindran, Scott A. Mahlke: Cost-Sensitive Partitioning in an Architecture Synthesis System for Multicluster Processors. 10-20
• 
  Peter Petrov, Alex Orailoglu: Transforming Binary Code for Low-Power Embedded Processors. 21-33
• 
  Alireza Hodjat, Ingrid Verbauwhede: High-Throughput Programmable Cryptocoprocessor. 34-45
• 
  Matthias Meyer: A Novel Processor Architecture with Exact Tag-Free Pointers. 46-55
• 
  Faraydon Karim, Alain Mellan, Anh Nguyen, Utku Aydonat, Tarek S. Abdelrahman: A Multilevel Computing Architecture for Embedded Multimedia Applications. 56-66

• 
  Shane Greenstein: Imitation happens. 67-69

• 
  Richard Mateosian: Back to the future. 70-71

• 
  Micro News. 72-

Volume 24, Number 4, July/August 2004

• 
  Pradip Bose: Editor in Chief's Message: Saving power-Lessons from embedded systems. 5-6

• 
  Richard H. Stern: FTC turns back challenge on patent coverage. 7

• 
  Alessio Bechini, Thomas M. Conte, Cosimo Antonio Prete: Guest Editors' Introduction: Opportunities and Challenges in Embedded Systems. 8-9
• 
  Alexander G. Dean: Efficient Real-Time Fine-Grained Concurrency on Low-Cost Microcontrollers. 10-22
• 
  Francisco J. Cazorla, Alex Ramírez, Mateo Valero, Peter M. W. Knijnenburg, Rizos Sakellariou, Enrique Fernández: QoS for High-Performance SMT Processors in Embedded Systems. 24-31
• 
  Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough: Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1. 33-41
• 
  David L. Andrews, Douglas Niehaus, Razali Jidin, Michael Finley, Wesley Peck, Michael Frisbie, Jorge L. Ortiz, Ed Komp, Peter J. Ashenden: Programming Models for Hybrid FPGA-CPU Computational Components: A Missing Link. 42-53
• 
  Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner: Design Space Exploration for Real-Time Embedded Stream Processors. 54-66
• 
  Andreas Krall, Ivan Pryanishnikov, Ulrich Hirnschrott, Christian Panis: xDSPcore: A Compiler-Based Configurable Digital Signal Processor. 67-78

• 
  Shane Greenstein: The diamond-wafer paradox: A modern mystery. 79-81

• 
  Micro News. 82-

• 
  Richard Mateosian: Attacking complexity. 87-88

Volume 24, Number 5, September-October 2004

• 
  Pradip Bose: Communication versus Computation. 5

• 
  Richard H. Stern: Vicarious liability for infringement. 6

• 
  Ioannis Papaefstathiou, Nikos A. Nikolaou, Bharat T. Doshi, Eric Grosse: Guest Editors' Introduction: Network Processors for Future High-End Systems and Applications. 7-9
• 
  Jakob Carlström, Thomas Boden: Synchronous Dataflow Architecture for Network Processors. 10-18
• 
  Ioannis Papaefstathiou, Stylianos Perissakis, Theofanis Orphanoudakis, Nikos A. Nikolaou, George Kornaros, Nicholas Zervos, George E. Konstantoulakis, Dionisios N. Pnevmatikatos, Kyriakos Vlachos: PRO3: A Hybrid NPU Architecture. 20-33
• 
  Yan Luo, Jun Yang, Laxmi N. Bhuyan, Li Zhao: NePSim: A Network Processor Simulator with a Power Evaluation Framework. 34-44
• 
  Niraj Shah, William Plishker, Kaushik Ravindran, Kurt Keutzer: NP-Click: A Productive Software Development Approach for Network Processors. 45-54
• 
  Zhangxi Tan, Chuang Lin, Hao Yin, Bo Li: Optimization and Benchmark of Cryptographic Algorithms on Network Processors. 55-69
• 
  Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough: Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2. 70-78

• 
  Shane Greenstein: Creative Destruction and Deconstruction. 83-85

• 
  Richard Mateosian: Seek and Show. 86-88

Volume 24, Number 6, November-December 2004

• 
  Pradip Bose: Computer architecture research: Shifting priorities and newer challenges. 5

• 
  Shane Greenstein: Canaries, whips, and sails. 6-7

• 
  David H. Albonesi: Guest Editor's Introduction: Micro's Top Picks from Microarchitecture Conferences. 8-9
• 
  Dan Ernst, Shidhartha Das, Seokwoo Lee, David Blaauw, Todd M. Austin, Trevor N. Mudge, Nam Sung Kim, Krisztián Flautner: Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. 10-20
• 
  Jared C. Smolens, Brian T. Gold, Jangwoo Kim, Babak Falsafi, James C. Hoe, Andreas Nowatzyk: Fingerprinting: Bounding Soft-Error-Detection Latency and Bandwidth. 22-29
• 
  Christopher T. Weaver, Joel S. Emer, Shubhendu S. Mukherjee, Steven K. Reinhardt: Reducing the Soft-Error Rate of a High-Performance Microprocessor. 30-37
• 
  Xiaodong Li, Zhenmin Li, Pin Zhou, Yuanyuan Zhou, Sarita V. Adve, Sanjeev Kumar: Performance-Directed Energy Management for Storage Systems. 38-49
• 
  Pin Zhou, Feng Qin, Wei Liu, Yuanyuan Zhou, Josep Torrellas: iWatcher: Simple, General Architectural Support for Software Debugging. 50-56
• 
  Brian A. Fields, Rastislav Bodík, Mark D. Hill, Chris J. Newburn: Interaction Cost: For When Event Counts Just Don't Add Up. 57-61
• 
  Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton: Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance. 62-73
• 
  Perry H. Wang, Jamison D. Collins, Hong Wang, Dongkeun Kim, Bill Greene, Kai-Ming Chan, Aamir B. Yunus, Terry Sych, Stephen F. Moore, John Paul Shen: Helper Threads via Virtual Multithreading. 74-82
• 
  Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic: The Vector-Thread Architecture. 84-90
• 
  Lance Hammond, Brian D. Carlstrom, Vicky Wong, Michael K. Chen, Christos Kozyrakis, Kunle Olukotun: Transactional Coherence and Consistency: Simplifying Parallel Hardware and Software. 92-103
• 
  Jaehyuk Huh, Doug Burger, Jichuan Chang, Gurindar S. Sohi: Speculative Incoherent Cache Protocols. 104-109
• 
  Harold W. Cain, Mikko H. Lipasti: Memory Ordering: A Value-Based Approach. 110-117
• 
  Simha Sethumadhavan, Rajagopalan Desikan, Doug Burger, Charles R. Moore, Stephen W. Keckler: Scalable Hardware Memory Disambiguation for High-ILP Processors. 118-127

• 
  Micro News. 129
• 
  Richard Mateosian: Micro Review: More on old themes. 133-134

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