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IEEE Micro, Volume 20, 2000
Volume 20, Number 1, January/February 2000
- Ken Sakamura:
Performance in the New Millennium. 2-3
- Letters. 3
- Micro News. 4-5
- Gary S. Robinson:
Standards Intellectual Property Licensing. 6-8
- Richard H. Stern:
IP-Related Refusals to Deal. Part 1: Updating the Intel-Intergraph Controversy. 9-12
- Shane M. Greenstein:
Aggressive Business Tactics: Are There Limits? 13-14
- Anujan Varma, Mark Laubach:
Guest Editors' Introduction: Solving Interconnection Problems. 15-17 - Charles D. Cranor
, R. Gopalakrishnan, Peter Z. Onufryk:
Architectural Considerations for CPU and Network Interface Integration. 18-26 - Tzi-cker Chiueh, Prashant Pradhan:
Cache Memory Design for Internet Processors. 28-33 - Pankaj Gupta, Nick McKeown:
Classifying Packets with Hierarchical Intelligent Cuttings. 34-41 - L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia:
A Scheduler ASIC for a Programmable Packet Switch. 42-48 - Benjamin C. Reed
, Edward G. Chron, Randal C. Burns
, Darrell D. E. Long:
Authenticating Network-Attached Storage. 49-57 - Dan Steinberg, Yitzhak Birk
:
An Empirical Analysis of the IEEE-1394 Serial Bus Protocol. 58-65
- José Fridman, Zvi Greenfield:
The TigerSHARC DSP Architecture. 66-76
- Richard Mateosian:
Happy New Year. 77-78
- Stephen L. Diamond:
Microdisplay Applications Reach the Mainstream. 79-80
Volume 20, Number 2, March/April 2000
- Ken Sakamura:
New Applications and Demands. 2
- Gary S. Robinson:
The Good, the Bad, and the Ugly. 3-4
- Letters. 4
- Shane M. Greenstein:
A Revolution? How Do You Know? 5-7
- Richard H. Stern:
IP-Related Refusals to Deal-Part 2: Pretext and Misconduct as Standards. 8-11
- Richard Mateosian:
Windows 2000. 12-13
- Monica S. Lam, Forest Baskett:
Guest Editors' Introduction: Cutting-Edge Designs. 14-15 - Henry Samueli:
The Broadband Revolution. 16-26 - Edward H. Frank, Jack Holloway:
Connecting the Home With a Phone Line Network Chip Set. 27-38 - Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato
, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki:
Vector Unit Architecture for Emotion Synthesis. 40-47 - Chris Basoglu, Woobin Lee, John Setel O'Donnell:
The MAP1000A VLIW Mediaprocessor. 48-59 - Ricardo E. Gonzalez:
Xtensa: A Configurable and Extensible Processor. 60-70 - Lance Hammond, Benedict A. Hubbert, Michael Siu, Manohar K. Prabhu, Michael K. Chen, Kunle Olukotun:
The Stanford Hydra CMP. 71-84
- Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales:
AltiVec Extension to PowerPC Accelerates Media Processing. 85-95
- Product Summary.
Volume 20, Number 3, May/June 2000
- Ken Sakamura:
Developing New Computer Architectures. 2
- News. 3
- Richard Mateosian:
Doing it right. 4-5
- Richard H. Stern:
IP-related Refusals to Deal: Part 2 1/2: A Postscript. 6-7
- Shane M. Greenstein:
Living in the Era of Impatience. 8-9
- Alan Clements:
Guest Editor's Introduction: Computer Architecture Education. 10-12 - Alan Clements:
The Undergraduate Curriculum in Computer Architecture. 13-22 - Daniel C. Hyde:
Teaching Design in a Computer Architecture Course. 23-28 - James O. Hamblen:
Rapid Prototyping Using Field-Programmable Logic Devices. 29-37 - Nirav H. Kapadia, Renato J. O. Figueiredo
, José A. B. Fortes:
PUNCH: Web Portal for Running Tools. 38-47 - Augustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski:
Building Real Computer Systems. 48-56 - Roland N. Ibbett:
HASE DLX Simulation Model. 57-65 - Jovan Djordjevic, Aleksandar Milenkovic
, Nenad Grbanovic:
An Integrated Environment for Teaching Computer Architecture. 66-74
- Arvind, Anton T. Dahbura, Alejandro Caro:
From Monsoon to StarT-Voyager: University-Industry Collaboration. 75-84
- Gary S. Robinson:
Join a Standards Group and See the World. 85-86
- Product Summary. 88
Volume 20, Number 4, July/August 2000
- Micro News. 2-4
- Shane M. Greenstein:
Hung up on AT&T. 5-6
- Richard Mateosian:
Summer Cleanup. 7-9
- Ken Sakamura:
21st-Century Microprocessors. 10-11
- Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi:
A Single-Chip Multiprocessor for Smart Terminals. 12-20 - Atsuhiro Suga, Kunihiko Matsunami:
Introducing the FR500 Embedded Microprocessor. 21-27 - Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama:
SH-5: The 64-Bit SuperH Architecture. 28-39 - Shigeo Araki:
The Memory Stick. 40-46
- Srinivas K. Raman, Vladimir M. Pentkovski, Jagannath Keshava:
Implementing Streaming SIMD Extensions on the Pentium III Processor. 47-57 - F. Jesús Sánchez, Antonio González
:
Analyzing Data Locality in Numeric Applications. 58-66
- Michael J. Flynn, Patrick Hung, Armita Peymandoust:
Using Simple Tools to Evaluate Complex Architectural Trade-offs. 67-75
- Silke Draber:
Optimizing Fault Tolerance in Embedded Distributed Systems. 76-84
- Predicting the Future. 87-88
- New Products.
Volume 20, Number 5, September/October 2000
- Ken Sakamura:
Connecting Will Be Commonplace. 2
- Micro News. 3-4
- Richard Mateosian:
Interaction Design. 5-6
- Shane M. Greenstein:
Falling Through the Cracks at Microsoft. 7
- John Crawford:
Guest Editor's Introduction: Introducing the Itanium Processors. 9-11 - Jerome C. Huck, Dale Morris, Jonathan Ross, Allan D. Knies, Hans M. Mulder, Rumi Zahir:
Introducing the IA-64 Architecture. 12-23 - Harsh Sharangpani, Ken Arora:
Itanium Processor Microarchitecture. 24-43 - Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce:
The Intel IA-64 Compiler Code Generator. 44-53 - Fumio Aono, Masayuki Kimura:
The AzusA 16-Way Itanium Server. 54-60 - Nhon T. Quach:
High Availability and Reliability in the Itanium Processor. 61-69
- Dezsö Sima:
The Design Space of Register Renaming Techniques. 70-83
- Gary S. Robinson:
Formal SDOs: They're Still Alive. 84
- Product Summary. 88
Volume 20, Number 6, November/December 2000
- Micro News. 2-3
- Richard H. Stern:
Napster: A Walking Copyright Infringement? 4-5
- Shane M. Greenstein:
PCs, the Internet, and You. 6-7
- Gary S. Robinson:
Making Standards Simple. 8-9
- Ken Sakamura:
Guest Editor's Introduction: Stepping Into the Future. 10-11 - Marc Tremblay, Jeffrey Chan, Shailender Chaudhry, Andrew W. Conigliaro, Shing Sheung Tse:
The MAJC Architecture: A Synthesis of Parallelism and Scalability. 12-25 - David M. Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook:
Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors. 26-44 - Chris Herring:
Microprocessors, Microcontrollers, and Systems in the New Millennium. 45-51 - Gene Frantz:
Digital Signal Processor Trends. 52-59
- Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M. Lavery, Wei Li, Chu-Cheow Lim, John Ng, David C. Sehr:
An Advanced Optimizer for the IA-64 Architecture. 60-68 - Eric Dahlen, Jennifer Gustin, Susan Meredith, Doug Moran:
The 82460GX Sever/Workstation Chip Set. 69-75 - Humayun Khalid:
Validating Trace-Driven Microarchitectural Simulations. 76-82 - Tadao Nakamura:
Cool Chips III. 83-84
- Product Summary. 96
- New Products.
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