Amir Muhammad, Michael J. Pont: Comments on: "Two novel shared-clock scheduling algorithms for use with 'Controller Area Network' and related protocols".
81-82
Xiaohang Wang, Mei Yang, Yingtao Jiang, Peng Liu: On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks.
119-129
Radu Stefan, Kees Goossens: A TDM slot allocation flow based on multipath routing in NoCs.
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Chris Jackson, Simon J. Hollis: A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip.
139-151
Dmitri Vainbrand, Ran Ginosar: Scalable network-on-chip architecture for configurable neural networks.
152-166
Ji Gu, Hui Guo, Patrick Li: An on-chip instruction cache design with one-bit tag for low-power embedded systems.
382-391
Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng: Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP).
392-404
Uros Legat, Anton Biasizzo, Franc Novak: A compact AES core with on-line error-detection for FPGA applications with modest hardware resources.
405-416
Giang Nguyen Huong, Yeoul Na, Seon Wook Kim: Applying frame layout to hardware design in FPGA for seamless support of cross calls in CPU-FPGA coupling architecture.
462-472
J. Manikandan, B. Venkataramani: Design of a real time automatic speech recognition system using Modified One Against All SVM classifier.
568-578
Sergio Saponara, Luca Fanucci, Marcello Coppola: Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects.
579-592