Volume 3, Numbers 1-2, March 2008

• 
  Matthias F. Carlsohn, Nasser Kehtarnavaz: 1st and 2nd issues of real-time image processing. 1-2
• 
  Konstantinos Babionitakis, Gregory Doumenis, George Georgakarakos, George Lentaris, Kostantinos Nakos, Dionysios I. Reisis, Ioannis Sifnaios, Nikolaos Vlassopoulos: A real-time motion estimation FPGA architecture. 3-20
• 
  Claudio Brunelli, Fabio Garzia, Jari Nurmi: A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities. 21-32
• 
  S. M. Meena, K. Linganagouda: Implementation and analysis of optimized architectures for rank order filter. 33-41
• 
  Konstantinos Babionitakis, Gregory Doumenis, George Georgakarakos, George Lentaris, Kostantinos Nakos, Dionysios I. Reisis, Ioannis Sifnaios, Nikolaos Vlassopoulos: A real-time H.264/AVC VLSI encoder architecture. 43-59
• 
  Marcos Nieto, Luis Salgado, Julián Cabrera, Narciso N. García: Fast mode decision on H.264/AVC baseline profile for real-time performance. 61-75
• 
  Jianfeng Ren, Nasser Kehtarnavaz, Madhukar Budagavi: A fast feature-assisted adaptive early termination approach for multiple reference frames motion estimation in H.264. 77-88
• 
  Mohammed Al-Rawi: Fast Zernike moments. 89-96
• 
  Khalid M. Hosny: Fast computation of accurate Zernike moments. 97-107
• 
  Huchuan Lu, Yingjie Huang, Yen-Wei Chen, Deli Yang: Automatic gender recognition based on pixel-pattern-based texture feature. 109-116

Volume 3, Number 3, September 2008

• 
  Mohamed Akil: Special issue on reconfigurable architecture for real-time image processing. 117-118
• 
  Julien Denoulet, Alain Mérigot: An architecture based on reconfigurability and asynchronism for real-time image processing. 119-130
• 
  Lounis Kessal, Nicolas Abel, Si Mahmoud Karabernou, Didier Demigny: Reconfigurable computing: design methodology and hardware tasks scheduling for real-time image processing. 131-147
• 
  Mainak Sen, Yashwanth Hemaraj, William Plishker, Raj Shekhar, Shuvra S. Bhattacharyya: Model-based mapping of reconfigurable image registration on FPGA platforms. 149-162
• 
  Hongying Meng, Michael Freeman, Nick Pears, Chris Bailey: Real-time human action recognition on an embedded, reconfigurable video processing architecture. 163-176
• 
  Richard M. Jiang, Danny Crookes: FPGA-based minutia matching for biometric fingerprint image database retrieval. 177-182
• 
  Shrutisagar Chandrasekaran, Abbes Amira, Minghua Shi, Amine Bermak: An efficient VLSI architecture and FPGA implementation of the Finite Ridgelet Transform. 183-193
• 
  Vinay Sriram, David Kearney: Multiple parallel FPGA implementations of a Kolmogorov phase screen generator. 195-200
• 
  Sergio Saponara, Michele Casula, Luca Fanucci: ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing. 201-216
• 
  G. Seetharaman, B. Venkataramani, Gopalakrishnan Lakshminarayanan: Automation techniques for implementation of hybrid wave-pipelined 2D DWT. 217-229

Volume 3, Number 4, December 2008

• 
  Matthias F. Carlsohn, Nasser Kehtarnavaz: Fourth issue of real-time image processing. 231-232
• 
  Clemens Arth, Horst Bischof: Real-time object recognition using local features on a DSP-based embedded system. 233-253
• 
  Pavel Babenko, Mubarak Shah: MinGPU: a minimum GPU library for computer vision. 255-268
• 
  C. Iakovidou, Vassilios Vonikakis, Ioannis Andreadis: FPGA implementation of a real-time biologically inspired image enhancement algorithm. 269-287
• 
  Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung: Custom parallel caching schemes for hardware-accelerated image compression. 289-302
• 
  Markos E. Papadonikolakis, Athanasios P. Kakarountas, Costas E. Goutis: Efficient high-performance implementation of JPEG-LS encoder. 303-310
• 
  Calin Rotaru, Thorsten Graf, Jianwei Zhang: Color image segmentation in HSI space for automotive applications. 311-322
• 
  Yu Zhu, Zongqi Lu, Min Liu, Tian Zuo: The line segment table: a fast region description algorithm. 323-331

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