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ORCIDIPSJ Transactions on System LSI Design Methodology, Volume 9
Volume 9, February 2016
- Nozomu Togawa
:
Message from the Editor-in-Chief. 1
- Wing-Kai Chow, Evangeline F. Y. Young:
Placement: From Wirelength to Detailed Routability. 2-12
- Yoshinobu Higami, Senling Wang, Hiroshi Takahashi, Shin-ya Kobayashi, Kewal K. Saluja:
Diagnosis Methods for Gate Delay Faults with Various Amounts of Delays. 13-20 - Atsushi Hashimoto, Nagisa Ishiura:
Detecting Arithmetic Optimization Opportunities for C Compilers by Randomly Generated Equivalent Programs. 21-29 - Ri Cui, Kazuteru Namba:
A Calibration Technique for DVMC with Delay Time Controllable Inverter. 30-36 - Farhan Shafiq, Tsuyoshi Isshiki, Dongju Li, Hiroaki Kunieda:
A Fast Trace Aware Statistical Based Prediction Model with Burst Traffic Modeling for Contention Stall in A Priority Based MPSoC Bus. 37-48
- Amro Awad, Ganesh Balakrishnan, Yipeng Wang, Yan Solihin:
Accurate Cloning of the Memory Access Behavior. 49-60
- Nana Sutisna, Reina Hongyo, Leonardo Lanante, Yuhei Nagao, Masayuki Kurosaki, Hiroshi Ochi:
Unified HW/SW Co-Verification Methodology for High Throughput Wireless Communication System. 61-71 - Michitarou Yabuuchi, Kazutoshi Kobayashi:
Size Optimization Technique for Logic Circuits that Considers BTI and Process Variations. 72-78
- Yohei Umeki, Koji Yanagida, Shusuke Yoshimoto, Shintaro Izumi, Masahiko Yoshimoto, Hiroshi Kawaguchi, Koji Tsunoda, Toshihiro Sugii:
A Counter-based Read Circuit Tolerant to Process Variation for 0.4-V Operating STT-MRAM. 79-83
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