Volume 5, Number 1, January 2011

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  Jude Angelo Ambrose, Roshan G. Ragel, Sri Parameswaran, Aleksandar Ignjatovic: Multiprocessor information concealment architecture to prevent power analysis-based side channel attacks. 1-15
• 
  Irith Pomeranz, Sudhakar M. Reddy: Primary input cones based on test sequences in synchronous sequential circuits. 16-24
• 
  Jiann-Chyi Rau, Po-Han Wu: Power-aware multi-chains encoding scheme for system-on-a-chip in low-cost environment. 25-35
• 
  Tuhina Samanta, Hafizur Rahaman, Parthasarathi Dasgupta: Near-optimal Y-routed delay trees in nanometric interconnect design. 36-48
• 
  Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay: Cone-based placement for field programmable gate arrays. 49-62
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  Wenqing Lu, Shuang Zhao, Xiaofang Zhou, J. Y. Ren, Gerald E. Sobelman: Reconfigurable baseband processing architecture for communication. 63-72

Volume 5, Number 2, March 2011

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  José L. Núñez-Yáñez, Trevor Spiteri, George Vafiadis: Multi-standard reconfigurable motion estimation processor for hybrid video codecs. 73-85
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  Miguel Morales-Sandoval, Claudia Feregrino Uribe, P. Kitsos: Bit-serial and digit-serial GF(2^m)Montgomery multipliers using linear feedback shift registers. 86-94
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  Benjamin Carrión Schäfer, Kazutoshi Wakabayashi: Precision tunable RTL macro-modelling cycle-accurate power estimation. 95-103
• 
  Basel Halak, Alexandre Yakovlev: Statistical analysis of crosstalk-induced errors for on-chip interconnects. 104-112
• 
  Y. Lee, T. Kim: State encoding algorithm for peak current minimisation. 113-122
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  Chantal Ykman-Couvreur, Prabhat Avasare, Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria: Linking run-time resource management of embedded multi-core platforms with automated design-time exploration. 123-135
• 
  Stephen McKeown, Roger Woods: Low power field programmable gate array implementation of fast digital signal processing algorithms: characterisation and manipulation of data locality. 136-144
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  Rubén Apolloni, Daniel Chaver, Fernando Castro, Luis Piñuel, Manuel Prieto, Francisco Tirado: Hybrid timing-address oriented load-store queue filtering for an x86 architecture. 145-157

Volume 5, Number 3, May 2011

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  Yuan Xie, Pol Marchal: Editorial- three-dimensional integrated circuits design. 159
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  Kuan-Neng Chen, Chuan Seng Tan: Integration schemes and enabling technologies for three-dimensional integrated circuits. 160-168
• 
  Ankur Jain, Syed M. Alam, Scott Pozder, Robert E. Jones: Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints. 169-178
• 
  Chia-Ming Hung, Youn-Long Lin: Three-dimensional integrated circuits implementation of multiple applications emphasising manufacture reuse. 179-185
• 
  Brandon Noia, Krishnendu Chakrabarty: Test-wrapper optimisation for embedded cores in through-silicon via-based three-dimensional system on chips. 186-197
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  Thorlindur Thorolfsson, Nariman Moezzi Madani, Paul D. Franzon: Reconfigurable five-layer three-dimensional integrated memory-on-logic synthetic aperture radar processor. 198-204
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  Tanay Karnik, Dinesh Somasekhar, Shekhar Borkar: Microprocessor system applications and challenges for through-silicon-via-based three-dimensional integration. 205-212
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  Xiangyu Dong, Xiaoxia Wu, Yuan Xie, Yiran Chen, Hai Helen Li: Stacking magnetic random access memory atop microprocessors: an architecture-level evaluation. 213-220

Volume 5, Number 4, July 2011

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  Yocheved Dotan, Nadav Levison, David J. Lilja: Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computation. 221-230
• 
  George Rosario Jagadeesh, Thambipillai Srikanthan, C. M. Lim: Field programmable gate array-based acceleration of shortest-path computation. 231-237
• 
  W.-C. Wang, C.-Y. Hsu, James Chien-Mo Li, Y.-C. Sung, A. Rao, L.-T. Wang: Row-linear feedback shift register-column x-masking technique for simultaneous testing of many-core system chips. 238-246
• 
  Irith Pomeranz, Sudhakar M. Reddy: Two-dimensional partially functional broadside tests. 247-253
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  A. Z. Jooya, A. Baniasadi, M. Analoui: History-aware, resource-based dynamic scheduling for heterogeneous multi-core processors. 254-262
• 
  M. G. Mohammad: Fault model and test procedure for phase change memory. 263-270
• 
  Maria E. Angelopoulou, Christos-Savvas Bouganis, Peter Y. K. Cheung: Blur identification with assumption validation for sensor-based video reconstruction and its implementation on field programmable gate array. 271-286
• 
  X. Zhou, P. Petrov: Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page table. 287-295
• 
  B. A. Al Jassani, N. Urquhart, A. E. A. Almaini: State assignment for sequential circuits using multi-objective genetic algorithm. 296-305
• 
  Sobeeh Almukhaizim, Ozgur Sinanoglu: Novel hazard-free majority voter for n-modular redundancy-based fault tolerance in asynchronous circuits. 306-315
• 
  Ken S. Stevens, Alexandre Yakovlev: Editorial - Selected papers from the 16th IEEE International Symposium on Asynchronous Circuits and Systems. 316-317
• 
  Mario R. Casu: Half-buffer retiming and token cages for synchronous elastic circuits. 318-330
• 
  W. B. Toms, David A. Edwards: Indicating combinational logic decomposition. 331-341
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  Omer Can Akgun, Joachim Neves Rodrigues, Jens Sparsø: Energy-minimum sub-threshold self-timed circuits using current-sensing completion detection. 342-353

Volume 5, Number 5, September 2011

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  Giacomo Paci, Davide Bertozzi, Luca Benini: Variability compensation for full-swing against low-swing on-chip communication. 355-365
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  Fotis Plessas, Alexis Alexandropoulos, Sotiris Koutsomitsos, Efthimios Davrazos, Michael K. Birbas: Advanced calibration techniques for high-speed source-synchronous interfaces. 366-374
• 
  Hui Shao, X. Li, Chi-Ying Tsui: Low energy multi-stage level converter for sub-threshold logic. 375-385
• 
  Noureddine Chabini, Marilyn Wolf: Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction bus. 386-392
• 
  Amir Kaivani, Adel Hosseiny, Ghassem Jaberipur: Improving the speed of decimal division. 393-404
• 
  Irith Pomeranz, Sudhakar M. Reddy: Sizes of test sets for path delay faults using strong and weak non-robust tests. 405-414
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  Irith Pomeranz, Sudhakar M. Reddy: Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. 415-423

Volume 5, Number 6, November 2011

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  Andrey Mokhov, Arseniy Alekseyev, Alex Yakovlev: Encoding of processor instruction sets with explicit concurrency control. 427-439
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  Dominic Wist, M. Schaefer, Walter Vogler, Ralf Wollowski: Signal transition graph decomposition: internal communication for speed independent circuit implementation. 440-451
• 
  W. Song, D. Edwards, Z. Liu, S. Dasgupta: Routing of asynchronous Clos networks. 452-467
• 
  Matthias Raffelsieper, Mohammad Reza Mousavi, Hans Zantema: Long-run order-independence of vector-based transition systems. 468-478
• 
  Tuomas Launiainen, Keijo Heljanko, Tommi A. Junttila: Efficient model checking of PSL safety properties. 479-492

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